/dragonfly/sys/dev/drm/amd/display/dc/inc/ |
H A D | reg_helper.h | 69 FN(reg, f1), v1,\ 70 FN(reg, f2), v2) 74 FN(reg, f1), v1,\ 75 FN(reg, f2), v2,\ 76 FN(reg, f3), v3) 83 FN(reg, f4), v4) 92 FN(reg, f5), v5) 102 FN(reg, f6), v6) 113 FN(reg, f7), v7) 125 FN(reg, f8), v8) [all …]
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/dragonfly/sys/dev/netif/ix/ |
H A D | ixgbe_dcb_82599.c | 125 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local 143 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() 236 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82599() local 254 reg = 0; in ixgbe_dcb_config_tx_data_arbiter_82599() 384 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82599() local 510 u32 reg; in ixgbe_dcb_config_82599() local 525 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599() 531 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599() 540 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599() 547 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) | in ixgbe_dcb_config_82599() [all …]
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H A D | ixgbe_dcb_82598.c | 123 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local 135 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598() 137 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598() 149 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598() 182 u32 reg, max_credits; in ixgbe_dcb_config_tx_desc_arbiter_82598() local 189 reg |= IXGBE_DPMCS_TSOEF; in ixgbe_dcb_config_tx_desc_arbiter_82598() 200 reg |= refill[i]; in ixgbe_dcb_config_tx_desc_arbiter_82598() 229 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82598() local 242 reg = refill[i]; in ixgbe_dcb_config_tx_data_arbiter_82598() 272 u32 fcrtl, reg; in ixgbe_dcb_config_pfc_82598() local [all …]
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/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
H A D | smu_helper.h | 112 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument 113 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK argument 117 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) 127 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) 131 reg, field) 135 reg, field) 139 cgs_read_register(device, mm##reg), reg, field, fieldval)) 144 reg, field, fieldval)) 149 reg, field, fieldval)) 160 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) [all …]
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | soc15_common.h | 28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument 31 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 32 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ 33 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 36 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 39 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) 42 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 45 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 48 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) 52 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ [all …]
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/dragonfly/contrib/gcc-4.7/libgcc/config/i386/ |
H A D | dragonfly-unwind.h | 14 #define REG_NAME(reg) sf_uc.uc_mcontext.mc_## reg argument 58 fs->regs.reg[0].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 60 fs->regs.reg[1].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 62 fs->regs.reg[2].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 64 fs->regs.reg[3].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 66 fs->regs.reg[4].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 68 fs->regs.reg[5].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 70 fs->regs.reg[6].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 72 fs->regs.reg[8].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 74 fs->regs.reg[9].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() [all …]
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/dragonfly/contrib/gcc-8.0/gcc/ |
H A D | lra-remat.c | 307 for (reg = id->regs; reg != NULL; reg = reg->next) in operand_to_remat() 343 for (reg = id->regs; reg != NULL; reg = reg->next) in operand_to_remat() 624 for (reg = id->regs; reg != NULL; reg = reg->next) in set_bb_regs() 710 reg = reg->next) in call_used_input_regno_present_p() 733 for (reg = id->regs; reg != NULL; reg = reg->next) in calculate_livein_cands() 861 for (reg = id->regs; reg != NULL; reg = reg->next) in cand_trans_fun() 1140 for (reg = cand_id->regs; reg != NULL; reg = reg->next) in do_remat() 1256 for (reg = id->regs; reg != NULL; reg = reg->next) in do_remat() 1267 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) in do_remat() 1272 for (reg = id->regs; reg != NULL; reg = reg->next) in do_remat() [all …]
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H A D | reg-stack.c | 2544 for (reg = 0; reg <= new_stack->top; reg++) in change_stack() 2567 pops[reg] = reg; in change_stack() 2575 for (reg = 0; reg < new_stack->top; reg++) in change_stack() 2608 for (reg = 0; reg <= old->top; reg++) in change_stack() 2662 for (reg = new_stack->top; reg >= 0; reg--) in change_stack() 2676 for (reg = new_stack->top; reg >= 0; reg--) in change_stack() 2677 if (new_stack->reg[reg] != old->reg[reg]) in change_stack() 2687 for (reg = old->top; reg >= 0; reg--) in change_stack() 2688 gcc_assert (old->reg[reg] == new_stack->reg[reg]); in change_stack() 2822 for (reg = 0; reg <= src_stack->top; ++reg) in propagate_stack() [all …]
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H A D | hsa-regalloc.c | 184 if (reg) in insn_reg_addr() 314 reg->m_lr_end = end; in note_lr_end() 399 cand = reg; in spill_at_interval() 604 if (!reg) in linear_scan_regalloc() 620 reg->m_order, reg->m_lr_begin, reg->m_lr_end); in linear_scan_regalloc() 621 if (reg->m_reg_class) in linear_scan_regalloc() 622 fprintf (dump_file, "$%c%i", reg->m_reg_class, reg->m_hard_num); in linear_scan_regalloc() 657 if (!reg) in linear_scan_regalloc() 660 reg->m_lr_begin, reg->m_lr_end); in linear_scan_regalloc() 661 if (reg->m_reg_class) in linear_scan_regalloc() [all …]
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/dragonfly/contrib/gcc-8.0/libgcc/config/i386/ |
H A D | dragonfly-unwind.h | 40 #define REG_NAME(reg) sf_uc.uc_mcontext.mc_## reg argument 105 fs->regs.reg[0].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 107 fs->regs.reg[1].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 109 fs->regs.reg[2].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 111 fs->regs.reg[3].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 113 fs->regs.reg[4].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 115 fs->regs.reg[5].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 117 fs->regs.reg[6].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 119 fs->regs.reg[8].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() 121 fs->regs.reg[9].how = REG_SAVED_OFFSET; in x86_64_dragonfly_fallback_frame_state() [all …]
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/dragonfly/contrib/gdb-7/gdb/ |
H A D | user-regs.c | 69 reg->name = name; in append_user_reg() 70 reg->read = read; in append_user_reg() 71 reg->baton = baton; in append_user_reg() 72 reg->next = NULL; in append_user_reg() 104 for (reg = builtin_user_regs.first; reg != NULL; reg = reg->next) in user_regs_init() 105 append_user_reg (regs, reg->name, reg->read, reg->baton, in user_regs_init() 160 for (nr = 0, reg = regs->first; reg != NULL; reg = reg->next, nr++) in user_reg_map_name_to_regnum() 179 for (reg = regs->first; reg != NULL; reg = reg->next) in usernum_to_user_reg() 182 return reg; in usernum_to_user_reg() 204 return reg->name; in user_reg_map_regnum_to_name() [all …]
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H A D | dwarf2-frame.c | 252 memcpy (reg, rs->reg, size); in dwarf2_frame_state_copy_regs() 331 fs->regs.reg[reg] = fs->initial.reg[reg]; in dwarf2_restore_rule() 432 fs->regs.reg[reg].loc.offset = offset; in execute_cfa_program() 505 fs->regs.reg[reg].loc.reg = utmp; in execute_cfa_program() 583 fs->regs.reg[reg].loc.exp = insn_ptr; in execute_cfa_program() 584 fs->regs.reg[reg].exp_len = utmp; in execute_cfa_program() 622 fs->regs.reg[reg].exp_len = utmp; in execute_cfa_program() 654 for (reg = 8; reg < 16; reg++) in execute_cfa_program() 657 fs->regs.reg[reg].loc.reg = reg + 16; in execute_cfa_program() 659 for (reg = 16; reg < 32; reg++) in execute_cfa_program() [all …]
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/dragonfly/contrib/gcc-8.0/libgcc/ |
H A D | unwind-dw2.c | 989 fs->regs.reg[reg].how = REG_UNSAVED; in execute_cfa_program() 1034 fs->regs.reg[reg].how = REG_UNSAVED; in execute_cfa_program() 1063 fs->regs.reg[reg].loc.reg = (_Unwind_Word)reg2; in execute_cfa_program() 1205 for (reg = 16; reg < 32; ++reg) in execute_cfa_program() 1208 fs->regs.reg[reg].loc.offset = (reg - 16) * sizeof (void *); in execute_cfa_program() 1348 for (reg = 0; reg < PRE_GCC3_DWARF_FRAME_REGISTERS + 1; reg++) in __frame_state_for() 1350 state_in->saved[reg] = fs.regs.reg[reg].how; in __frame_state_for() 1354 state_in->reg_or_offset[reg] = fs.regs.reg[reg].loc.reg; in __frame_state_for() 1357 state_in->reg_or_offset[reg] = fs.regs.reg[reg].loc.offset; in __frame_state_for() 1463 fs->regs.reg[i].loc.reg)); in uw_update_context_1() [all …]
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/dragonfly/sys/dev/netif/vge/ |
H A D | if_vgevar.h | 143 #define CSR_READ_4(sc, reg) \ argument 145 #define CSR_READ_2(sc, reg) \ argument 147 #define CSR_READ_1(sc, reg) \ argument 150 #define CSR_SETBIT_1(sc, reg, x) \ argument 151 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 152 #define CSR_SETBIT_2(sc, reg, x) \ argument 153 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 155 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 158 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 160 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) [all …]
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/dragonfly/sys/dev/virtual/nvmm/x86/ |
H A D | nvmm_x86_vmxfunc.S | 85 #define GUEST_SAVE_GPRS(reg) \ argument 86 movq %rcx,(NVMM_X64_GPR_RCX * 8)(reg) ;\ 87 movq %rdx,(NVMM_X64_GPR_RDX * 8)(reg) ;\ 88 movq %rbx,(NVMM_X64_GPR_RBX * 8)(reg) ;\ 92 movq %r8,(NVMM_X64_GPR_R8 * 8)(reg) ;\ 93 movq %r9,(NVMM_X64_GPR_R9 * 8)(reg) ;\ 99 movq %r15,(NVMM_X64_GPR_R15 * 8)(reg) 101 #define GUEST_RESTORE_GPRS(reg) \ argument 108 movq (NVMM_X64_GPR_R8 * 8)(reg),%r8 ;\ 109 movq (NVMM_X64_GPR_R9 * 8)(reg),%r9 ;\ [all …]
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H A D | nvmm_x86_svmfunc.S | 114 #define GUEST_SAVE_GPRS(reg) \ argument 115 movq %rcx,(NVMM_X64_GPR_RCX * 8)(reg) ;\ 116 movq %rdx,(NVMM_X64_GPR_RDX * 8)(reg) ;\ 117 movq %rbx,(NVMM_X64_GPR_RBX * 8)(reg) ;\ 121 movq %r8,(NVMM_X64_GPR_R8 * 8)(reg) ;\ 122 movq %r9,(NVMM_X64_GPR_R9 * 8)(reg) ;\ 128 movq %r15,(NVMM_X64_GPR_R15 * 8)(reg) 130 #define GUEST_RESTORE_GPRS(reg) \ argument 137 movq (NVMM_X64_GPR_R8 * 8)(reg),%r8 ;\ 138 movq (NVMM_X64_GPR_R9 * 8)(reg),%r9 ;\ [all …]
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/dragonfly/contrib/gcc-4.7/gcc/ |
H A D | reg-stack.c | 2462 for (reg = 0; reg <= new_stack->top; reg++) in change_stack() 2485 pops[reg] = reg; in change_stack() 2493 for (reg = 0; reg < new_stack->top; reg++) in change_stack() 2526 for (reg = 0; reg <= old->top; reg++) in change_stack() 2580 for (reg = new_stack->top; reg >= 0; reg--) in change_stack() 2594 for (reg = new_stack->top; reg >= 0; reg--) in change_stack() 2595 if (new_stack->reg[reg] != old->reg[reg]) in change_stack() 2605 for (reg = old->top; reg >= 0; reg--) in change_stack() 2606 gcc_assert (old->reg[reg] == new_stack->reg[reg]); in change_stack() 2732 for (reg = 0; reg <= src_stack->top; ++reg) in propagate_stack() [all …]
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/dragonfly/contrib/wpa_supplicant/src/wps/ |
H A D | wps_registrar.c | 602 if (reg->pbc) in wps_build_sel_reg_config_methods() 671 struct wps_registrar *reg = os_zalloc(sizeof(*reg)); in wps_registrar_init() local 722 return reg; in wps_registrar_init() 756 os_free(reg); in wps_registrar_deinit() 823 reg->pbc = 0; in wps_registrar_add_pin() 1182 reg->enrollee_seen_cb(reg->cb_ctx, addr, attr.uuid_e, in wps_registrar_probe_req_rx() 1246 reg->pin_needed_cb(reg->cb_ctx, uuid_e, dev); in wps_cb_pin_needed() 1284 reg->selected_registrar, reg->wps->config_methods, in wps_cb_set_sel_reg() 1287 reg->set_sel_reg_cb(reg->cb_ctx, reg->selected_registrar, in wps_cb_set_sel_reg() 3561 reg->sel_reg_union = reg->selected_registrar; in wps_registrar_selected_registrar_changed() [all …]
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/dragonfly/contrib/gcc-4.7/libgcc/ |
H A D | unwind-dw2.c | 1011 fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.reg = in execute_cfa_program() 1131 for (reg = 16; reg < 32; ++reg) in execute_cfa_program() 1133 fs->regs.reg[reg].how = REG_SAVED_OFFSET; in execute_cfa_program() 1134 fs->regs.reg[reg].loc.offset = (reg - 16) * sizeof (void *); in execute_cfa_program() 1255 int reg; in __frame_state_for() local 1270 for (reg = 0; reg < PRE_GCC3_DWARF_FRAME_REGISTERS + 1; reg++) in __frame_state_for() 1272 state_in->saved[reg] = fs.regs.reg[reg].how; in __frame_state_for() 1276 state_in->reg_or_offset[reg] = fs.regs.reg[reg].loc.reg; in __frame_state_for() 1279 state_in->reg_or_offset[reg] = fs.regs.reg[reg].loc.offset; in __frame_state_for() 1385 fs->regs.reg[i].loc.reg)); in uw_update_context_1() [all …]
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/dragonfly/sys/dev/netif/sk/ |
H A D | if_skreg.h | 75 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) argument 78 #define SK_REG(reg) ((reg) & SK_REG_MASK) argument 549 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) argument 1176 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x)) 1179 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x)) 1182 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x)) 1185 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x)) 1205 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x)) 1208 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x)) 1211 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x)) [all …]
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/dragonfly/sys/bus/pci/x86_64/ |
H A D | pci_cfgreg.c | 75 unsigned reg, unsigned bytes); 152 if (reg == PCIR_INTLINE && bytes == 1) { in pci_cfgregread() 190 (unsigned)reg <= PCI_REGMAX && in pci_cfgenable() 193 (reg & (bytes - 1)) == 0) { in pci_cfgenable() 195 (func << 8) | (reg & ~0x03)); in pci_cfgenable() 196 dataport = CONF1_DATA_PORT + (reg & 0x03); in pci_cfgenable() 308 #define PCIE_VADDR(base, reg, bus, slot, func) \ argument 313 ((reg) & 0xfff))) 323 func > PCI_FUNCMAX || reg > PCIE_REGMAX) in pciereg_cfgread() 326 va = PCIE_VADDR(pcie_base, reg, bus, slot, func); in pciereg_cfgread() [all …]
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/dragonfly/sys/dev/netif/mii_layer/ |
H A D | e1000phy.c | 197 uint16_t reg, page; in e1000phy_reset() local 199 reg = PHY_READ(sc, E1000_SCR); in e1000phy_reset() 235 reg |= E1000_SCR_AUTO_MDIX; in e1000phy_reset() 238 reg |= E1000_SCR_LPNP; in e1000phy_reset() 293 reg |= E1000_ESCR_TX_CLK_25; in e1000phy_reset() 299 reg = PHY_READ(sc, E1000_CR); in e1000phy_reset() 300 reg |= E1000_CR_RESET; in e1000phy_reset() 301 PHY_WRITE(sc, E1000_CR, reg); in e1000phy_reset() 309 int reg; in e1000phy_service() local 434 if (reg & BMSR_LINK) { in e1000phy_service() [all …]
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/dragonfly/sys/bus/gpio/gpio_intel/ |
H A D | gpio_cherryview.c | 243 uint32_t reg, reg1, reg2; in gpio_cherryview_map_intr() local 384 uint32_t reg, intcfg, gpiocfg; in gpio_cherryview_unmap_intr() local 403 reg |= intcfg; in gpio_cherryview_unmap_intr() 411 reg |= gpiocfg; in gpio_cherryview_unmap_intr() 420 uint32_t reg; in gpio_cherryview_enable_intr() local 429 reg |= (1U << map->intidx); in gpio_cherryview_enable_intr() 437 uint32_t reg; in gpio_cherryview_disable_intr() local 443 reg &= ~(1U << map->intidx); in gpio_cherryview_disable_intr() 479 uint32_t reg; in gpio_cherryview_read_pin() local 498 uint32_t reg; in gpio_cherryview_write_pin() local [all …]
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/dragonfly/sys/dev/netif/ig_hal/ |
H A D | e1000_osdep.h | 94 ? reg : e1000_translate_register_82542(reg)) 110 #define E1000_READ_REG(hw, reg) \ argument 113 E1000_REGISTER(hw, reg)) 115 #define E1000_WRITE_REG(hw, reg, value) \ argument 118 E1000_REGISTER(hw, reg), value) 120 #define E1000_READ_REG_ARRAY(hw, reg, index) \ argument 136 E1000_REGISTER(hw, reg) + index) 141 E1000_REGISTER(hw, reg) + index, value) 151 (hw)->io_base, reg); \ 156 #define E1000_READ_FLASH_REG(hw, reg) \ argument [all …]
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/dragonfly/sys/dev/drm/i915/ |
H A D | intel_sideband.c | 113 SB_CRRDDA_NP, reg, &val); in vlv_bunit_read() 121 SB_CRWRDA_NP, reg, &val); in vlv_bunit_write() 142 SB_CRRDDA_NP, reg, &val); in vlv_iosf_sb_read() 150 SB_CRWRDA_NP, reg, &val); in vlv_iosf_sb_write() 157 SB_CRRDDA_NP, reg, &val); in vlv_cck_read() 164 SB_CRWRDA_NP, reg, &val); in vlv_cck_write() 186 SB_MRD_NP, reg, &val); in vlv_dpio_read() 201 SB_MWR_NP, reg, &val); in vlv_dpio_write() 278 value, reg); in intel_sbi_write() 287 reg, &val); in vlv_flisdsi_read() [all …]
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