Searched refs:sdma_offsets (Results 1 – 2 of 2) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | sdma_v3_0.c | 71 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable 581 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable() 588 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable() 590 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable() 600 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable() 665 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in sdma_v3_0_gfx_resume() 683 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume() 685 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume() 720 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume() 807 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); in sdma_v3_0_load_microcode() [all …]
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H A D | sdma_v2_4.c | 57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable 392 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable() 421 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume() 426 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in sdma_v2_4_gfx_resume() 443 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume() 444 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume() 445 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume() 446 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume() 449 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], in sdma_v2_4_gfx_resume() 451 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], in sdma_v2_4_gfx_resume() [all …]
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