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Searched refs:set_wptr (Results 1 – 15 of 15) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dradeon_asic.c195 .set_wptr = &r100_gfx_set_wptr,
345 .set_wptr = &r100_gfx_set_wptr,
359 .set_wptr = &r100_gfx_set_wptr,
916 .set_wptr = &r600_gfx_set_wptr,
929 .set_wptr = &r600_dma_set_wptr,
1014 .set_wptr = &uvd_v1_0_set_wptr,
1213 .set_wptr = &uvd_v1_0_set_wptr,
1320 .set_wptr = &r600_gfx_set_wptr,
1333 .set_wptr = &r600_dma_set_wptr,
1657 .set_wptr = &uvd_v1_0_set_wptr,
[all …]
H A Dradeon.h1825 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); member
2748 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_ring.h123 void (*set_wptr)(struct amdgpu_ring *ring); member
H A Dvce_v3_0.c901 .set_wptr = vce_v3_0_ring_set_wptr,
924 .set_wptr = vce_v3_0_ring_set_wptr,
H A Duvd_v6_0.c1536 .set_wptr = uvd_v6_0_ring_set_wptr,
1561 .set_wptr = uvd_v6_0_ring_set_wptr,
1589 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
H A Dvcn_v1_0.c1663 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1696 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1728 .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
H A Duvd_v5_0.c864 .set_wptr = uvd_v5_0_ring_set_wptr,
H A Duvd_v7_0.c1781 .set_wptr = uvd_v7_0_ring_set_wptr,
1813 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
H A Dvce_v4_0.c1071 .set_wptr = vce_v4_0_ring_set_wptr,
H A Dsdma_v2_4.c1192 .set_wptr = sdma_v2_4_ring_set_wptr,
H A Dsdma_v3_0.c1632 .set_wptr = sdma_v3_0_ring_set_wptr,
H A Dsdma_v4_0.c1630 .set_wptr = sdma_v4_0_ring_set_wptr,
H A Dgfx_v9_0.c4629 .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4679 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4714 .set_wptr = gfx_v9_0_ring_set_wptr_compute,
H A Damdgpu.h1744 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
H A Dgfx_v8_0.c7170 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
7214 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
7244 .set_wptr = gfx_v8_0_ring_set_wptr_compute,