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Searched refs:smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_default.h4582 #define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b macro
H A Dnbio_6_1_default.h3082 #define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b macro