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Searched refs:vddc_dependency_on_sclk (Results 1 – 19 of 19) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu8_hwmgr.c104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
260 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
558 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit()
682 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit()
1141 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels()
1340 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_dpm_get_pp_table_entry_callback()
1513 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_print_clock_levels()
1611 table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_clock_by_type()
1630 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_max_high_clocks()
[all …]
H A Dprocesspptables.c1238 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1334 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency()
1366 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency()
1367 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency()
1370 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency()
1674 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize()
1675 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
H A Dppatomctrl.c1131 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv()
1132 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv()
1138 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv()
1147 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
H A Dsmu7_hwmgr.c670 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
2406 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); in smu7_patch_dependency_tables_with_leakage()
2462 …clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_set_private_data_based_on_pptable_v0()
2759 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
2761 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { in smu7_get_profiling_clk()
2762 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; in smu7_get_profiling_clk()
2769 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; in smu7_get_profiling_clk()
2773 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; in smu7_get_profiling_clk()
4653 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_get_sclks()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Diceland_smumgr.c540 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in iceland_get_std_voltage_value_sidd()
554 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
555 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd()
574 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in iceland_get_std_voltage_value_sidd()
575 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in iceland_get_std_voltage_value_sidd()
734 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
741 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in iceland_populate_ulv_level()
745 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in iceland_populate_ulv_level()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
1825 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in iceland_populate_smc_initial_state()
[all …]
H A Dci_smumgr.c417 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
771 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in ci_get_std_voltage_value_sidd()
780 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
781 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
796 …for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) { in ci_get_std_voltage_value_sidd()
797 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) { in ci_get_std_voltage_value_sidd()
965 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
972 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v) in ci_populate_ulv_level()
976 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage) in ci_populate_ulv_level()
1857 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count); in ci_populate_smc_initial_state()
[all …]
/dragonfly/sys/dev/drm/radeon/
H A Dr600_dpm.c927 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table()
939 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
950 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
962 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
1303 kfree(dyn_state->vddc_dependency_on_sclk.entries); in r600_free_extended_power_table()
H A Dkv_dpm.c553 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
575 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
716 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
1077 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1709 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
2104 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2145 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2349 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
H A Dci_dpm.c280 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
2371 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2377 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2394 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2628 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
3175 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3262 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3479 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3822 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
4950 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
[all …]
H A Dbtc_dpm.c2206 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
2215 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
2224 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in btc_apply_state_adjust_rules()
H A Dsi_dpm.c3047 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3153 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
4156 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4159 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4161 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4174 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4176 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
5902 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
H A Dradeon_atombios.c3295 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in radeon_atom_get_voltage_evv()
3299 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in radeon_atom_get_voltage_evv()
3311 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in radeon_atom_get_voltage_evv()
H A Dni_dpm.c873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
H A Dradeon.h1484 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; member
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_dpm.h194 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; member
H A Damdgpu_atombios.c1360 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in amdgpu_atombios_get_voltage_evv()
1364 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in amdgpu_atombios_get_voltage_evv()
1376 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in amdgpu_atombios_get_voltage_evv()
H A Damdgpu_dpm.c390 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
779 kfree(dyn_state->vddc_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()
H A Dsi_dpm.c3506 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3612 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
4619 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4622 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4624 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4637 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4639 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
6355 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dhwmgr.h594 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; member