Searched refs:vlv_cck_read (Results 1 – 6 of 6) sorted by relevance
/dragonfly/sys/dev/drm/i915/ |
H A D | intel_dsi_pll.c | 166 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & in vlv_enable_dsi_pll() 187 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in vlv_disable_dsi_pll() 278 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in vlv_dsi_get_pclk() 279 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); in vlv_dsi_get_pclk()
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H A D | intel_sideband.c | 153 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) in vlv_cck_read() function
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H A D | intel_cdclk.c | 527 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk() 532 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
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H A D | i915_drv.h | 4154 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
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H A D | intel_display.c | 169 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & in vlv_get_hpll_vco() 183 val = vlv_cck_read(dev_priv, reg); in vlv_get_cck_clock() 1098 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in assert_dsi_pll()
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H A D | intel_pm.c | 7195 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); in cherryview_init_gt_powersave()
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