Searched refs:vlv_dpio_read (Results 1 – 5 of 5) sorted by relevance
/dragonfly/sys/dev/drm/i915/ |
H A D | intel_dpio_phy.c | 654 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level() 668 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level() 674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level() 745 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset() 761 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset() 810 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_pre_pll_enable() 818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_phy_pre_pll_enable() 828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_phy_pre_pll_enable() 851 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_phy_pre_pll_enable() 963 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_post_pll_disable() [all …]
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H A D | intel_sideband.c | 181 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg) in vlv_dpio_read() function
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H A D | intel_runtime_pm.c | 1185 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable() 1191 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable() 1200 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable() 1269 val = vlv_dpio_read(dev_priv, pipe, reg); in assert_chv_phy_powergate()
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H A D | intel_display.c | 1450 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in _chv_enable_pll() 1642 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll() 6445 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp() 6450 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp() 6455 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp() 6459 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp() 6606 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll() 6658 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll() 6767 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | in chv_prepare_pll() 7373 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get() [all …]
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H A D | i915_drv.h | 4160 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);
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