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Searched refs:vlv_dpio_write (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_dpio_phy.c671 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
750 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
767 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
816 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_phy_pre_pll_enable()
856 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_phy_pre_pll_enable()
894 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_phy_pre_encoder_enable()
920 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), in chv_phy_pre_encoder_enable()
928 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), in chv_phy_pre_encoder_enable()
999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), in vlv_set_phy_signal_level()
1024 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_phy_pre_pll_enable()
[all …]
H A Dintel_sideband.c198 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val) in vlv_dpio_write() function
H A Dintel_display.c6453 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
6611 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); in vlv_prepare_pll()
6634 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
6637 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
6643 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6646 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6651 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6654 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6701 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), in chv_prepare_pll()
6711 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), in chv_prepare_pll()
[all …]
H A Dintel_runtime_pm.c1188 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); in chv_dpio_cmn_power_well_enable()
1193 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); in chv_dpio_cmn_power_well_enable()
1202 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); in chv_dpio_cmn_power_well_enable()
H A Di915_drv.h4161 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);