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Searched refs:vtaps (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_dscl.c464 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps) in dpp1_dscl_is_lb_conf_valid() argument
467 return vtaps <= (num_partitions - ceil_vratio + 2); in dpp1_dscl_is_lb_conf_valid()
469 return vtaps <= num_partitions; in dpp1_dscl_is_lb_conf_valid()
477 int vtaps = scl_data->taps.v_taps; in dpp1_dscl_find_lb_memory_config() local
492 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
499 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
508 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
517 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) in dpp1_dscl_find_lb_memory_config()
H A Ddcn10_dpp.h1386 int vtaps);
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
H A Ddcn_calc_auto.c99 v->vtaps[k] = v->override_vta_ps[k]; in scaler_settings_calculation()
102 v->vtaps[k] = v->acceptable_quality_vta_ps; in scaler_settings_calculation()
331 …v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(… in mode_support_and_system_configuration()
427 …v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ra… in mode_support_and_system_configuration()
554 …(v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); in mode_support_and_system_configuration()
747 …v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) /… in mode_support_and_system_configuration()
759 …v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio… in mode_support_and_system_configuration()
1165 …v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1571 …v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k]… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1582 …v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_out… in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
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H A Ddcn_calcs.c380 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
/dragonfly/sys/dev/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h279 unsigned int vtaps; member
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c694 u32 vtaps; /* vertical scaler taps */ member
897 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v10_0_latency_watermark()
898 (wm->vtaps >= 5) || in dce_v10_0_latency_watermark()
987 if (lb_partitions <= (wm->vtaps + 1)) in dce_v10_0_check_latency_hiding()
1049 wm_high.vtaps = 1; in dce_v10_0_program_watermarks()
1051 wm_high.vtaps = 2; in dce_v10_0_program_watermarks()
1088 wm_low.vtaps = 1; in dce_v10_0_program_watermarks()
1090 wm_low.vtaps = 2; in dce_v10_0_program_watermarks()
H A Ddce_v11_0.c720 u32 vtaps; /* vertical scaler taps */ member
923 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v11_0_latency_watermark()
924 (wm->vtaps >= 5) || in dce_v11_0_latency_watermark()
1013 if (lb_partitions <= (wm->vtaps + 1)) in dce_v11_0_check_latency_hiding()
1075 wm_high.vtaps = 1; in dce_v11_0_program_watermarks()
1077 wm_high.vtaps = 2; in dce_v11_0_program_watermarks()
1114 wm_low.vtaps = 1; in dce_v11_0_program_watermarks()
1116 wm_low.vtaps = 2; in dce_v11_0_program_watermarks()
/dragonfly/sys/dev/drm/radeon/
H A Devergreen.c1926 u32 vtaps; /* vertical scaler taps */ member
2063 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in evergreen_latency_watermark()
2064 (wm->vtaps >= 5) || in evergreen_latency_watermark()
2120 if (lb_partitions <= (wm->vtaps + 1)) in evergreen_check_latency_hiding()
2180 wm_high.vtaps = 1; in evergreen_program_watermarks()
2182 wm_high.vtaps = 2; in evergreen_program_watermarks()
2207 wm_low.vtaps = 1; in evergreen_program_watermarks()
2209 wm_low.vtaps = 2; in evergreen_program_watermarks()
H A Dsi.c2056 u32 vtaps; /* vertical scaler taps */ member
2211 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce6_latency_watermark()
2212 (wm->vtaps >= 5) || in dce6_latency_watermark()
2270 if (lb_partitions <= (wm->vtaps + 1)) in dce6_check_latency_hiding()
2333 wm_high.vtaps = 1; in dce6_program_watermarks()
2335 wm_high.vtaps = 2; in dce6_program_watermarks()
2360 wm_low.vtaps = 1; in dce6_program_watermarks()
2362 wm_low.vtaps = 2; in dce6_program_watermarks()
H A Dcik.c8897 u32 vtaps; /* vertical scaler taps */ member
9100 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce8_latency_watermark()
9101 (wm->vtaps >= 5) || in dce8_latency_watermark()
9190 if (lb_partitions <= (wm->vtaps + 1)) in dce8_check_latency_hiding()
9253 wm_high.vtaps = 1; in dce8_program_watermarks()
9255 wm_high.vtaps = 2; in dce8_program_watermarks()
9293 wm_low.vtaps = 1; in dce8_program_watermarks()
9295 wm_low.vtaps = 2; in dce8_program_watermarks()
/dragonfly/sys/dev/drm/amd/display/dc/inc/
H A Ddcn_calcs.h203 float vtaps[number_of_planes_minus_one + 1]; member