1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Aleksandr Rybalko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __AR8X16_SWITCHREG_H__ 30 #define __AR8X16_SWITCHREG_H__ 31 32 /* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */ 33 /* 34 * Register manipulation macros that expect bit field defines 35 * to follow the convention that an _S suffix is appended for 36 * a shift count, while the field mask has no suffix. 37 */ 38 #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 39 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 40 41 /* XXX Linux define compatibility stuff */ 42 #define BIT(_m) (1UL << (_m)) 43 #define BITM(_count) ((1UL << (_count)) - 1) 44 #define BITS(_shift, _count) (BITM(_count) << (_shift)) 45 46 /* Atheros specific MII registers */ 47 #define MII_ATH_MMD_ADDR 0x0d 48 #define MII_ATH_MMD_DATA 0x0e 49 #define MII_ATH_DBG_ADDR 0x1d 50 #define MII_ATH_DBG_DATA 0x1e 51 52 #define AR8X16_REG_MASK_CTRL 0x0000 53 #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff 54 #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 55 #define AR8X16_MASK_CTRL_VER_SHIFT 8 56 #define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31) 57 58 #define AR8X16_REG_MODE 0x0008 59 /* DIR-615 E4 U-Boot */ 60 #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0 61 /* From Ubiquiti RSPRO */ 62 #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea 63 #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 64 /* AVM Fritz!Box 7390 */ 65 #define AR8X16_MODE_GMII 0x010e5b71 66 /* from avm_cpmac/linux_ar_reg.h */ 67 #define AR8X16_MODE_RESERVED 0x000e1b20 68 #define AR8X16_MODE_MAC0_GMII_EN (1u << 0) 69 #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1) 70 #define AR8X16_MODE_PHY4_GMII_EN (1u << 2) 71 #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3) 72 #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4) 73 #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6) 74 #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7) 75 #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14) 76 #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15) 77 #define AR8X16_MODE_TXDELAY_S0 (1u << 21) 78 #define AR8X16_MODE_TXDELAY_S1 (1u << 22) 79 #define AR8X16_MODE_RXDELAY_S0 (1u << 23) 80 #define AR8X16_MODE_LED_OPEN_EN (1u << 24) 81 #define AR8X16_MODE_SPI_EN (1u << 25) 82 #define AR8X16_MODE_RXDELAY_S1 (1u << 26) 83 #define AR8X16_MODE_POWER_ON_SEL (1u << 31) 84 85 #define AR8X16_REG_ISR 0x0010 86 #define AR8X16_REG_IMR 0x0014 87 88 #define AR8X16_REG_SW_MAC_ADDR0 0x0020 89 #define AR8X16_REG_SW_MAC_ADDR0_BYTE4 BITS(8, 8) 90 #define AR8X16_REG_SW_MAC_ADDR0_BYTE4_S 8 91 #define AR8X16_REG_SW_MAC_ADDR0_BYTE5 BITS(0, 8) 92 #define AR8X16_REG_SW_MAC_ADDR0_BYTE5_S 0 93 94 #define AR8X16_REG_SW_MAC_ADDR1 0x0024 95 #define AR8X16_REG_SW_MAC_ADDR1_BYTE0 BITS(24, 8) 96 #define AR8X16_REG_SW_MAC_ADDR1_BYTE0_S 24 97 #define AR8X16_REG_SW_MAC_ADDR1_BYTE1 BITS(16, 8) 98 #define AR8X16_REG_SW_MAC_ADDR1_BYTE1_S 16 99 #define AR8X16_REG_SW_MAC_ADDR1_BYTE2 BITS(8, 8) 100 #define AR8X16_REG_SW_MAC_ADDR1_BYTE2_S 8 101 #define AR8X16_REG_SW_MAC_ADDR1_BYTE3 BITS(0, 8) 102 #define AR8X16_REG_SW_MAC_ADDR1_BYTE3_S 0 103 104 #define AR8X16_REG_FLOOD_MASK 0x002c 105 #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26) 106 107 #define AR8X16_REG_GLOBAL_CTRL 0x0030 108 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff 109 #define AR8216_GLOBAL_CTRL_MTU_MASK_S 0 110 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff 111 #define AR8316_GLOBAL_CTRL_MTU_MASK_S 0 112 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff 113 #define AR8236_GLOBAL_CTRL_MTU_MASK_S 0 114 115 #define AR8X16_REG_VLAN_CTRL 0x0040 116 #define AR8X16_VLAN_OP 0x00000007 117 #define AR8X16_VLAN_OP_NOOP 0x0 118 #define AR8X16_VLAN_OP_FLUSH 0x1 119 #define AR8X16_VLAN_OP_LOAD 0x2 120 #define AR8X16_VLAN_OP_PURGE 0x3 121 #define AR8X16_VLAN_OP_REMOVE_PORT 0x4 122 #define AR8X16_VLAN_OP_GET_NEXT 0x5 123 #define AR8X16_VLAN_OP_GET 0x6 124 #define AR8X16_VLAN_ACTIVE (1 << 3) 125 #define AR8X16_VLAN_FULL (1 << 4) 126 #define AR8X16_VLAN_PORT 0x00000f00 127 #define AR8X16_VLAN_PORT_SHIFT 8 128 #define AR8X16_VLAN_VID 0x0fff0000 129 #define AR8X16_VLAN_VID_SHIFT 16 130 #define AR8X16_VLAN_PRIO 0x70000000 131 #define AR8X16_VLAN_PRIO_SHIFT 28 132 #define AR8X16_VLAN_PRIO_EN (1U << 31) 133 134 #define AR8X16_REG_VLAN_DATA 0x0044 135 #define AR8X16_VLAN_MEMBER 0x0000003f 136 #define AR8X16_VLAN_VALID (1 << 11) 137 138 #define AR8216_REG_ATU 0x0050 139 #define AR8216_ATU_OP BITS(0, 3) 140 #define AR8216_ATU_OP_NOOP 0x0 141 #define AR8216_ATU_OP_FLUSH 0x1 142 #define AR8216_ATU_OP_LOAD 0x2 143 #define AR8216_ATU_OP_PURGE 0x3 144 #define AR8216_ATU_OP_FLUSH_LOCKED 0x4 145 #define AR8216_ATU_OP_FLUSH_UNICAST 0x5 146 #define AR8216_ATU_OP_GET_NEXT 0x6 147 #define AR8216_ATU_ACTIVE BIT(3) 148 #define AR8216_ATU_PORT_NUM BITS(8, 4) 149 #define AR8216_ATU_PORT_NUM_S 8 150 #define AR8216_ATU_FULL_VIO BIT(12) 151 #define AR8216_ATU_ADDR5 BITS(16, 8) 152 #define AR8216_ATU_ADDR5_S 16 153 #define AR8216_ATU_ADDR4 BITS(24, 8) 154 #define AR8216_ATU_ADDR4_S 24 155 156 #define AR8216_REG_ATU_DATA 0x0054 157 #define AR8216_ATU_ADDR3 BITS(0, 8) 158 #define AR8216_ATU_ADDR3_S 0 159 #define AR8216_ATU_ADDR2 BITS(8, 8) 160 #define AR8216_ATU_ADDR2_S 8 161 #define AR8216_ATU_ADDR1 BITS(16, 8) 162 #define AR8216_ATU_ADDR1_S 16 163 #define AR8216_ATU_ADDR0 BITS(24, 8) 164 #define AR8216_ATU_ADDR0_S 24 165 166 #define AR8216_REG_ATU_CTRL2 0x0058 167 #define AR8216_ATU_CTRL2_DESPORT BITS(0, 5) 168 #define AR8216_ATU_CTRL2_DESPORT_S 0 169 #define AR934X_ATU_CROSS_STATE_PORT_EN BIT(8) 170 #define AR934X_ATU_HASH_HIGH_ADDR BIT(9) /* Used for CPU_FUNC (get_next_valid) */ 171 #define AR8216_ATU_CTRL2_AT_PRIORITY BITS(10, 2) 172 #define AR8216_ATU_CTRL2_AT_PRIORITY_EN BIT(12) 173 #define AR8216_ATU_CTRL2_MIRROR_EN BIT(13) 174 #define AR8216_ATU_CTRL2_SA_DROP_EN BIT(14) 175 #define AR934X_ATU_CTRL2_MAC_CLONE BIT(15) 176 #define AR8216_ATU_CTRL2_AT_STATUS BITS(16, 4) 177 #define AR8216_ATU_CTRL2_AT_STATUS_S 16 178 /* 179 * For at least the AR9340 - 180 * 0: empty 181 * 1-7: dynamic, valid 182 * 15: static, won't be aged 183 */ 184 #define AR8216_ATU_CTRL2_VLAN_LEAKY_EN BIT(24) 185 /* 186 * This defines whether this MAC will leak between VLANs; 187 * controlled by ARL_UNI_LEAKY_EN and ARL_MULTI_LEAKY_EN. 188 */ 189 #define AR8216_ATU_CTRL2_REDIRECT2CPU BIT(25) 190 #define AR8216_ATU_CTRL2_COPY2CPU BIT(26) 191 192 #define AR8216_REG_ATU_CTRL 0x005C 193 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) 194 #define AR8216_ATU_CTRL_AGE_TIME_S 0 195 #define AR8216_ATU_CTRL_AGE_EN BIT(17) 196 #define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18) 197 #define AR8216_ATU_CTRL_ARP_EN BIT(20) 198 199 #define AR8X16_REG_IP_PRIORITY_1 0x0060 200 #define AR8X16_REG_IP_PRIORITY_2 0x0064 201 #define AR8X16_REG_IP_PRIORITY_3 0x0068 202 #define AR8X16_REG_IP_PRIORITY_4 0x006C 203 204 #define AR8X16_REG_TAG_PRIO 0x0070 205 206 #define AR8X16_REG_SERVICE_TAG 0x0074 207 #define AR8X16_SERVICE_TAG_MASK 0x0000ffff 208 209 #define AR8X16_REG_CPU_PORT 0x0078 210 #define AR8X16_MIRROR_PORT_SHIFT 4 211 #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT) 212 #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT) 213 #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf) 214 #define AR8X16_CPU_PORT_EN (1 << 8) 215 216 #define AR8X16_REG_MIB_FUNC0 0x0080 217 #define AR8X16_MIB_TIMER_MASK 0x0000ffff 218 #define AR8X16_MIB_AT_HALF_EN (1 << 16) 219 #define AR8X16_MIB_BUSY (1 << 17) 220 #define AR8X16_MIB_FUNC_SHIFT 24 221 #define AR8X16_MIB_FUNC_NO_OP 0x0 222 #define AR8X16_MIB_FUNC_FLUSH 0x1 223 #define AR8X16_MIB_FUNC_CAPTURE 0x3 224 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ 225 226 #define AR934X_MIB_ENABLE (1 << 30) 227 228 #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 229 230 #define AR8X16_REG_MDIO_CTRL 0x0098 231 #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff 232 #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16 233 #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21 234 #define AR8X16_MDIO_CTRL_CMD_WRITE 0 235 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) 236 #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) 237 #define AR8X16_MDIO_CTRL_BUSY (1U << 31) 238 239 #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) 240 241 #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000) 242 #define AR8X16_PORT_STS_SPEED_MASK 0x00000003 243 #define AR8X16_PORT_STS_SPEED_10 0 244 #define AR8X16_PORT_STS_SPEED_100 1 245 #define AR8X16_PORT_STS_SPEED_1000 2 246 #define AR8X16_PORT_STS_TXMAC (1 << 2) 247 #define AR8X16_PORT_STS_RXMAC (1 << 3) 248 #define AR8X16_PORT_STS_TXFLOW (1 << 4) 249 #define AR8X16_PORT_STS_RXFLOW (1 << 5) 250 #define AR8X16_PORT_STS_DUPLEX (1 << 6) 251 #define AR8X16_PORT_STS_LINK_UP (1 << 8) 252 #define AR8X16_PORT_STS_LINK_AUTO (1 << 9) 253 #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10) 254 255 #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004) 256 #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007 257 #define AR8X16_PORT_CTRL_STATE_DISABLED 0 258 #define AR8X16_PORT_CTRL_STATE_BLOCK 1 259 #define AR8X16_PORT_CTRL_STATE_LISTEN 2 260 #define AR8X16_PORT_CTRL_STATE_LEARN 3 261 #define AR8X16_PORT_CTRL_STATE_FORWARD 4 262 #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7) 263 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8 264 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0 265 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1 266 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2 267 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3 268 #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10) 269 #define AR8X16_PORT_CTRL_HEADER (1 << 11) 270 #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12) 271 #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13) 272 #define AR8X16_PORT_CTRL_LEARN (1 << 14) 273 #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15) 274 #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16) 275 #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17) 276 277 #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008) 278 279 #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0 280 #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16 281 #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000 282 #define AR8X16_PORT_VLAN_MODE_SHIFT 30 283 #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0 284 #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1 285 #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2 286 #define AR8X16_PORT_VLAN_MODE_SECURE 3 287 288 #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c) 289 #define AR8X16_PORT_RATE_LIM_128KB 0 290 #define AR8X16_PORT_RATE_LIM_256KB 1 291 #define AR8X16_PORT_RATE_LIM_512KB 2 292 #define AR8X16_PORT_RATE_LIM_1MB 3 293 #define AR8X16_PORT_RATE_LIM_2MB 4 294 #define AR8X16_PORT_RATE_LIM_4MB 5 295 #define AR8X16_PORT_RATE_LIM_8MB 6 296 #define AR8X16_PORT_RATE_LIM_16MB 7 297 #define AR8X16_PORT_RATE_LIM_32MB 8 298 #define AR8X16_PORT_RATE_LIM_64MB 9 299 #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24) 300 #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23) 301 #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000 302 #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16 303 #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f 304 #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0 305 306 #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010) 307 308 #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100) 309 310 #define AR8X16_STATS_RXBROAD 0x0000 311 #define AR8X16_STATS_RXPAUSE 0x0004 312 #define AR8X16_STATS_RXMULTI 0x0008 313 #define AR8X16_STATS_RXFCSERR 0x000c 314 #define AR8X16_STATS_RXALIGNERR 0x0010 315 #define AR8X16_STATS_RXRUNT 0x0014 316 #define AR8X16_STATS_RXFRAGMENT 0x0018 317 #define AR8X16_STATS_RX64BYTE 0x001c 318 #define AR8X16_STATS_RX128BYTE 0x0020 319 #define AR8X16_STATS_RX256BYTE 0x0024 320 #define AR8X16_STATS_RX512BYTE 0x0028 321 #define AR8X16_STATS_RX1024BYTE 0x002c 322 #define AR8X16_STATS_RX1518BYTE 0x0030 323 #define AR8X16_STATS_RXMAXBYTE 0x0034 324 #define AR8X16_STATS_RXTOOLONG 0x0038 325 #define AR8X16_STATS_RXGOODBYTE 0x003c 326 #define AR8X16_STATS_RXBADBYTE 0x0044 327 #define AR8X16_STATS_RXOVERFLOW 0x004c 328 #define AR8X16_STATS_FILTERED 0x0050 329 #define AR8X16_STATS_TXBROAD 0x0054 330 #define AR8X16_STATS_TXPAUSE 0x0058 331 #define AR8X16_STATS_TXMULTI 0x005c 332 #define AR8X16_STATS_TXUNDERRUN 0x0060 333 #define AR8X16_STATS_TX64BYTE 0x0064 334 #define AR8X16_STATS_TX128BYTE 0x0068 335 #define AR8X16_STATS_TX256BYTE 0x006c 336 #define AR8X16_STATS_TX512BYTE 0x0070 337 #define AR8X16_STATS_TX1024BYTE 0x0074 338 #define AR8X16_STATS_TX1518BYTE 0x0078 339 #define AR8X16_STATS_TXMAXBYTE 0x007c 340 #define AR8X16_STATS_TXOVERSIZE 0x0080 341 #define AR8X16_STATS_TXBYTE 0x0084 342 #define AR8X16_STATS_TXCOLLISION 0x008c 343 #define AR8X16_STATS_TXABORTCOL 0x0090 344 #define AR8X16_STATS_TXMULTICOL 0x0094 345 #define AR8X16_STATS_TXSINGLECOL 0x0098 346 #define AR8X16_STATS_TXEXCDEFER 0x009c 347 #define AR8X16_STATS_TXDEFER 0x00a0 348 #define AR8X16_STATS_TXLATECOL 0x00a4 349 350 #define AR8X16_PORT_CPU 0 351 #define AR8X16_NUM_PORTS 6 352 #define AR8X16_NUM_PHYS 5 353 #define AR8X16_MAGIC 0xc000050e 354 355 #define AR8X16_PHY_ID1 0x004d 356 #define AR8X16_PHY_ID2 0xd041 357 358 #define AR8X16_PORT_MASK(_port) (1 << (_port)) 359 #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1) 360 #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port))) 361 362 #define AR8X16_MAX_VLANS 16 363 364 /* 365 * AR8327 specific registers 366 */ 367 #define AR8327_NUM_PORTS 7 368 #define AR8327_NUM_PHYS 5 369 #define AR8327_PORTS_ALL 0x7f 370 371 #define AR8327_PORT_GMAC0 0 372 #define AR8327_PORT_GMAC6 6 373 374 #define AR8327_REG_MASK 0x000 375 376 #define AR8327_REG_PAD0_MODE 0x004 377 #define AR8327_REG_PAD5_MODE 0x008 378 #define AR8327_REG_PAD6_MODE 0x00c 379 380 #define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0) 381 #define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1) 382 #define AR8327_PAD_MAC_MII_EN (1 << 2) 383 #define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4) 384 #define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5) 385 #define AR8327_PAD_MAC_GMII_EN (1 << 6) 386 #define AR8327_PAD_SGMII_EN (1 << 7) 387 #define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8) 388 #define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9) 389 #define AR8327_PAD_PHY_MII_EN (1 << 10) 390 #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11) 391 #define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12) 392 #define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13) 393 #define AR8327_PAD_PHY_GMII_EN (1 << 14) 394 #define AR8327_PAD_PHYX_GMII_EN (1 << 16) 395 #define AR8327_PAD_PHYX_RGMII_EN (1 << 17) 396 #define AR8327_PAD_PHYX_MII_EN (1 << 18) 397 #define AR8327_PAD_SGMII_DELAY_EN (1 << 19) 398 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) 399 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 400 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) 401 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 402 #define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24) 403 #define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25) 404 #define AR8327_PAD_RGMII_EN (1 << 26) 405 406 #define AR8327_REG_POWER_ON_STRIP 0x010 407 #define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31) 408 #define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24) 409 #define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7) 410 411 #define AR8327_REG_INT_STATUS0 0x020 412 #define AR8327_INT0_VT_DONE (1 << 20) 413 414 #define AR8327_REG_INT_STATUS1 0x024 415 #define AR8327_REG_INT_MASK0 0x028 416 #define AR8327_REG_INT_MASK1 0x02c 417 418 #define AR8327_REG_MODULE_EN 0x030 419 #define AR8327_MODULE_EN_MIB (1 << 0) 420 421 #define AR8327_REG_MIB_FUNC 0x034 422 #define AR8327_MIB_CPU_KEEP (1 << 20) 423 424 #define AR8327_REG_MDIO_CTRL 0x03c 425 426 #define AR8327_REG_SERVICE_TAG 0x048 427 #define AR8327_REG_LED_CTRL0 0x050 428 #define AR8327_REG_LED_CTRL1 0x054 429 #define AR8327_REG_LED_CTRL2 0x058 430 #define AR8327_REG_LED_CTRL3 0x05c 431 #define AR8327_REG_MAC_ADDR0 0x060 432 #define AR8327_REG_MAC_ADDR1 0x064 433 434 #define AR8327_REG_MAX_FRAME_SIZE 0x078 435 #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) 436 437 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 438 439 #define AR8327_REG_HEADER_CTRL 0x098 440 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) 441 442 #define AR8327_REG_SGMII_CTRL 0x0e0 443 #define AR8327_SGMII_CTRL_EN_PLL (1 << 1) 444 #define AR8327_SGMII_CTRL_EN_RX (1 << 2) 445 #define AR8327_SGMII_CTRL_EN_TX (1 << 3) 446 447 #define AR8327_REG_EEE_CTRL 0x100 448 #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) 449 450 #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) 451 #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) 452 #define AR8327_PORT_VLAN0_DEF_SVID_S 0 453 #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) 454 #define AR8327_PORT_VLAN0_DEF_CVID_S 16 455 456 #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) 457 #define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6) 458 #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) 459 #define AR8327_PORT_VLAN1_OUT_MODE_S 12 460 #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 461 #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 462 #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 463 #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 464 465 #define AR8327_REG_ATU_DATA0 0x600 466 #define AR8327_ATU_DATA0_MAC_ADDR3 BITS(0, 8) 467 #define AR8327_ATU_DATA0_MAC_ADDR3_S 0 468 #define AR8327_ATU_DATA0_MAC_ADDR2 BITS(8, 8) 469 #define AR8327_ATU_DATA0_MAC_ADDR2_S 8 470 #define AR8327_ATU_DATA0_MAC_ADDR1 BITS(16, 8) 471 #define AR8327_ATU_DATA0_MAC_ADDR1_S 16 472 #define AR8327_ATU_DATA0_MAC_ADDR0 BITS(24, 8) 473 #define AR8327_ATU_DATA0_MAC_ADDR0_S 24 474 475 #define AR8327_REG_ATU_DATA1 0x604 476 #define AR8327_ATU_DATA1_MAC_ADDR4 BITS(0, 8) 477 #define AR8327_ATU_DATA1_MAC_ADDR4_S 0 478 #define AR8327_ATU_DATA1_MAC_ADDR5 BITS(8, 8) 479 #define AR8327_ATU_DATA1_MAC_ADDR5_S 8 480 #define AR8327_ATU_DATA1_DEST_PORT BITS(16, 7) 481 #define AR8327_ATU_DATA1_DEST_PORT_S 16 482 #define AR8327_ATU_DATA1_CROSS_PORT_STATE_EN BIT(23) 483 #define AR8327_ATU_DATA1_PRI BITS(24, 3) 484 #define AR8327_ATU_DATA1_SVL_ENTRY BIT(27) 485 #define AR8327_ATU_DATA1_PRI_OVER_EN BIT(28) 486 #define AR8327_ATU_DATA1_MIRROR_EN BIT(29) 487 #define AR8327_ATU_DATA1_SA_DROP_EN BIT(30) 488 #define AR8327_ATU_DATA1_HASH_HIGH_ADDR BIT(31) 489 490 #define AR8327_REG_ATU_DATA2 0x608 491 #define AR8327_ATU_FUNC_DATA2_STATUS BITS(0, 4) 492 #define AR8327_ATU_FUNC_DATA2_STATUS_S 0 493 #define AR8327_ATU_FUNC_DATA2_VLAN_LEAKY_EN BIT(4) 494 #define AR8327_ATU_FUNC_DATA2_REDIRECT_TO_CPU BIT(5) 495 #define AR8327_ATU_FUNC_DATA2_COPY_TO_CPU BIT(6) 496 #define AR8327_ATU_FUNC_DATA2_SHORT_LOOP BIT(7) 497 #define AR8327_ATU_FUNC_DATA2_ATU_VID BITS(8, 12) 498 #define AR8327_ATU_FUNC_DATA2_ATU_VID_S 8 499 500 #define AR8327_REG_ATU_FUNC 0x60c 501 #define AR8327_ATU_FUNC_OP BITS(0, 4) 502 #define AR8327_ATU_FUNC_OP_NOOP 0x0 503 #define AR8327_ATU_FUNC_OP_FLUSH 0x1 504 #define AR8327_ATU_FUNC_OP_LOAD 0x2 505 #define AR8327_ATU_FUNC_OP_PURGE 0x3 506 #define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 507 #define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 508 #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 509 #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 510 #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 511 #define AR8327_ATU_FUNC_FLUSH_STATIC_EN BIT(4) 512 #define AR8327_ATU_FUNC_ENTRY_TYPE BIT(5) 513 #define AR8327_ATU_FUNC_PORT_NUM BITS(8, 4) 514 #define AR8327_ATU_FUNC_PORT_NUM_S 8 515 #define AR8327_ATU_FUNC_FULL_VIOLATION BIT(12) 516 #define AR8327_ATU_FUNC_MULTI_EN BIT(13) /* for GET_NEXT */ 517 #define AR8327_ATU_FUNC_PORT_EN BIT(14) /* for GET_NEXT */ 518 #define AR8327_ATU_FUNC_VID_EN BIT(15) /* for GET_NEXT */ 519 #define AR8327_ATU_FUNC_ATU_INDEX BITS(16, 5) 520 #define AR8327_ATU_FUNC_ATU_INDEX_S 16 521 #define AR8327_ATU_FUNC_TRUNK_PORT_NUM BITS(22, 3) /* for CHANGE_TRUNK */ 522 #define AR8327_ATU_FUNC_TRUNK_PORT_NUM_S 22 523 #define AR8327_ATU_FUNC_BUSY BIT(31) 524 525 #define AR8327_REG_VTU_FUNC0 0x0610 526 #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) 527 #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) 528 #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 529 #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 530 #define AR8327_VTU_FUNC0_EG_MODE_TAG 2 531 #define AR8327_VTU_FUNC0_EG_MODE_NOT 3 532 #define AR8327_VTU_FUNC0_IVL (1 << 19) 533 #define AR8327_VTU_FUNC0_VALID (1 << 20) 534 535 #define AR8327_REG_VTU_FUNC1 0x0614 536 #define AR8327_VTU_FUNC1_OP BITS(0, 3) 537 #define AR8327_VTU_FUNC1_OP_NOOP 0 538 #define AR8327_VTU_FUNC1_OP_FLUSH 1 539 #define AR8327_VTU_FUNC1_OP_LOAD 2 540 #define AR8327_VTU_FUNC1_OP_PURGE 3 541 #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 542 #define AR8327_VTU_FUNC1_OP_GET_NEXT 5 543 #define AR8327_VTU_FUNC1_OP_GET_ONE 6 544 #define AR8327_VTU_FUNC1_FULL (1 << 4) 545 #define AR8327_VTU_FUNC1_PORT (1 << 8, 4) 546 #define AR8327_VTU_FUNC1_PORT_S 8 547 #define AR8327_VTU_FUNC1_VID (1 << 16, 12) 548 #define AR8327_VTU_FUNC1_VID_S 16 549 #define AR8327_VTU_FUNC1_BUSY (1U << 31) 550 551 #define AR8327_REG_FWD_CTRL0 0x620 552 #define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10) 553 #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) 554 #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 555 556 #define AR8327_REG_FWD_CTRL1 0x624 557 #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) 558 #define AR8327_FWD_CTRL1_UC_FLOOD_S 0 559 #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) 560 #define AR8327_FWD_CTRL1_MC_FLOOD_S 8 561 #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) 562 #define AR8327_FWD_CTRL1_BC_FLOOD_S 16 563 #define AR8327_FWD_CTRL1_IGMP BITS(24, 7) 564 #define AR8327_FWD_CTRL1_IGMP_S 24 565 566 #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) 567 #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) 568 #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) 569 #define AR8327_PORT_LOOKUP_IN_MODE_S 8 570 #define AR8327_PORT_LOOKUP_STATE BITS(16, 3) 571 #define AR8327_PORT_LOOKUP_STATE_S 16 572 #define AR8327_PORT_LOOKUP_LEARN (1 << 20) 573 #define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25) 574 575 #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) 576 577 #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) 578 #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16) 579 580 #define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100) 581 582 #endif /* __AR8X16_SWITCHREG_H__ */ 583