1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _AVR32DCI_H_ 29 #define _AVR32DCI_H_ 30 31 #define AVR32_MAX_DEVICES (USB_MIN_DEVICES + 1) 32 33 /* Register definitions */ 34 35 #define AVR32_CTRL 0x00 /* Control */ 36 #define AVR32_CTRL_DEV_ADDR 0x7F 37 #define AVR32_CTRL_DEV_FADDR_EN 0x80 38 #define AVR32_CTRL_DEV_EN_USBA 0x100 39 #define AVR32_CTRL_DEV_DETACH 0x200 40 #define AVR32_CTRL_DEV_REWAKEUP 0x400 41 42 #define AVR32_FNUM 0x04 /* Frame Number */ 43 #define AVR32_FNUM_MASK 0x3FFF 44 #define AVR32_FRAME_MASK 0x7FF 45 46 /* 0x08 - 0x0C Reserved */ 47 #define AVR32_IEN 0x10 /* Interrupt Enable */ 48 #define AVR32_INTSTA 0x14 /* Interrupt Status */ 49 #define AVR32_CLRINT 0x18 /* Clear Interrupt */ 50 51 #define AVR32_INT_SPEED 0x00000001 /* set if High Speed else Full Speed */ 52 #define AVR32_INT_DET_SUSPD 0x00000002 53 #define AVR32_INT_MICRO_SOF 0x00000004 54 #define AVR32_INT_INT_SOF 0x00000008 55 #define AVR32_INT_ENDRESET 0x00000010 56 #define AVR32_INT_WAKE_UP 0x00000020 57 #define AVR32_INT_ENDOFRSM 0x00000040 58 #define AVR32_INT_UPSTR_RES 0x00000080 59 #define AVR32_INT_EPT_INT(n) (0x00000100 << (n)) 60 #define AVR32_INT_DMA_INT(n) (0x01000000 << (n)) 61 62 #define AVR32_EPTRST 0x1C /* Endpoints Reset */ 63 #define AVR32_EPTRST_MASK(n) (0x00000001 << (n)) 64 65 /* 0x20 - 0xCC Reserved */ 66 #define AVR32_TSTSOFCNT 0xD0 /* Test SOF Counter */ 67 #define AVR32_TSTCNTA 0xD4 /* Test A Counter */ 68 #define AVR32_TSTCNTB 0xD8 /* Test B Counter */ 69 #define AVR32_TSTMODEREG 0xDC /* Test Mode */ 70 #define AVR32_TST 0xE0 /* Test */ 71 #define AVR32_TST_NORMAL 0x00000000 72 #define AVR32_TST_HS_ONLY 0x00000002 73 #define AVR32_TST_FS_ONLY 0x00000003 74 75 /* 0xE4 - 0xE8 Reserved */ 76 #define AVR32_IPPADDRSIZE 0xEC /* PADDRSIZE */ 77 #define AVR32_IPNAME1 0xF0 /* Name1 */ 78 #define AVR32_IPNAME2 0xF4 /* Name2 */ 79 #define AVR32_IPFEATURES 0xF8 /* Features */ 80 #define AVR32_IPFEATURES_NEP(x) (((x) & 0xF) ? ((x) & 0xF) : 0x10) 81 82 #define AVR32_IPVERSION 0xFC /* IP Version */ 83 84 #define _A(base,n) ((base) + (0x20*(n))) 85 #define AVR32_EPTCFG(n) _A(0x100, n) /* Endpoint Configuration */ 86 #define AVR32_EPTCFG_EPSIZE(n) ((n)-3) /* power of two */ 87 #define AVR32_EPTCFG_EPDIR_OUT 0x00000000 88 #define AVR32_EPTCFG_EPDIR_IN 0x00000008 89 #define AVR32_EPTCFG_TYPE_CTRL 0x00000000 90 #define AVR32_EPTCFG_TYPE_ISOC 0x00000100 91 #define AVR32_EPTCFG_TYPE_BULK 0x00000200 92 #define AVR32_EPTCFG_TYPE_INTR 0x00000300 93 #define AVR32_EPTCFG_NBANK(n) (0x00000400*(n)) 94 #define AVR32_EPTCFG_NB_TRANS(n) (0x00001000*(n)) 95 #define AVR32_EPTCFG_EPT_MAPD 0x80000000 96 97 #define AVR32_EPTCTLENB(n) _A(0x104, n) /* Endpoint Control Enable */ 98 #define AVR32_EPTCTLDIS(n) _A(0x108, n) /* Endpoint Control Disable */ 99 #define AVR32_EPTCTL(n) _A(0x10C, n) /* Endpoint Control */ 100 #define AVR32_EPTCTL_EPT_ENABL 0x00000001 101 #define AVR32_EPTCTL_AUTO_VALID 0x00000002 102 #define AVR32_EPTCTL_INTDIS_DMA 0x00000008 103 #define AVR32_EPTCTL_NYET_DIS 0x00000010 104 #define AVR32_EPTCTL_DATAX_RX 0x00000040 105 #define AVR32_EPTCTL_MDATA_RX 0x00000080 106 #define AVR32_EPTCTL_ERR_OVFLW 0x00000100 107 #define AVR32_EPTCTL_RX_BK_RDY 0x00000200 108 #define AVR32_EPTCTL_TX_COMPLT 0x00000400 109 #define AVR32_EPTCTL_TX_PK_RDY 0x00000800 110 #define AVR32_EPTCTL_RX_SETUP 0x00001000 111 #define AVR32_EPTCTL_STALL_SNT 0x00002000 112 #define AVR32_EPTCTL_NAK_IN 0x00004000 113 #define AVR32_EPTCTL_NAK_OUT 0x00008000 114 #define AVR32_EPTCTL_BUSY_BANK 0x00040000 115 #define AVR32_EPTCTL_SHORT_PCKT 0x80000000 116 117 /* 0x110 Reserved */ 118 #define AVR32_EPTSETSTA(n) _A(0x114, n) /* Endpoint Set Status */ 119 #define AVR32_EPTCLRSTA(n) _A(0x118, n) /* Endpoint Clear Status */ 120 #define AVR32_EPTSTA(n) _A(0x11C, n) /* Endpoint Status */ 121 #define AVR32_EPTSTA_FRCESTALL 0x00000020 122 #define AVR32_EPTSTA_TOGGLESQ_STA(x) (((x) & 0xC0) >> 6) 123 #define AVR32_EPTSTA_TOGGLESQ 0x00000040 124 #define AVR32_EPTSTA_ERR_OVFLW 0x00000100 125 #define AVR32_EPTSTA_RX_BK_RDY 0x00000200 126 #define AVR32_EPTSTA_TX_COMPLT 0x00000400 127 #define AVR32_EPTSTA_TX_PK_RDY 0x00000800 128 #define AVR32_EPTSTA_RX_SETUP 0x00001000 129 #define AVR32_EPTSTA_STALL_SNT 0x00002000 130 #define AVR32_EPTSTA_NAK_IN 0x00004000 131 #define AVR32_EPTSTA_NAK_OUT 0x00008000 132 #define AVR32_EPTSTA_CURRENT_BANK(x) (((x) & 0x00030000) >> 16) 133 #define AVR32_EPTSTA_BUSY_BANK_STA(x) (((x) & 0x000C0000) >> 18) 134 #define AVR32_EPTSTA_BYTE_COUNT(x) (((x) & 0x7FF00000) >> 20) 135 #define AVR32_EPTSTA_SHRT_PCKT 0x80000000 136 137 /* 0x300 - 0x30C Reserved */ 138 #define AVR32_DMANXTDSC 0x310 /* DMA Next Descriptor Address */ 139 #define AVR32_DMAADDRESS 0x314 /* DMA Channel Address */ 140 141 #define AVR32_READ_4(sc, reg) \ 142 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 143 144 #define AVR32_WRITE_4(sc, reg, data) \ 145 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 146 147 #define AVR32_WRITE_MULTI_4(sc, reg, ptr, len) \ 148 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 149 150 #define AVR32_READ_MULTI_4(sc, reg, ptr, len) \ 151 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 152 153 /* 154 * Maximum number of endpoints supported: 155 */ 156 #define AVR32_EP_MAX 7 157 158 struct avr32dci_td; 159 160 typedef uint8_t (avr32dci_cmd_t)(struct avr32dci_td *td); 161 typedef void (avr32dci_clocks_t)(struct usb_bus *); 162 163 struct avr32dci_td { 164 struct avr32dci_td *obj_next; 165 avr32dci_cmd_t *func; 166 struct usb_page_cache *pc; 167 uint32_t offset; 168 uint32_t remainder; 169 uint16_t max_packet_size; 170 uint8_t bank_shift; 171 uint8_t error:1; 172 uint8_t alt_next:1; 173 uint8_t short_pkt:1; 174 uint8_t support_multi_buffer:1; 175 uint8_t did_stall:1; 176 uint8_t ep_no:3; 177 }; 178 179 struct avr32dci_std_temp { 180 avr32dci_cmd_t *func; 181 struct usb_page_cache *pc; 182 struct avr32dci_td *td; 183 struct avr32dci_td *td_next; 184 uint32_t len; 185 uint32_t offset; 186 uint16_t max_frame_size; 187 uint8_t bank_shift; 188 uint8_t short_pkt; 189 /* 190 * short_pkt = 0: transfer should be short terminated 191 * short_pkt = 1: transfer should not be short terminated 192 */ 193 uint8_t setup_alt_next; 194 uint8_t did_stall; 195 }; 196 197 struct avr32dci_config_desc { 198 struct usb_config_descriptor confd; 199 struct usb_interface_descriptor ifcd; 200 struct usb_endpoint_descriptor endpd; 201 } __packed; 202 203 union avr32dci_hub_temp { 204 uWord wValue; 205 struct usb_port_status ps; 206 }; 207 208 struct avr32dci_flags { 209 uint8_t change_connect:1; 210 uint8_t change_suspend:1; 211 uint8_t status_suspend:1; /* set if suspended */ 212 uint8_t status_vbus:1; /* set if present */ 213 uint8_t status_bus_reset:1; /* set if reset complete */ 214 uint8_t remote_wakeup:1; 215 uint8_t self_powered:1; 216 uint8_t clocks_off:1; 217 uint8_t port_powered:1; 218 uint8_t port_enabled:1; 219 uint8_t d_pulled_up:1; 220 }; 221 222 struct avr32dci_softc { 223 struct usb_bus sc_bus; 224 union avr32dci_hub_temp sc_hub_temp; 225 226 /* must be set by by the bus interface layer */ 227 avr32dci_clocks_t *sc_clocks_on; 228 avr32dci_clocks_t *sc_clocks_off; 229 230 struct usb_device *sc_devices[AVR32_MAX_DEVICES]; 231 struct resource *sc_irq_res; 232 void *sc_intr_hdl; 233 struct resource *sc_io_res; 234 bus_space_tag_t sc_io_tag; 235 bus_space_handle_t sc_io_hdl; 236 uint8_t *physdata; 237 238 uint8_t sc_rt_addr; /* root hub address */ 239 uint8_t sc_dv_addr; /* device address */ 240 uint8_t sc_conf; /* root hub config */ 241 242 uint8_t sc_hub_idata[1]; 243 244 struct avr32dci_flags sc_flags; 245 }; 246 247 /* prototypes */ 248 249 usb_error_t avr32dci_init(struct avr32dci_softc *sc); 250 void avr32dci_uninit(struct avr32dci_softc *sc); 251 void avr32dci_interrupt(struct avr32dci_softc *sc); 252 void avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on); 253 254 #endif /* _AVR32DCI_H_ */ 255