| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InsertPrefetch.cpp | 84 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch()
225 static_assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && in runOnMachineFunction()
233 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg()) in runOnMachineFunction()
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| H A D | X86OptimizeLEAs.cpp | 194 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
363 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
458 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
464 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
557 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
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| H A D | X86FixupLEAs.cpp | 458 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage()
507 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU()
554 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
657 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
694 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
746 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
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| H A D | X86AsmPrinter.cpp | 377 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
414 PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier); in PrintLeaMemReference()
473 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference()
501 PrintOperand(MI, OpNo + X86::AddrBaseReg, O); in PrintIntelMemReference()
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| H A D | X86CallFrameOptimization.cpp | 427 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
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| H A D | X86SpeculativeLoadHardening.cpp | 1329 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1400 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1800 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in sinkPostLoadHardenedInst()
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| H A D | X86InstrInfo.h | 136 MI.getOperand(Op + X86::AddrBaseReg).isReg() && in isLeaMem()
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| H A D | X86AvoidStoreForwardingBlocks.cpp | 301 return MI->getOperand(AddrOffset + X86::AddrBaseReg); in getBaseOperand()
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| H A D | X86LoadValueInjectionLoadHardening.cpp | 782 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in instrUsesRegToAccessMemory()
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| H A D | X86InstrInfo.cpp | 476 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() && in isFrameOperand()
483 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex(); in isFrameOperand()
906 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() && in isReallyTriviallyReMaterializable()
911 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
932 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg()) in isReallyTriviallyReMaterializable()
934 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
4393 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp()
4521 &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg); in getMemOperandsWithOffsetWidth()
8680 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) || in areLoadsFromSameBasePtr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 604 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in emitMemModRMByte()
1064 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1082 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1124 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1134 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1143 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1164 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1359 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitREXPrefix()
1368 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitREXPrefix()
1383 Prefix.setBB2(MI, MemOperand + X86::AddrBaseReg); in emitREXPrefix()
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| H A D | X86MCTargetDesc.cpp | 78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
665 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress()
691 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset()
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| H A D | X86ATTInstPrinter.cpp | 426 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
447 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
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| H A D | X86IntelInstPrinter.cpp | 383 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
396 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
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| H A D | X86AsmBackend.cpp | 264 unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg; in isRIPRelative()
340 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg; in determinePaddingPrefix()
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| H A D | X86EncodingOptimization.cpp | 357 if (Absolute && (MI.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || in optimizeMOV()
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| H A D | X86BaseInfo.h | 29 AddrBaseReg = 0, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 3808 const MCOperand &MO = Inst.getOperand(X86::AddrBaseReg); in validateInstruction()
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