/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InsertPrefetch.cpp | 85 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() 226 X86::AddrIndexReg == 2 && X86::AddrDisp == 3 && in runOnMachineFunction() 237 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg()) in runOnMachineFunction()
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H A D | X86FixupLEAs.cpp | 459 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage() 508 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU() 556 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in optTwoAddrLEA() 661 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction() 696 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstructionForSlowLEA() 748 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg); in processInstrForSlow3OpLEA()
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H A D | X86AsmPrinter.cpp | 378 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() 418 PrintModifiedOperand(MI, OpNo + X86::AddrIndexReg, O, Modifier); in PrintLeaMemReference() 475 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() 509 PrintOperand(MI, OpNo + X86::AddrIndexReg, O); in PrintIntelMemReference()
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H A D | X86OptimizeLEAs.cpp | 196 &MI.getOperand(N + X86::AddrIndexReg), in getMemOpKey() 560 MI.getOperand(MemOpNo + X86::AddrIndexReg) in removeRedundantAddrCalc()
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H A D | X86CallFrameOptimization.cpp | 431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
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H A D | X86SpeculativeLoadHardening.cpp | 1331 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden() 1402 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in tracePredStateThroughBlocksAndHarden() 1802 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in sinkPostLoadHardenedInst()
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H A D | X86InstrInfo.h | 138 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isLeaMem()
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H A D | X86InstrInfo.cpp | 478 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand() 481 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && in isFrameOperand() 908 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable() 909 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable() 928 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable() 929 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable() 3505 const MachineOperand &Index = MI.getOperand(OpNo + X86::AddrIndexReg); in getConstantFromPool() 4528 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != in getMemOperandsWithOffsetWidth() 4594 MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg); in loadStoreTileReg() 4607 MachineOperand &MO = NewMI->getOperand(1 + X86::AddrIndexReg); in loadStoreTileReg() [all …]
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H A D | X86AvoidStoreForwardingBlocks.cpp | 317 const MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg); in isRelevantAddressingMode()
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H A D | X86LoadValueInjectionLoadHardening.cpp | 784 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg); in instrUsesRegToAccessMemory()
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H A D | X86FastISel.cpp | 219 X86::AddrIndexReg); in addFullAddress()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 1065 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 1083 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 1084 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix() 1125 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 1126 Prefix.setV2(MI, MemOperand + X86::AddrIndexReg, HasVEX_4V); in emitVEXOpcodePrefix() 1135 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 1144 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 1165 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitVEXOpcodePrefix() 1360 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitREXPrefix() 1369 Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); in emitREXPrefix() [all …]
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H A D | X86MCTargetDesc.cpp | 79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand() 89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand() 99 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() 666 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() 692 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset()
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H A D | X86ATTInstPrinter.cpp | 427 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() 451 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
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H A D | X86IntelInstPrinter.cpp | 385 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() 404 printOperand(MI, Op+X86::AddrIndexReg, O); in printMemReference()
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H A D | X86EncodingOptimization.cpp | 359 MI.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in optimizeMOV()
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H A D | X86BaseInfo.h | 31 AddrIndexReg = 2, enumerator
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 3766 Inst.getOperand(4 + X86::AddrIndexReg).getReg()); in validateInstruction() 3774 Inst.getOperand(3 + X86::AddrIndexReg).getReg()); in validateInstruction()
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