1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/dmi.h>
11 #include <linux/firmware.h>
12 #include <linux/iopoll.h>
13 #include <linux/workqueue.h>
14 #include <net/mac80211.h>
15 #if defined(__FreeBSD__)
16 #include <linux/seq_file.h>
17 #include <linux/lockdep.h>
18 #include <linux/interrupt.h>
19 #include <linux/pm.h>
20 #endif
21
22 struct rtw89_dev;
23 struct rtw89_pci_info;
24 struct rtw89_mac_gen_def;
25 struct rtw89_phy_gen_def;
26 struct rtw89_efuse_block_cfg;
27 struct rtw89_h2c_rf_tssi;
28 struct rtw89_fw_txpwr_track_cfg;
29 struct rtw89_phy_rfk_log_fmt;
30
31 extern const struct ieee80211_ops rtw89_ops;
32
33 #define MASKBYTE0 0xff
34 #define MASKBYTE1 0xff00
35 #define MASKBYTE2 0xff0000
36 #define MASKBYTE3 0xff000000
37 #define MASKBYTE4 0xff00000000ULL
38 #define MASKHWORD 0xffff0000
39 #define MASKLWORD 0x0000ffff
40 #define MASKDWORD 0xffffffff
41 #define RFREG_MASK 0xfffff
42 #define INV_RF_DATA 0xffffffff
43 #define BYPASS_CR_DATA 0xbabecafe
44
45 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
46 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
47 #define CFO_TRACK_MAX_USER 64
48 #define MAX_RSSI 110
49 #define RSSI_FACTOR 1
50 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
51 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
52 #define DELTA_SWINGIDX_SIZE 30
53
54 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
55 #define RTW89_RADIOTAP_ROOM_EHT \
56 (sizeof(struct ieee80211_radiotap_tlv) + \
57 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
58 sizeof(struct ieee80211_radiotap_tlv) + \
59 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
60 #define RTW89_RADIOTAP_ROOM \
61 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
62
63 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
64 #define RTW89_HTC_VARIANT_HE 3
65 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
66 #define RTW89_HTC_VARIANT_HE_CID_OM 1
67 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
68 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
69
70 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
71 enum htc_om_channel_width {
72 HTC_OM_CHANNEL_WIDTH_20 = 0,
73 HTC_OM_CHANNEL_WIDTH_40 = 1,
74 HTC_OM_CHANNEL_WIDTH_80 = 2,
75 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
76 };
77 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
78 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
79 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
80 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
81 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
82 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
83
84 #define RTW89_TF_PAD GENMASK(11, 0)
85 #define RTW89_TF_BASIC_USER_INFO_SZ 6
86
87 #define RTW89_GET_TF_USER_INFO_AID12(data) \
88 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
89 #define RTW89_GET_TF_USER_INFO_RUA(data) \
90 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
91 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
92 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
93
94 enum rtw89_subband {
95 RTW89_CH_2G = 0,
96 RTW89_CH_5G_BAND_1 = 1,
97 /* RTW89_CH_5G_BAND_2 = 2, unused */
98 RTW89_CH_5G_BAND_3 = 3,
99 RTW89_CH_5G_BAND_4 = 4,
100
101 RTW89_CH_6G_BAND_IDX0, /* Low */
102 RTW89_CH_6G_BAND_IDX1, /* Low */
103 RTW89_CH_6G_BAND_IDX2, /* Mid */
104 RTW89_CH_6G_BAND_IDX3, /* Mid */
105 RTW89_CH_6G_BAND_IDX4, /* High */
106 RTW89_CH_6G_BAND_IDX5, /* High */
107 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
108 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
109
110 RTW89_SUBBAND_NR,
111 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
112 };
113
114 enum rtw89_gain_offset {
115 RTW89_GAIN_OFFSET_2G_CCK,
116 RTW89_GAIN_OFFSET_2G_OFDM,
117 RTW89_GAIN_OFFSET_5G_LOW,
118 RTW89_GAIN_OFFSET_5G_MID,
119 RTW89_GAIN_OFFSET_5G_HIGH,
120 RTW89_GAIN_OFFSET_6G_L0,
121 RTW89_GAIN_OFFSET_6G_L1,
122 RTW89_GAIN_OFFSET_6G_M0,
123 RTW89_GAIN_OFFSET_6G_M1,
124 RTW89_GAIN_OFFSET_6G_H0,
125 RTW89_GAIN_OFFSET_6G_H1,
126 RTW89_GAIN_OFFSET_6G_UH0,
127 RTW89_GAIN_OFFSET_6G_UH1,
128
129 RTW89_GAIN_OFFSET_NR,
130 };
131
132 enum rtw89_hci_type {
133 RTW89_HCI_TYPE_PCIE,
134 RTW89_HCI_TYPE_USB,
135 RTW89_HCI_TYPE_SDIO,
136 };
137
138 enum rtw89_core_chip_id {
139 RTL8852A,
140 RTL8852B,
141 RTL8852BT,
142 RTL8852C,
143 RTL8851B,
144 RTL8922A,
145 };
146
147 enum rtw89_chip_gen {
148 RTW89_CHIP_AX,
149 RTW89_CHIP_BE,
150
151 RTW89_CHIP_GEN_NUM,
152 };
153
154 enum rtw89_cv {
155 CHIP_CAV,
156 CHIP_CBV,
157 CHIP_CCV,
158 CHIP_CDV,
159 CHIP_CEV,
160 CHIP_CFV,
161 CHIP_CV_MAX,
162 CHIP_CV_INVALID = CHIP_CV_MAX,
163 };
164
165 enum rtw89_bacam_ver {
166 RTW89_BACAM_V0,
167 RTW89_BACAM_V1,
168
169 RTW89_BACAM_V0_EXT = 99,
170 };
171
172 enum rtw89_core_tx_type {
173 RTW89_CORE_TX_TYPE_DATA,
174 RTW89_CORE_TX_TYPE_MGMT,
175 RTW89_CORE_TX_TYPE_FWCMD,
176 };
177
178 enum rtw89_core_rx_type {
179 RTW89_CORE_RX_TYPE_WIFI = 0,
180 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
181 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
182 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
183 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
184 RTW89_CORE_RX_TYPE_SS2FW = 5,
185 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
186 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
187 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
188 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
189 RTW89_CORE_RX_TYPE_C2H = 10,
190 RTW89_CORE_RX_TYPE_CSI = 11,
191 RTW89_CORE_RX_TYPE_CQI = 12,
192 RTW89_CORE_RX_TYPE_H2C = 13,
193 RTW89_CORE_RX_TYPE_FWDL = 14,
194 };
195
196 enum rtw89_txq_flags {
197 RTW89_TXQ_F_AMPDU = 0,
198 RTW89_TXQ_F_BLOCK_BA = 1,
199 RTW89_TXQ_F_FORBID_BA = 2,
200 };
201
202 enum rtw89_net_type {
203 RTW89_NET_TYPE_NO_LINK = 0,
204 RTW89_NET_TYPE_AD_HOC = 1,
205 RTW89_NET_TYPE_INFRA = 2,
206 RTW89_NET_TYPE_AP_MODE = 3,
207 };
208
209 enum rtw89_wifi_role {
210 RTW89_WIFI_ROLE_NONE,
211 RTW89_WIFI_ROLE_STATION,
212 RTW89_WIFI_ROLE_AP,
213 RTW89_WIFI_ROLE_AP_VLAN,
214 RTW89_WIFI_ROLE_ADHOC,
215 RTW89_WIFI_ROLE_ADHOC_MASTER,
216 RTW89_WIFI_ROLE_MESH_POINT,
217 RTW89_WIFI_ROLE_MONITOR,
218 RTW89_WIFI_ROLE_P2P_DEVICE,
219 RTW89_WIFI_ROLE_P2P_CLIENT,
220 RTW89_WIFI_ROLE_P2P_GO,
221 RTW89_WIFI_ROLE_NAN,
222 RTW89_WIFI_ROLE_MLME_MAX
223 };
224
225 enum rtw89_upd_mode {
226 RTW89_ROLE_CREATE,
227 RTW89_ROLE_REMOVE,
228 RTW89_ROLE_TYPE_CHANGE,
229 RTW89_ROLE_INFO_CHANGE,
230 RTW89_ROLE_CON_DISCONN,
231 RTW89_ROLE_BAND_SW,
232 RTW89_ROLE_FW_RESTORE,
233 };
234
235 enum rtw89_self_role {
236 RTW89_SELF_ROLE_CLIENT,
237 RTW89_SELF_ROLE_AP,
238 RTW89_SELF_ROLE_AP_CLIENT
239 };
240
241 enum rtw89_msk_sO_el {
242 RTW89_NO_MSK,
243 RTW89_SMA,
244 RTW89_TMA,
245 RTW89_BSSID
246 };
247
248 enum rtw89_sch_tx_sel {
249 RTW89_SCH_TX_SEL_ALL,
250 RTW89_SCH_TX_SEL_HIQ,
251 RTW89_SCH_TX_SEL_MG0,
252 RTW89_SCH_TX_SEL_MACID,
253 };
254
255 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
256 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
257 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
258 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
259 */
260 enum rtw89_add_cam_sec_mode {
261 RTW89_ADDR_CAM_SEC_NONE = 0,
262 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
263 RTW89_ADDR_CAM_SEC_NORMAL = 2,
264 RTW89_ADDR_CAM_SEC_4GROUP = 3,
265 };
266
267 enum rtw89_sec_key_type {
268 RTW89_SEC_KEY_TYPE_NONE = 0,
269 RTW89_SEC_KEY_TYPE_WEP40 = 1,
270 RTW89_SEC_KEY_TYPE_WEP104 = 2,
271 RTW89_SEC_KEY_TYPE_TKIP = 3,
272 RTW89_SEC_KEY_TYPE_WAPI = 4,
273 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
274 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
275 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
276 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
277 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
278 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
279 };
280
281 enum rtw89_port {
282 RTW89_PORT_0 = 0,
283 RTW89_PORT_1 = 1,
284 RTW89_PORT_2 = 2,
285 RTW89_PORT_3 = 3,
286 RTW89_PORT_4 = 4,
287 RTW89_PORT_NUM
288 };
289
290 enum rtw89_band {
291 RTW89_BAND_2G = 0,
292 RTW89_BAND_5G = 1,
293 RTW89_BAND_6G = 2,
294 RTW89_BAND_NUM,
295 };
296
297 enum rtw89_hw_rate {
298 RTW89_HW_RATE_CCK1 = 0x0,
299 RTW89_HW_RATE_CCK2 = 0x1,
300 RTW89_HW_RATE_CCK5_5 = 0x2,
301 RTW89_HW_RATE_CCK11 = 0x3,
302 RTW89_HW_RATE_OFDM6 = 0x4,
303 RTW89_HW_RATE_OFDM9 = 0x5,
304 RTW89_HW_RATE_OFDM12 = 0x6,
305 RTW89_HW_RATE_OFDM18 = 0x7,
306 RTW89_HW_RATE_OFDM24 = 0x8,
307 RTW89_HW_RATE_OFDM36 = 0x9,
308 RTW89_HW_RATE_OFDM48 = 0xA,
309 RTW89_HW_RATE_OFDM54 = 0xB,
310 RTW89_HW_RATE_MCS0 = 0x80,
311 RTW89_HW_RATE_MCS1 = 0x81,
312 RTW89_HW_RATE_MCS2 = 0x82,
313 RTW89_HW_RATE_MCS3 = 0x83,
314 RTW89_HW_RATE_MCS4 = 0x84,
315 RTW89_HW_RATE_MCS5 = 0x85,
316 RTW89_HW_RATE_MCS6 = 0x86,
317 RTW89_HW_RATE_MCS7 = 0x87,
318 RTW89_HW_RATE_MCS8 = 0x88,
319 RTW89_HW_RATE_MCS9 = 0x89,
320 RTW89_HW_RATE_MCS10 = 0x8A,
321 RTW89_HW_RATE_MCS11 = 0x8B,
322 RTW89_HW_RATE_MCS12 = 0x8C,
323 RTW89_HW_RATE_MCS13 = 0x8D,
324 RTW89_HW_RATE_MCS14 = 0x8E,
325 RTW89_HW_RATE_MCS15 = 0x8F,
326 RTW89_HW_RATE_MCS16 = 0x90,
327 RTW89_HW_RATE_MCS17 = 0x91,
328 RTW89_HW_RATE_MCS18 = 0x92,
329 RTW89_HW_RATE_MCS19 = 0x93,
330 RTW89_HW_RATE_MCS20 = 0x94,
331 RTW89_HW_RATE_MCS21 = 0x95,
332 RTW89_HW_RATE_MCS22 = 0x96,
333 RTW89_HW_RATE_MCS23 = 0x97,
334 RTW89_HW_RATE_MCS24 = 0x98,
335 RTW89_HW_RATE_MCS25 = 0x99,
336 RTW89_HW_RATE_MCS26 = 0x9A,
337 RTW89_HW_RATE_MCS27 = 0x9B,
338 RTW89_HW_RATE_MCS28 = 0x9C,
339 RTW89_HW_RATE_MCS29 = 0x9D,
340 RTW89_HW_RATE_MCS30 = 0x9E,
341 RTW89_HW_RATE_MCS31 = 0x9F,
342 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
343 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
344 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
345 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
346 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
347 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
348 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
349 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
350 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
351 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
352 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
353 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
354 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
355 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
356 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
357 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
358 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
359 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
360 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
361 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
362 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
363 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
364 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
365 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
366 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
367 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
368 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
369 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
370 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
371 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
372 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
373 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
374 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
375 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
376 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
377 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
378 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
379 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
380 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
381 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
382 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
383 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
384 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
385 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
386 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
387 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
388 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
389 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
390 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
391 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
392 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
393 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
394 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
395 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
396 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
397 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
398 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
399 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
400 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
401 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
402 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
403 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
404 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
405 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
406 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
407 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
408 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
409 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
410 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
411 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
412 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
413 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
414 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
415 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
416 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
417 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
418 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
419 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
420 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
421 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
422 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
423 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
424 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
425 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
426 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
427 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
428 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
429 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
430
431 RTW89_HW_RATE_V1_MCS0 = 0x100,
432 RTW89_HW_RATE_V1_MCS1 = 0x101,
433 RTW89_HW_RATE_V1_MCS2 = 0x102,
434 RTW89_HW_RATE_V1_MCS3 = 0x103,
435 RTW89_HW_RATE_V1_MCS4 = 0x104,
436 RTW89_HW_RATE_V1_MCS5 = 0x105,
437 RTW89_HW_RATE_V1_MCS6 = 0x106,
438 RTW89_HW_RATE_V1_MCS7 = 0x107,
439 RTW89_HW_RATE_V1_MCS8 = 0x108,
440 RTW89_HW_RATE_V1_MCS9 = 0x109,
441 RTW89_HW_RATE_V1_MCS10 = 0x10A,
442 RTW89_HW_RATE_V1_MCS11 = 0x10B,
443 RTW89_HW_RATE_V1_MCS12 = 0x10C,
444 RTW89_HW_RATE_V1_MCS13 = 0x10D,
445 RTW89_HW_RATE_V1_MCS14 = 0x10E,
446 RTW89_HW_RATE_V1_MCS15 = 0x10F,
447 RTW89_HW_RATE_V1_MCS16 = 0x110,
448 RTW89_HW_RATE_V1_MCS17 = 0x111,
449 RTW89_HW_RATE_V1_MCS18 = 0x112,
450 RTW89_HW_RATE_V1_MCS19 = 0x113,
451 RTW89_HW_RATE_V1_MCS20 = 0x114,
452 RTW89_HW_RATE_V1_MCS21 = 0x115,
453 RTW89_HW_RATE_V1_MCS22 = 0x116,
454 RTW89_HW_RATE_V1_MCS23 = 0x117,
455 RTW89_HW_RATE_V1_MCS24 = 0x118,
456 RTW89_HW_RATE_V1_MCS25 = 0x119,
457 RTW89_HW_RATE_V1_MCS26 = 0x11A,
458 RTW89_HW_RATE_V1_MCS27 = 0x11B,
459 RTW89_HW_RATE_V1_MCS28 = 0x11C,
460 RTW89_HW_RATE_V1_MCS29 = 0x11D,
461 RTW89_HW_RATE_V1_MCS30 = 0x11E,
462 RTW89_HW_RATE_V1_MCS31 = 0x11F,
463 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
464 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
465 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
466 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
467 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
468 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
469 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
470 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
471 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
472 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
473 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
474 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
475 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
476 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
477 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
478 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
479 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
480 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
481 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
482 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
483 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
484 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
485 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
486 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
487 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
488 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
489 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
490 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
491 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
492 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
493 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
494 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
495 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
496 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
497 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
498 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
499 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
500 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
501 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
502 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
503 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
504 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
505 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
506 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
507 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
508 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
509 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
510 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
511 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
512 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
513 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
514 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
515 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
516 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
517 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
518 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
519 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
520 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
521 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
522 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
523 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
524 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
525 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
526 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
527 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
528 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
529 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
530 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
531 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
532 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
533 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
534 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
535 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
536 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
537 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
538 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
539 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
540 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
541 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
542 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
543 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
544 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
545 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
546 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
547 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
548 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
549 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
550 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
551 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
552 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
553 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
554 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
555 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
556 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
557 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
558 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
559 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
560 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
561 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
562 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
563 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
564 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
565 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
566 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
567 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
568 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
569 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
570 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
571 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
572 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
573 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
574 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
575 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
576 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
577 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
578 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
579 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
580 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
581 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
582 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
583 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
584 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
585 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
586 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
587 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
588 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
589 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
590 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
591 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
592 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
593 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
594 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
595 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
596 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
597 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
598 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
599 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
600 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
601 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
602 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
603 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
604 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
605 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
606 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
607 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
608 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
609 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
610 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
611 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
612 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
613 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
614 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
615 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
616 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
617
618 RTW89_HW_RATE_NR,
619 RTW89_HW_RATE_INVAL,
620
621 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
622 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
623 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
624 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
625 };
626
627 /* 2G channels,
628 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
629 */
630 #define RTW89_2G_CH_NUM 14
631
632 /* 5G channels,
633 * 36, 38, 40, 42, 44, 46, 48, 50,
634 * 52, 54, 56, 58, 60, 62, 64,
635 * 100, 102, 104, 106, 108, 110, 112, 114,
636 * 116, 118, 120, 122, 124, 126, 128, 130,
637 * 132, 134, 136, 138, 140, 142, 144,
638 * 149, 151, 153, 155, 157, 159, 161, 163,
639 * 165, 167, 169, 171, 173, 175, 177
640 */
641 #define RTW89_5G_CH_NUM 53
642
643 /* 6G channels,
644 * 1, 3, 5, 7, 9, 11, 13, 15,
645 * 17, 19, 21, 23, 25, 27, 29, 33,
646 * 35, 37, 39, 41, 43, 45, 47, 49,
647 * 51, 53, 55, 57, 59, 61, 65, 67,
648 * 69, 71, 73, 75, 77, 79, 81, 83,
649 * 85, 87, 89, 91, 93, 97, 99, 101,
650 * 103, 105, 107, 109, 111, 113, 115, 117,
651 * 119, 121, 123, 125, 129, 131, 133, 135,
652 * 137, 139, 141, 143, 145, 147, 149, 151,
653 * 153, 155, 157, 161, 163, 165, 167, 169,
654 * 171, 173, 175, 177, 179, 181, 183, 185,
655 * 187, 189, 193, 195, 197, 199, 201, 203,
656 * 205, 207, 209, 211, 213, 215, 217, 219,
657 * 221, 225, 227, 229, 231, 233, 235, 237,
658 * 239, 241, 243, 245, 247, 249, 251, 253,
659 */
660 #define RTW89_6G_CH_NUM 120
661
662 enum rtw89_rate_section {
663 RTW89_RS_CCK,
664 RTW89_RS_OFDM,
665 RTW89_RS_MCS, /* for HT/VHT/HE */
666 RTW89_RS_HEDCM,
667 RTW89_RS_OFFSET,
668 RTW89_RS_NUM,
669 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
670 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
671 };
672
673 enum rtw89_rate_offset_indexes {
674 RTW89_RATE_OFFSET_HE,
675 RTW89_RATE_OFFSET_VHT,
676 RTW89_RATE_OFFSET_HT,
677 RTW89_RATE_OFFSET_OFDM,
678 RTW89_RATE_OFFSET_CCK,
679 RTW89_RATE_OFFSET_DLRU_EHT,
680 RTW89_RATE_OFFSET_DLRU_HE,
681 RTW89_RATE_OFFSET_EHT,
682 __RTW89_RATE_OFFSET_NUM,
683
684 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
685 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
686 };
687
688 enum rtw89_rate_num {
689 RTW89_RATE_CCK_NUM = 4,
690 RTW89_RATE_OFDM_NUM = 8,
691 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
692
693 RTW89_RATE_MCS_NUM_AX = 12,
694 RTW89_RATE_MCS_NUM_BE = 16,
695 __RTW89_RATE_MCS_NUM = 16,
696 };
697
698 enum rtw89_nss {
699 RTW89_NSS_1 = 0,
700 RTW89_NSS_2 = 1,
701 /* HE DCM only support 1ss and 2ss */
702 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
703 RTW89_NSS_3 = 2,
704 RTW89_NSS_4 = 3,
705 RTW89_NSS_NUM,
706 };
707
708 enum rtw89_ntx {
709 RTW89_1TX = 0,
710 RTW89_2TX = 1,
711 RTW89_NTX_NUM,
712 };
713
714 enum rtw89_beamforming_type {
715 RTW89_NONBF = 0,
716 RTW89_BF = 1,
717 RTW89_BF_NUM,
718 };
719
720 enum rtw89_ofdma_type {
721 RTW89_NON_OFDMA = 0,
722 RTW89_OFDMA = 1,
723 RTW89_OFDMA_NUM,
724 };
725
726 enum rtw89_regulation_type {
727 RTW89_WW = 0,
728 RTW89_ETSI = 1,
729 RTW89_FCC = 2,
730 RTW89_MKK = 3,
731 RTW89_NA = 4,
732 RTW89_IC = 5,
733 RTW89_KCC = 6,
734 RTW89_ACMA = 7,
735 RTW89_NCC = 8,
736 RTW89_MEXICO = 9,
737 RTW89_CHILE = 10,
738 RTW89_UKRAINE = 11,
739 RTW89_CN = 12,
740 RTW89_QATAR = 13,
741 RTW89_UK = 14,
742 RTW89_THAILAND = 15,
743 RTW89_REGD_NUM,
744 };
745
746 enum rtw89_reg_6ghz_power {
747 RTW89_REG_6GHZ_POWER_VLP = 0,
748 RTW89_REG_6GHZ_POWER_LPI = 1,
749 RTW89_REG_6GHZ_POWER_STD = 2,
750
751 NUM_OF_RTW89_REG_6GHZ_POWER,
752 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
753 };
754
755 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
756
757 /* calculate based on ieee80211 Transmit Power Envelope */
758 struct rtw89_reg_6ghz_tpe {
759 bool valid;
760 s8 constraint; /* unit: dBm */
761 };
762
763 enum rtw89_fw_pkt_ofld_type {
764 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
765 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
766 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
767 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
768 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
769 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
770 RTW89_PKT_OFLD_TYPE_NDP = 6,
771 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
772 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
773 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
774 RTW89_PKT_OFLD_TYPE_NUM,
775 };
776
777 struct rtw89_txpwr_byrate {
778 s8 cck[RTW89_RATE_CCK_NUM];
779 s8 ofdm[RTW89_RATE_OFDM_NUM];
780 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
781 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
782 s8 offset[__RTW89_RATE_OFFSET_NUM];
783 s8 trap;
784 };
785
786 struct rtw89_rate_desc {
787 enum rtw89_nss nss;
788 enum rtw89_rate_section rs;
789 enum rtw89_ofdma_type ofdma;
790 u8 idx;
791 };
792
793 #define PHY_STS_HDR_LEN 8
794 #define RF_PATH_MAX 4
795 #define RTW89_MAX_PPDU_CNT 8
796 struct rtw89_rx_phy_ppdu {
797 void *buf;
798 u32 len;
799 u8 rssi_avg;
800 u8 rssi[RF_PATH_MAX];
801 u8 mac_id;
802 u8 chan_idx;
803 u8 ie;
804 u16 rate;
805 struct {
806 bool has;
807 u8 avg_snr;
808 u8 evm_max;
809 u8 evm_min;
810 } ofdm;
811 bool ldpc;
812 bool stbc;
813 bool to_self;
814 bool valid;
815 };
816
817 enum rtw89_mac_idx {
818 RTW89_MAC_0 = 0,
819 RTW89_MAC_1 = 1,
820 RTW89_MAC_NUM,
821 };
822
823 enum rtw89_phy_idx {
824 RTW89_PHY_0 = 0,
825 RTW89_PHY_1 = 1,
826 RTW89_PHY_MAX
827 };
828
829 enum rtw89_sub_entity_idx {
830 RTW89_SUB_ENTITY_0 = 0,
831 RTW89_SUB_ENTITY_1 = 1,
832
833 NUM_OF_RTW89_SUB_ENTITY,
834 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY,
835 };
836
837 enum rtw89_rf_path {
838 RF_PATH_A = 0,
839 RF_PATH_B = 1,
840 RF_PATH_C = 2,
841 RF_PATH_D = 3,
842 RF_PATH_AB,
843 RF_PATH_AC,
844 RF_PATH_AD,
845 RF_PATH_BC,
846 RF_PATH_BD,
847 RF_PATH_CD,
848 RF_PATH_ABC,
849 RF_PATH_ABD,
850 RF_PATH_ACD,
851 RF_PATH_BCD,
852 RF_PATH_ABCD,
853 };
854
855 enum rtw89_rf_path_bit {
856 RF_A = BIT(0),
857 RF_B = BIT(1),
858 RF_C = BIT(2),
859 RF_D = BIT(3),
860
861 RF_AB = (RF_A | RF_B),
862 RF_AC = (RF_A | RF_C),
863 RF_AD = (RF_A | RF_D),
864 RF_BC = (RF_B | RF_C),
865 RF_BD = (RF_B | RF_D),
866 RF_CD = (RF_C | RF_D),
867
868 RF_ABC = (RF_A | RF_B | RF_C),
869 RF_ABD = (RF_A | RF_B | RF_D),
870 RF_ACD = (RF_A | RF_C | RF_D),
871 RF_BCD = (RF_B | RF_C | RF_D),
872
873 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
874 };
875
876 enum rtw89_bandwidth {
877 RTW89_CHANNEL_WIDTH_20 = 0,
878 RTW89_CHANNEL_WIDTH_40 = 1,
879 RTW89_CHANNEL_WIDTH_80 = 2,
880 RTW89_CHANNEL_WIDTH_160 = 3,
881 RTW89_CHANNEL_WIDTH_320 = 4,
882
883 /* keep index order above */
884 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
885
886 RTW89_CHANNEL_WIDTH_80_80 = 5,
887 RTW89_CHANNEL_WIDTH_5 = 6,
888 RTW89_CHANNEL_WIDTH_10 = 7,
889 };
890
891 enum rtw89_ps_mode {
892 RTW89_PS_MODE_NONE = 0,
893 RTW89_PS_MODE_RFOFF = 1,
894 RTW89_PS_MODE_CLK_GATED = 2,
895 RTW89_PS_MODE_PWR_GATED = 3,
896 };
897
898 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
899 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
900 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
901 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
902 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
903
904 enum rtw89_pe_duration {
905 RTW89_PE_DURATION_0 = 0,
906 RTW89_PE_DURATION_8 = 1,
907 RTW89_PE_DURATION_16 = 2,
908 RTW89_PE_DURATION_16_20 = 3,
909 };
910
911 enum rtw89_ru_bandwidth {
912 RTW89_RU26 = 0,
913 RTW89_RU52 = 1,
914 RTW89_RU106 = 2,
915 RTW89_RU52_26 = 3,
916 RTW89_RU106_26 = 4,
917 RTW89_RU_NUM,
918 };
919
920 enum rtw89_sc_offset {
921 RTW89_SC_DONT_CARE = 0,
922 RTW89_SC_20_UPPER = 1,
923 RTW89_SC_20_LOWER = 2,
924 RTW89_SC_20_UPMOST = 3,
925 RTW89_SC_20_LOWEST = 4,
926 RTW89_SC_20_UP2X = 5,
927 RTW89_SC_20_LOW2X = 6,
928 RTW89_SC_20_UP3X = 7,
929 RTW89_SC_20_LOW3X = 8,
930 RTW89_SC_40_UPPER = 9,
931 RTW89_SC_40_LOWER = 10,
932 };
933
934 enum rtw89_wow_flags {
935 RTW89_WOW_FLAG_EN_MAGIC_PKT,
936 RTW89_WOW_FLAG_EN_REKEY_PKT,
937 RTW89_WOW_FLAG_EN_DISCONNECT,
938 RTW89_WOW_FLAG_NUM,
939 };
940
941 struct rtw89_chan {
942 u8 channel;
943 u8 primary_channel;
944 enum rtw89_band band_type;
945 enum rtw89_bandwidth band_width;
946
947 /* The follow-up are derived from the above. We must ensure that it
948 * is assigned correctly in rtw89_chan_create() if new one is added.
949 */
950 u32 freq;
951 enum rtw89_subband subband_type;
952 enum rtw89_sc_offset pri_ch_idx;
953 u8 pri_sb_idx;
954 };
955
956 struct rtw89_chan_rcd {
957 u8 prev_primary_channel;
958 enum rtw89_band prev_band_type;
959 bool band_changed;
960 };
961
962 struct rtw89_channel_help_params {
963 u32 tx_en;
964 };
965
966 struct rtw89_port_reg {
967 u32 port_cfg;
968 u32 tbtt_prohib;
969 u32 bcn_area;
970 u32 bcn_early;
971 u32 tbtt_early;
972 u32 tbtt_agg;
973 u32 bcn_space;
974 u32 bcn_forcetx;
975 u32 bcn_err_cnt;
976 u32 bcn_err_flag;
977 u32 dtim_ctrl;
978 u32 tbtt_shift;
979 u32 bcn_cnt_tmr;
980 u32 tsftr_l;
981 u32 tsftr_h;
982 u32 md_tsft;
983 u32 bss_color;
984 u32 mbssid;
985 u32 mbssid_drop;
986 u32 tsf_sync;
987 u32 ptcl_dbg;
988 u32 ptcl_dbg_info;
989 u32 bcn_drop_all;
990 u32 hiq_win[RTW89_PORT_NUM];
991 };
992
993 struct rtw89_txwd_body {
994 __le32 dword0;
995 __le32 dword1;
996 __le32 dword2;
997 __le32 dword3;
998 __le32 dword4;
999 __le32 dword5;
1000 } __packed;
1001
1002 struct rtw89_txwd_body_v1 {
1003 __le32 dword0;
1004 __le32 dword1;
1005 __le32 dword2;
1006 __le32 dword3;
1007 __le32 dword4;
1008 __le32 dword5;
1009 __le32 dword6;
1010 __le32 dword7;
1011 } __packed;
1012
1013 struct rtw89_txwd_body_v2 {
1014 __le32 dword0;
1015 __le32 dword1;
1016 __le32 dword2;
1017 __le32 dword3;
1018 __le32 dword4;
1019 __le32 dword5;
1020 __le32 dword6;
1021 __le32 dword7;
1022 } __packed;
1023
1024 struct rtw89_txwd_info {
1025 __le32 dword0;
1026 __le32 dword1;
1027 __le32 dword2;
1028 __le32 dword3;
1029 __le32 dword4;
1030 __le32 dword5;
1031 } __packed;
1032
1033 struct rtw89_txwd_info_v2 {
1034 __le32 dword0;
1035 __le32 dword1;
1036 __le32 dword2;
1037 __le32 dword3;
1038 __le32 dword4;
1039 __le32 dword5;
1040 __le32 dword6;
1041 __le32 dword7;
1042 } __packed;
1043
1044 struct rtw89_rx_desc_info {
1045 u16 pkt_size;
1046 u8 pkt_type;
1047 u8 drv_info_size;
1048 u8 phy_rpt_size;
1049 u8 hdr_cnv_size;
1050 u8 shift;
1051 u8 wl_hd_iv_len;
1052 bool long_rxdesc;
1053 bool bb_sel;
1054 bool mac_info_valid;
1055 u16 data_rate;
1056 u8 gi_ltf;
1057 u8 bw;
1058 u32 free_run_cnt;
1059 u8 user_id;
1060 bool sr_en;
1061 u8 ppdu_cnt;
1062 u8 ppdu_type;
1063 bool icv_err;
1064 bool crc32_err;
1065 bool hw_dec;
1066 bool sw_dec;
1067 bool addr1_match;
1068 u8 frag;
1069 u16 seq;
1070 u8 frame_type;
1071 u8 rx_pl_id;
1072 bool addr_cam_valid;
1073 u8 addr_cam_id;
1074 u8 sec_cam_id;
1075 u8 mac_id;
1076 u16 offset;
1077 u16 rxd_len;
1078 bool ready;
1079 };
1080
1081 struct rtw89_rxdesc_short {
1082 __le32 dword0;
1083 __le32 dword1;
1084 __le32 dword2;
1085 __le32 dword3;
1086 } __packed;
1087
1088 struct rtw89_rxdesc_short_v2 {
1089 __le32 dword0;
1090 __le32 dword1;
1091 __le32 dword2;
1092 __le32 dword3;
1093 __le32 dword4;
1094 __le32 dword5;
1095 } __packed;
1096
1097 struct rtw89_rxdesc_long {
1098 __le32 dword0;
1099 __le32 dword1;
1100 __le32 dword2;
1101 __le32 dword3;
1102 __le32 dword4;
1103 __le32 dword5;
1104 __le32 dword6;
1105 __le32 dword7;
1106 } __packed;
1107
1108 struct rtw89_rxdesc_long_v2 {
1109 __le32 dword0;
1110 __le32 dword1;
1111 __le32 dword2;
1112 __le32 dword3;
1113 __le32 dword4;
1114 __le32 dword5;
1115 __le32 dword6;
1116 __le32 dword7;
1117 __le32 dword8;
1118 __le32 dword9;
1119 } __packed;
1120
1121 struct rtw89_tx_desc_info {
1122 u16 pkt_size;
1123 u8 wp_offset;
1124 u8 mac_id;
1125 u8 qsel;
1126 u8 ch_dma;
1127 u8 hdr_llc_len;
1128 bool is_bmc;
1129 bool en_wd_info;
1130 bool wd_page;
1131 bool use_rate;
1132 bool dis_data_fb;
1133 bool tid_indicate;
1134 bool agg_en;
1135 bool bk;
1136 u8 ampdu_density;
1137 u8 ampdu_num;
1138 bool sec_en;
1139 u8 addr_info_nr;
1140 u8 sec_keyid;
1141 u8 sec_type;
1142 u8 sec_cam_idx;
1143 u8 sec_seq[6];
1144 u16 data_rate;
1145 u16 data_retry_lowest_rate;
1146 bool fw_dl;
1147 u16 seq;
1148 bool a_ctrl_bsr;
1149 u8 hw_ssn_sel;
1150 #define RTW89_MGMT_HW_SSN_SEL 1
1151 u8 hw_seq_mode;
1152 #define RTW89_MGMT_HW_SEQ_MODE 1
1153 bool hiq;
1154 u8 port;
1155 bool er_cap;
1156 bool stbc;
1157 bool ldpc;
1158 };
1159
1160 struct rtw89_core_tx_request {
1161 enum rtw89_core_tx_type tx_type;
1162
1163 struct sk_buff *skb;
1164 struct ieee80211_vif *vif;
1165 struct ieee80211_sta *sta;
1166 struct rtw89_tx_desc_info desc_info;
1167 };
1168
1169 struct rtw89_txq {
1170 struct list_head list;
1171 unsigned long flags;
1172 int wait_cnt;
1173 };
1174
1175 struct rtw89_mac_ax_gnt {
1176 u8 gnt_bt_sw_en;
1177 u8 gnt_bt;
1178 u8 gnt_wl_sw_en;
1179 u8 gnt_wl;
1180 } __packed;
1181
1182 struct rtw89_mac_ax_wl_act {
1183 u8 wlan_act_en;
1184 u8 wlan_act;
1185 };
1186
1187 #define RTW89_MAC_AX_COEX_GNT_NR 2
1188 struct rtw89_mac_ax_coex_gnt {
1189 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1190 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1191 };
1192
1193 enum rtw89_btc_ncnt {
1194 BTC_NCNT_POWER_ON = 0x0,
1195 BTC_NCNT_POWER_OFF,
1196 BTC_NCNT_INIT_COEX,
1197 BTC_NCNT_SCAN_START,
1198 BTC_NCNT_SCAN_FINISH,
1199 BTC_NCNT_SPECIAL_PACKET,
1200 BTC_NCNT_SWITCH_BAND,
1201 BTC_NCNT_RFK_TIMEOUT,
1202 BTC_NCNT_SHOW_COEX_INFO,
1203 BTC_NCNT_ROLE_INFO,
1204 BTC_NCNT_CONTROL,
1205 BTC_NCNT_RADIO_STATE,
1206 BTC_NCNT_CUSTOMERIZE,
1207 BTC_NCNT_WL_RFK,
1208 BTC_NCNT_WL_STA,
1209 BTC_NCNT_WL_STA_LAST,
1210 BTC_NCNT_FWINFO,
1211 BTC_NCNT_TIMER,
1212 BTC_NCNT_SWITCH_CHBW,
1213 BTC_NCNT_RESUME_DL_FW,
1214 BTC_NCNT_COUNTRYCODE,
1215 BTC_NCNT_NUM,
1216 };
1217
1218 enum rtw89_btc_btinfo {
1219 BTC_BTINFO_L0 = 0,
1220 BTC_BTINFO_L1,
1221 BTC_BTINFO_L2,
1222 BTC_BTINFO_L3,
1223 BTC_BTINFO_H0,
1224 BTC_BTINFO_H1,
1225 BTC_BTINFO_H2,
1226 BTC_BTINFO_H3,
1227 BTC_BTINFO_MAX
1228 };
1229
1230 enum rtw89_btc_dcnt {
1231 BTC_DCNT_RUN = 0x0,
1232 BTC_DCNT_CX_RUNINFO,
1233 BTC_DCNT_RPT,
1234 BTC_DCNT_RPT_HANG,
1235 BTC_DCNT_CYCLE,
1236 BTC_DCNT_CYCLE_HANG,
1237 BTC_DCNT_W1,
1238 BTC_DCNT_W1_HANG,
1239 BTC_DCNT_B1,
1240 BTC_DCNT_B1_HANG,
1241 BTC_DCNT_TDMA_NONSYNC,
1242 BTC_DCNT_SLOT_NONSYNC,
1243 BTC_DCNT_BTCNT_HANG,
1244 BTC_DCNT_BTTX_HANG,
1245 BTC_DCNT_WL_SLOT_DRIFT,
1246 BTC_DCNT_WL_STA_LAST,
1247 BTC_DCNT_BT_SLOT_DRIFT,
1248 BTC_DCNT_BT_SLOT_FLOOD,
1249 BTC_DCNT_FDDT_TRIG,
1250 BTC_DCNT_E2G,
1251 BTC_DCNT_E2G_HANG,
1252 BTC_DCNT_WL_FW_VER_MATCH,
1253 BTC_DCNT_NULL_TX_FAIL,
1254 BTC_DCNT_WL_STA_NTFY,
1255 BTC_DCNT_NUM,
1256 };
1257
1258 enum rtw89_btc_wl_state_cnt {
1259 BTC_WCNT_SCANAP = 0x0,
1260 BTC_WCNT_DHCP,
1261 BTC_WCNT_EAPOL,
1262 BTC_WCNT_ARP,
1263 BTC_WCNT_SCBDUPDATE,
1264 BTC_WCNT_RFK_REQ,
1265 BTC_WCNT_RFK_GO,
1266 BTC_WCNT_RFK_REJECT,
1267 BTC_WCNT_RFK_TIMEOUT,
1268 BTC_WCNT_CH_UPDATE,
1269 BTC_WCNT_DBCC_ALL_2G,
1270 BTC_WCNT_DBCC_CHG,
1271 BTC_WCNT_RX_OK_LAST,
1272 BTC_WCNT_RX_OK_LAST2S,
1273 BTC_WCNT_RX_ERR_LAST,
1274 BTC_WCNT_RX_ERR_LAST2S,
1275 BTC_WCNT_RX_LAST,
1276 BTC_WCNT_NUM
1277 };
1278
1279 enum rtw89_btc_bt_state_cnt {
1280 BTC_BCNT_RETRY = 0x0,
1281 BTC_BCNT_REINIT,
1282 BTC_BCNT_REENABLE,
1283 BTC_BCNT_SCBDREAD,
1284 BTC_BCNT_RELINK,
1285 BTC_BCNT_IGNOWL,
1286 BTC_BCNT_INQPAG,
1287 BTC_BCNT_INQ,
1288 BTC_BCNT_PAGE,
1289 BTC_BCNT_ROLESW,
1290 BTC_BCNT_AFH,
1291 BTC_BCNT_INFOUPDATE,
1292 BTC_BCNT_INFOSAME,
1293 BTC_BCNT_SCBDUPDATE,
1294 BTC_BCNT_HIPRI_TX,
1295 BTC_BCNT_HIPRI_RX,
1296 BTC_BCNT_LOPRI_TX,
1297 BTC_BCNT_LOPRI_RX,
1298 BTC_BCNT_POLUT,
1299 BTC_BCNT_POLUT_NOW,
1300 BTC_BCNT_POLUT_DIFF,
1301 BTC_BCNT_RATECHG,
1302 BTC_BCNT_NUM,
1303 };
1304
1305 enum rtw89_btc_bt_profile {
1306 BTC_BT_NOPROFILE = 0,
1307 BTC_BT_HFP = BIT(0),
1308 BTC_BT_HID = BIT(1),
1309 BTC_BT_A2DP = BIT(2),
1310 BTC_BT_PAN = BIT(3),
1311 BTC_PROFILE_MAX = 4,
1312 };
1313
1314 struct rtw89_btc_ant_info {
1315 u8 type; /* shared, dedicated */
1316 u8 num;
1317 u8 isolation;
1318
1319 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1320 u8 diversity: 1;
1321 u8 btg_pos: 2;
1322 u8 stream_cnt: 4;
1323 };
1324
1325 struct rtw89_btc_ant_info_v7 {
1326 u8 type; /* shared, dedicated(non-shared) */
1327 u8 num; /* antenna count */
1328 u8 isolation;
1329 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1330
1331 u8 diversity; /* only for wifi use 1-antenna */
1332 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1333 u8 stream_cnt; /* spatial_stream count */
1334 u8 rsvd;
1335 } __packed;
1336
1337 enum rtw89_tfc_dir {
1338 RTW89_TFC_UL,
1339 RTW89_TFC_DL,
1340 };
1341
1342 struct rtw89_btc_wl_smap {
1343 u32 busy: 1;
1344 u32 scan: 1;
1345 u32 connecting: 1;
1346 u32 roaming: 1;
1347 u32 dbccing: 1;
1348 u32 transacting: 1;
1349 u32 _4way: 1;
1350 u32 rf_off: 1;
1351 u32 lps: 2;
1352 u32 ips: 1;
1353 u32 init_ok: 1;
1354 u32 traffic_dir : 2;
1355 u32 rf_off_pre: 1;
1356 u32 lps_pre: 2;
1357 u32 lps_exiting: 1;
1358 u32 emlsr: 1;
1359 };
1360
1361 enum rtw89_tfc_lv {
1362 RTW89_TFC_IDLE,
1363 RTW89_TFC_ULTRA_LOW,
1364 RTW89_TFC_LOW,
1365 RTW89_TFC_MID,
1366 RTW89_TFC_HIGH,
1367 };
1368
1369 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1370 DECLARE_EWMA(tp, 10, 2);
1371
1372 struct rtw89_traffic_stats {
1373 /* units in bytes */
1374 u64 tx_unicast;
1375 u64 rx_unicast;
1376 u32 tx_avg_len;
1377 u32 rx_avg_len;
1378
1379 /* count for packets */
1380 u64 tx_cnt;
1381 u64 rx_cnt;
1382
1383 /* units in Mbps */
1384 u32 tx_throughput;
1385 u32 rx_throughput;
1386 u32 tx_throughput_raw;
1387 u32 rx_throughput_raw;
1388
1389 u32 rx_tf_acc;
1390 u32 rx_tf_periodic;
1391
1392 enum rtw89_tfc_lv tx_tfc_lv;
1393 enum rtw89_tfc_lv rx_tfc_lv;
1394 struct ewma_tp tx_ewma_tp;
1395 struct ewma_tp rx_ewma_tp;
1396
1397 u16 tx_rate;
1398 u16 rx_rate;
1399 };
1400
1401 struct rtw89_btc_chdef {
1402 u8 center_ch;
1403 u8 band;
1404 u8 chan;
1405 enum rtw89_sc_offset offset;
1406 enum rtw89_bandwidth bw;
1407 };
1408
1409 struct rtw89_btc_statistic {
1410 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1411 struct rtw89_traffic_stats traffic;
1412 };
1413
1414 #define BTC_WL_RSSI_THMAX 4
1415
1416 struct rtw89_btc_wl_link_info {
1417 struct rtw89_btc_chdef chdef;
1418 struct rtw89_btc_statistic stat;
1419 enum rtw89_tfc_dir dir;
1420 u8 rssi_state[BTC_WL_RSSI_THMAX];
1421 u8 mac_addr[ETH_ALEN];
1422 u8 busy;
1423 u8 ch;
1424 u8 bw;
1425 u8 band;
1426 u8 role;
1427 u8 pid;
1428 u8 phy;
1429 u8 dtim_period;
1430 u8 mode;
1431 u8 tx_1ss_limit;
1432
1433 u8 mac_id;
1434 u8 tx_retry;
1435
1436 u32 bcn_period;
1437 u32 busy_t;
1438 u32 tx_time;
1439 u32 client_cnt;
1440 u32 rx_rate_drop_cnt;
1441 u32 noa_duration;
1442
1443 u32 active: 1;
1444 u32 noa: 1;
1445 u32 client_ps: 1;
1446 u32 connected: 2;
1447 };
1448
1449 union rtw89_btc_wl_state_map {
1450 u32 val;
1451 struct rtw89_btc_wl_smap map;
1452 };
1453
1454 struct rtw89_btc_bt_hfp_desc {
1455 u32 exist: 1;
1456 u32 type: 2;
1457 u32 rsvd: 29;
1458 };
1459
1460 struct rtw89_btc_bt_hid_desc {
1461 u32 exist: 1;
1462 u32 slot_info: 2;
1463 u32 pair_cnt: 2;
1464 u32 type: 8;
1465 u32 rsvd: 19;
1466 };
1467
1468 struct rtw89_btc_bt_a2dp_desc {
1469 u8 exist: 1;
1470 u8 exist_last: 1;
1471 u8 play_latency: 1;
1472 u8 type: 3;
1473 u8 active: 1;
1474 u8 sink: 1;
1475 u32 handle_update: 1;
1476 u32 devinfo_query: 1;
1477 u32 no_empty_streak_2s: 8;
1478 u32 no_empty_streak_max: 8;
1479 u32 rsvd: 6;
1480
1481 u8 bitpool;
1482 u16 vendor_id;
1483 u32 device_name;
1484 u32 flush_time;
1485 };
1486
1487 struct rtw89_btc_bt_pan_desc {
1488 u32 exist: 1;
1489 u32 type: 1;
1490 u32 active: 1;
1491 u32 rsvd: 29;
1492 };
1493
1494 struct rtw89_btc_bt_rfk_info {
1495 u32 run: 1;
1496 u32 req: 1;
1497 u32 timeout: 1;
1498 u32 rsvd: 29;
1499 };
1500
1501 union rtw89_btc_bt_rfk_info_map {
1502 u32 val;
1503 struct rtw89_btc_bt_rfk_info map;
1504 };
1505
1506 struct rtw89_btc_bt_ver_info {
1507 u32 fw_coex; /* match with which coex_ver */
1508 u32 fw;
1509 };
1510
1511 struct rtw89_btc_bool_sta_chg {
1512 u32 now: 1;
1513 u32 last: 1;
1514 u32 remain: 1;
1515 u32 srvd: 29;
1516 };
1517
1518 struct rtw89_btc_u8_sta_chg {
1519 u8 now;
1520 u8 last;
1521 u8 remain;
1522 u8 rsvd;
1523 };
1524
1525 struct rtw89_btc_wl_scan_info {
1526 u8 band[RTW89_PHY_MAX];
1527 u8 phy_map;
1528 u8 rsvd;
1529 };
1530
1531 struct rtw89_btc_wl_dbcc_info {
1532 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1533 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1534 u8 real_band[RTW89_PHY_MAX];
1535 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1536 };
1537
1538 struct rtw89_btc_wl_active_role {
1539 u8 connected: 1;
1540 u8 pid: 3;
1541 u8 phy: 1;
1542 u8 noa: 1;
1543 u8 band: 2;
1544
1545 u8 client_ps: 1;
1546 u8 bw: 7;
1547
1548 u8 role;
1549 u8 ch;
1550
1551 u16 tx_lvl;
1552 u16 rx_lvl;
1553 u16 tx_rate;
1554 u16 rx_rate;
1555 };
1556
1557 struct rtw89_btc_wl_active_role_v1 {
1558 u8 connected: 1;
1559 u8 pid: 3;
1560 u8 phy: 1;
1561 u8 noa: 1;
1562 u8 band: 2;
1563
1564 u8 client_ps: 1;
1565 u8 bw: 7;
1566
1567 u8 role;
1568 u8 ch;
1569
1570 u16 tx_lvl;
1571 u16 rx_lvl;
1572 u16 tx_rate;
1573 u16 rx_rate;
1574
1575 u32 noa_duration; /* ms */
1576 };
1577
1578 struct rtw89_btc_wl_active_role_v2 {
1579 u8 connected: 1;
1580 u8 pid: 3;
1581 u8 phy: 1;
1582 u8 noa: 1;
1583 u8 band: 2;
1584
1585 u8 client_ps: 1;
1586 u8 bw: 7;
1587
1588 u8 role;
1589 u8 ch;
1590
1591 u32 noa_duration; /* ms */
1592 };
1593
1594 struct rtw89_btc_wl_role_info_bpos {
1595 u16 none: 1;
1596 u16 station: 1;
1597 u16 ap: 1;
1598 u16 vap: 1;
1599 u16 adhoc: 1;
1600 u16 adhoc_master: 1;
1601 u16 mesh: 1;
1602 u16 moniter: 1;
1603 u16 p2p_device: 1;
1604 u16 p2p_gc: 1;
1605 u16 p2p_go: 1;
1606 u16 nan: 1;
1607 };
1608
1609 struct rtw89_btc_wl_scc_ctrl {
1610 u8 null_role1;
1611 u8 null_role2;
1612 u8 ebt_null; /* if tx null at EBT slot */
1613 };
1614
1615 union rtw89_btc_wl_role_info_map {
1616 u16 val;
1617 struct rtw89_btc_wl_role_info_bpos role;
1618 };
1619
1620 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1621 u8 connect_cnt;
1622 u8 link_mode;
1623 union rtw89_btc_wl_role_info_map role_map;
1624 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1625 };
1626
1627 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1628 u8 connect_cnt;
1629 u8 link_mode;
1630 union rtw89_btc_wl_role_info_map role_map;
1631 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1632 u32 mrole_type; /* btc_wl_mrole_type */
1633 u32 mrole_noa_duration; /* ms */
1634
1635 u32 dbcc_en: 1;
1636 u32 dbcc_chg: 1;
1637 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1638 u32 link_mode_chg: 1;
1639 u32 rsvd: 27;
1640 };
1641
1642 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1643 u8 connect_cnt;
1644 u8 link_mode;
1645 union rtw89_btc_wl_role_info_map role_map;
1646 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1647 u32 mrole_type; /* btc_wl_mrole_type */
1648 u32 mrole_noa_duration; /* ms */
1649
1650 u32 dbcc_en: 1;
1651 u32 dbcc_chg: 1;
1652 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1653 u32 link_mode_chg: 1;
1654 u32 rsvd: 27;
1655 };
1656
1657 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1658 u8 connected;
1659 u8 pid;
1660 u8 phy;
1661 u8 noa;
1662
1663 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1664 u8 active; /* 0:rlink is under doze */
1665 u8 bw; /* enum channel_width */
1666 u8 role; /*enum role_type */
1667
1668 u8 ch;
1669 u8 noa_dur; /* ms */
1670 u8 client_cnt; /* for Role = P2P-Go/AP */
1671 u8 mode; /* wifi protocol */
1672 } __packed;
1673
1674 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1675 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1676 u8 connect_cnt;
1677 u8 link_mode;
1678 u8 link_mode_chg;
1679 u8 p2p_2g;
1680
1681 u8 pta_req_band;
1682 u8 dbcc_en; /* 1+1 and 2.4G-included */
1683 u8 dbcc_chg;
1684 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1685
1686 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1687
1688 u32 role_map;
1689 u32 mrole_type; /* btc_wl_mrole_type */
1690 u32 mrole_noa_duration; /* ms */
1691 } __packed;
1692
1693 struct rtw89_btc_wl_ver_info {
1694 u32 fw_coex; /* match with which coex_ver */
1695 u32 fw;
1696 u32 mac;
1697 u32 bb;
1698 u32 rf;
1699 };
1700
1701 struct rtw89_btc_wl_afh_info {
1702 u8 en;
1703 u8 ch;
1704 u8 bw;
1705 u8 rsvd;
1706 } __packed;
1707
1708 struct rtw89_btc_wl_rfk_info {
1709 u32 state: 2;
1710 u32 path_map: 4;
1711 u32 phy_map: 2;
1712 u32 band: 2;
1713 u32 type: 8;
1714 u32 rsvd: 14;
1715
1716 u32 start_time;
1717 u32 proc_time;
1718 };
1719
1720 struct rtw89_btc_bt_smap {
1721 u32 connect: 1;
1722 u32 ble_connect: 1;
1723 u32 acl_busy: 1;
1724 u32 sco_busy: 1;
1725 u32 mesh_busy: 1;
1726 u32 inq_pag: 1;
1727 };
1728
1729 union rtw89_btc_bt_state_map {
1730 u32 val;
1731 struct rtw89_btc_bt_smap map;
1732 };
1733
1734 #define BTC_BT_RSSI_THMAX 4
1735 #define BTC_BT_AFH_GROUP 12
1736 #define BTC_BT_AFH_LE_GROUP 5
1737
1738 struct rtw89_btc_bt_link_info {
1739 struct rtw89_btc_u8_sta_chg profile_cnt;
1740 struct rtw89_btc_bool_sta_chg multi_link;
1741 struct rtw89_btc_bool_sta_chg relink;
1742 struct rtw89_btc_bt_hfp_desc hfp_desc;
1743 struct rtw89_btc_bt_hid_desc hid_desc;
1744 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1745 struct rtw89_btc_bt_pan_desc pan_desc;
1746 union rtw89_btc_bt_state_map status;
1747
1748 u8 sut_pwr_level[BTC_PROFILE_MAX];
1749 u8 golden_rx_shift[BTC_PROFILE_MAX];
1750 u8 rssi_state[BTC_BT_RSSI_THMAX];
1751 u8 afh_map[BTC_BT_AFH_GROUP];
1752 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1753
1754 u32 role_sw: 1;
1755 u32 slave_role: 1;
1756 u32 afh_update: 1;
1757 u32 cqddr: 1;
1758 u32 rssi: 8;
1759 u32 tx_3m: 1;
1760 u32 rsvd: 19;
1761 };
1762
1763 struct rtw89_btc_3rdcx_info {
1764 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1765 u8 hw_coex;
1766 u16 rsvd;
1767 };
1768
1769 struct rtw89_btc_dm_emap {
1770 u32 init: 1;
1771 u32 pta_owner: 1;
1772 u32 wl_rfk_timeout: 1;
1773 u32 bt_rfk_timeout: 1;
1774 u32 wl_fw_hang: 1;
1775 u32 cycle_hang: 1;
1776 u32 w1_hang: 1;
1777 u32 b1_hang: 1;
1778 u32 tdma_no_sync: 1;
1779 u32 slot_no_sync: 1;
1780 u32 wl_slot_drift: 1;
1781 u32 bt_slot_drift: 1;
1782 u32 role_num_mismatch: 1;
1783 u32 null1_tx_late: 1;
1784 u32 bt_afh_conflict: 1;
1785 u32 bt_leafh_conflict: 1;
1786 u32 bt_slot_flood: 1;
1787 u32 wl_e2g_hang: 1;
1788 u32 wl_ver_mismatch: 1;
1789 u32 bt_ver_mismatch: 1;
1790 u32 rfe_type0: 1;
1791 u32 h2c_buffer_over: 1;
1792 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1793 u32 wl_no_sta_ntfy: 1;
1794
1795 u32 h2c_bmap_mismatch: 1;
1796 u32 c2h_bmap_mismatch: 1;
1797 u32 h2c_struct_invalid: 1;
1798 u32 c2h_struct_invalid: 1;
1799 u32 h2c_c2h_buffer_mismatch: 1;
1800 };
1801
1802 union rtw89_btc_dm_error_map {
1803 u32 val;
1804 struct rtw89_btc_dm_emap map;
1805 };
1806
1807 struct rtw89_btc_rf_para {
1808 u32 tx_pwr_freerun;
1809 u32 rx_gain_freerun;
1810 u32 tx_pwr_perpkt;
1811 u32 rx_gain_perpkt;
1812 };
1813
1814 struct rtw89_btc_wl_nhm {
1815 u8 instant_wl_nhm_dbm;
1816 u8 instant_wl_nhm_per_mhz;
1817 u16 valid_record_times;
1818 s8 record_pwr[16];
1819 u8 record_ratio[16];
1820 s8 pwr; /* dbm_per_MHz */
1821 u8 ratio;
1822 u8 current_status;
1823 u8 refresh;
1824 bool start_flag;
1825 s8 pwr_max;
1826 s8 pwr_min;
1827 };
1828
1829 struct rtw89_btc_wl_info {
1830 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1831 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1832 struct rtw89_btc_wl_rfk_info rfk_info;
1833 struct rtw89_btc_wl_ver_info ver_info;
1834 struct rtw89_btc_wl_afh_info afh_info;
1835 struct rtw89_btc_wl_role_info role_info;
1836 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1837 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1838 struct rtw89_btc_wl_role_info_v8 role_info_v8;
1839 struct rtw89_btc_wl_scan_info scan_info;
1840 struct rtw89_btc_wl_dbcc_info dbcc_info;
1841 struct rtw89_btc_rf_para rf_para;
1842 struct rtw89_btc_wl_nhm nhm;
1843 union rtw89_btc_wl_state_map status;
1844
1845 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1846 u8 rssi_level;
1847 u8 cn_report;
1848 u8 coex_mode;
1849 u8 pta_req_mac;
1850 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */
1851
1852 bool is_5g_hi_channel;
1853 bool pta_reg_mac_chg;
1854 bool bg_mode;
1855 bool scbd_change;
1856 bool fw_ver_mismatch;
1857 u32 scbd;
1858 };
1859
1860 struct rtw89_btc_module {
1861 struct rtw89_btc_ant_info ant;
1862 u8 rfe_type;
1863 u8 cv;
1864
1865 u8 bt_solo: 1;
1866 u8 bt_pos: 1;
1867 u8 switch_type: 1;
1868 u8 wa_type: 3;
1869
1870 u8 kt_ver_adie;
1871 };
1872
1873 struct rtw89_btc_module_v7 {
1874 u8 rfe_type;
1875 u8 kt_ver;
1876 u8 bt_solo;
1877 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
1878
1879 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1880 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1881 u8 kt_ver_adie;
1882 u8 rsvd;
1883
1884 struct rtw89_btc_ant_info_v7 ant;
1885 } __packed;
1886
1887 union rtw89_btc_module_info {
1888 struct rtw89_btc_module md;
1889 struct rtw89_btc_module_v7 md_v7;
1890 };
1891
1892 #define RTW89_BTC_DM_MAXSTEP 30
1893 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1894
1895 struct rtw89_btc_dm_step {
1896 u16 step[RTW89_BTC_DM_MAXSTEP];
1897 u8 step_pos;
1898 bool step_ov;
1899 };
1900
1901 struct rtw89_btc_init_info {
1902 struct rtw89_btc_module module;
1903 u8 wl_guard_ch;
1904
1905 u8 wl_only: 1;
1906 u8 wl_init_ok: 1;
1907 u8 dbcc_en: 1;
1908 u8 cx_other: 1;
1909 u8 bt_only: 1;
1910
1911 u16 rsvd;
1912 };
1913
1914 struct rtw89_btc_init_info_v7 {
1915 u8 wl_guard_ch;
1916 u8 wl_only;
1917 u8 wl_init_ok;
1918 u8 rsvd3;
1919
1920 u8 cx_other;
1921 u8 bt_only;
1922 u8 pta_mode;
1923 u8 pta_direction;
1924
1925 struct rtw89_btc_module_v7 module;
1926 } __packed;
1927
1928 union rtw89_btc_init_info_u {
1929 struct rtw89_btc_init_info init;
1930 struct rtw89_btc_init_info_v7 init_v7;
1931 };
1932
1933 struct rtw89_btc_wl_tx_limit_para {
1934 u16 enable;
1935 u32 tx_time; /* unit: us */
1936 u16 tx_retry;
1937 };
1938
1939 enum rtw89_btc_bt_scan_type {
1940 BTC_SCAN_INQ = 0,
1941 BTC_SCAN_PAGE,
1942 BTC_SCAN_BLE,
1943 BTC_SCAN_INIT,
1944 BTC_SCAN_TV,
1945 BTC_SCAN_ADV,
1946 BTC_SCAN_MAX1,
1947 };
1948
1949 enum rtw89_btc_ble_scan_type {
1950 CXSCAN_BG = 0,
1951 CXSCAN_INIT,
1952 CXSCAN_LE,
1953 CXSCAN_MAX
1954 };
1955
1956 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1957 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1958
1959 struct rtw89_btc_bt_scan_info_v1 {
1960 __le16 win;
1961 __le16 intvl;
1962 __le32 flags;
1963 } __packed;
1964
1965 struct rtw89_btc_bt_scan_info_v2 {
1966 __le16 win;
1967 __le16 intvl;
1968 } __packed;
1969
1970 struct rtw89_btc_fbtc_btscan_v1 {
1971 u8 fver; /* btc_ver::fcxbtscan */
1972 u8 rsvd;
1973 __le16 rsvd2;
1974 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
1975 } __packed;
1976
1977 struct rtw89_btc_fbtc_btscan_v2 {
1978 u8 fver; /* btc_ver::fcxbtscan */
1979 u8 type;
1980 __le16 rsvd2;
1981 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1982 } __packed;
1983
1984 struct rtw89_btc_fbtc_btscan_v7 {
1985 u8 fver; /* btc_ver::fcxbtscan */
1986 u8 type;
1987 u8 rsvd0;
1988 u8 rsvd1;
1989 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1990 } __packed;
1991
1992 union rtw89_btc_fbtc_btscan {
1993 struct rtw89_btc_fbtc_btscan_v1 v1;
1994 struct rtw89_btc_fbtc_btscan_v2 v2;
1995 struct rtw89_btc_fbtc_btscan_v7 v7;
1996 };
1997
1998 struct rtw89_btc_bt_info {
1999 struct rtw89_btc_bt_link_info link_info;
2000 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2001 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2002 struct rtw89_btc_bt_ver_info ver_info;
2003 struct rtw89_btc_bool_sta_chg enable;
2004 struct rtw89_btc_bool_sta_chg inq_pag;
2005 struct rtw89_btc_rf_para rf_para;
2006 union rtw89_btc_bt_rfk_info_map rfk_info;
2007
2008 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2009 u8 rssi_level;
2010
2011 u32 scbd;
2012 u32 feature;
2013
2014 u32 mbx_avl: 1;
2015 u32 whql_test: 1;
2016 u32 igno_wl: 1;
2017 u32 reinit: 1;
2018 u32 ble_scan_en: 1;
2019 u32 btg_type: 1;
2020 u32 inq: 1;
2021 u32 pag: 1;
2022 u32 run_patch_code: 1;
2023 u32 hi_lna_rx: 1;
2024 u32 scan_rx_low_pri: 1;
2025 u32 scan_info_update: 1;
2026 u32 lna_constrain: 3;
2027 u32 rsvd: 17;
2028 };
2029
2030 struct rtw89_btc_cx {
2031 struct rtw89_btc_wl_info wl;
2032 struct rtw89_btc_bt_info bt;
2033 struct rtw89_btc_3rdcx_info other;
2034 u32 state_map;
2035 u32 cnt_bt[BTC_BCNT_NUM];
2036 u32 cnt_wl[BTC_WCNT_NUM];
2037 };
2038
2039 struct rtw89_btc_fbtc_tdma {
2040 u8 type; /* btc_ver::fcxtdma */
2041 u8 rxflctrl;
2042 u8 txpause;
2043 u8 wtgle_n;
2044 u8 leak_n;
2045 u8 ext_ctrl;
2046 u8 rxflctrl_role;
2047 u8 option_ctrl;
2048 } __packed;
2049
2050 struct rtw89_btc_fbtc_tdma_v3 {
2051 u8 fver; /* btc_ver::fcxtdma */
2052 u8 rsvd;
2053 __le16 rsvd1;
2054 struct rtw89_btc_fbtc_tdma tdma;
2055 } __packed;
2056
2057 union rtw89_btc_fbtc_tdma_le32 {
2058 struct rtw89_btc_fbtc_tdma v1;
2059 struct rtw89_btc_fbtc_tdma_v3 v3;
2060 };
2061
2062 #define CXMREG_MAX 30
2063 #define CXMREG_MAX_V2 20
2064 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2065 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2066
2067 enum rtw89_btc_bt_sta_counter {
2068 BTC_BCNT_RFK_REQ = 0,
2069 BTC_BCNT_RFK_GO = 1,
2070 BTC_BCNT_RFK_REJECT = 2,
2071 BTC_BCNT_RFK_FAIL = 3,
2072 BTC_BCNT_RFK_TIMEOUT = 4,
2073 BTC_BCNT_HI_TX = 5,
2074 BTC_BCNT_HI_RX = 6,
2075 BTC_BCNT_LO_TX = 7,
2076 BTC_BCNT_LO_RX = 8,
2077 BTC_BCNT_POLLUTED = 9,
2078 BTC_BCNT_STA_MAX
2079 };
2080
2081 enum rtw89_btc_bt_sta_counter_v105 {
2082 BTC_BCNT_RFK_REQ_V105 = 0,
2083 BTC_BCNT_HI_TX_V105 = 1,
2084 BTC_BCNT_HI_RX_V105 = 2,
2085 BTC_BCNT_LO_TX_V105 = 3,
2086 BTC_BCNT_LO_RX_V105 = 4,
2087 BTC_BCNT_POLLUTED_V105 = 5,
2088 BTC_BCNT_STA_MAX_V105
2089 };
2090
2091 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2092 u16 fver; /* btc_ver::fcxbtcrpt */
2093 u16 rpt_cnt; /* tmr counters */
2094 u32 wl_fw_coex_ver; /* match which driver's coex version */
2095 u32 wl_fw_cx_offload;
2096 u32 wl_fw_ver;
2097 u32 rpt_enable;
2098 u32 rpt_para; /* ms */
2099 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2100 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2101 u32 mb_recv_cnt; /* fw recv mailbox counter */
2102 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2103 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2104 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2105 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2106 u32 c2h_cnt; /* fw send c2h counter */
2107 u32 h2c_cnt; /* fw recv h2c counter */
2108 } __packed;
2109
2110 struct rtw89_btc_fbtc_rpt_ctrl_info {
2111 __le32 cnt; /* fw report counter */
2112 __le32 en; /* report map */
2113 __le32 para; /* not used */
2114
2115 __le32 cnt_c2h; /* fw send c2h counter */
2116 __le32 cnt_h2c; /* fw recv h2c counter */
2117 __le32 len_c2h; /* The total length of the last C2H */
2118
2119 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2120 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2121 } __packed;
2122
2123 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2124 __le32 cx_ver; /* match which driver's coex version */
2125 __le32 fw_ver;
2126 __le32 en; /* report map */
2127
2128 __le16 cnt; /* fw report counter */
2129 __le16 cnt_c2h; /* fw send c2h counter */
2130 __le16 cnt_h2c; /* fw recv h2c counter */
2131 __le16 len_c2h; /* The total length of the last C2H */
2132
2133 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2134 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2135 } __packed;
2136
2137 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2138 __le16 cnt; /* fw report counter */
2139 __le16 cnt_c2h; /* fw send c2h counter */
2140 __le16 cnt_h2c; /* fw recv h2c counter */
2141 __le16 len_c2h; /* The total length of the last C2H */
2142
2143 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2144 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2145
2146 __le32 cx_ver; /* match which driver's coex version */
2147 __le32 fw_ver;
2148 __le32 en; /* report map */
2149 } __packed;
2150
2151 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2152 __le32 cx_ver; /* match which driver's coex version */
2153 __le32 cx_offload;
2154 __le32 fw_ver;
2155 } __packed;
2156
2157 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2158 __le32 cnt_empty; /* a2dp empty count */
2159 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
2160 __le32 cnt_tx;
2161 __le32 cnt_ack;
2162 __le32 cnt_nack;
2163 } __packed;
2164
2165 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2166 __le32 cnt_send_ok; /* fw send mailbox ok counter */
2167 __le32 cnt_send_fail; /* fw send mailbox fail counter */
2168 __le32 cnt_recv; /* fw recv mailbox counter */
2169 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2170 } __packed;
2171
2172 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2173 u8 fver;
2174 u8 rsvd;
2175 __le16 rsvd1;
2176 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2177 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2178 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2179 __le32 bt_cnt[BTC_BCNT_STA_MAX];
2180 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
2181 } __packed;
2182
2183 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2184 u8 fver;
2185 u8 rsvd;
2186 __le16 rsvd1;
2187
2188 u8 gnt_val[RTW89_PHY_MAX][4];
2189 __le16 bt_cnt[BTC_BCNT_STA_MAX];
2190
2191 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2192 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2193 } __packed;
2194
2195 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2196 u8 fver;
2197 u8 rsvd;
2198 __le16 rsvd1;
2199
2200 u8 gnt_val[RTW89_PHY_MAX][4];
2201 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2202
2203 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2204 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2205 } __packed;
2206
2207 struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2208 u8 fver;
2209 u8 rsvd0;
2210 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2211 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2212
2213 u8 gnt_val[RTW89_PHY_MAX][4];
2214 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2215
2216 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2217 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2218 } __packed;
2219
2220 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2221 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2222 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2223 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2224 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2225 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2226 };
2227
2228 enum rtw89_fbtc_ext_ctrl_type {
2229 CXECTL_OFF = 0x0, /* tdma off */
2230 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2231 CXECTL_EXT = 0x2,
2232 CXECTL_MAX
2233 };
2234
2235 union rtw89_btc_fbtc_rxflct {
2236 u8 val;
2237 u8 type: 3;
2238 u8 tgln_n: 5;
2239 };
2240
2241 enum rtw89_btc_cxst_state {
2242 CXST_OFF = 0x0,
2243 CXST_B2W = 0x1,
2244 CXST_W1 = 0x2,
2245 CXST_W2 = 0x3,
2246 CXST_W2B = 0x4,
2247 CXST_B1 = 0x5,
2248 CXST_B2 = 0x6,
2249 CXST_B3 = 0x7,
2250 CXST_B4 = 0x8,
2251 CXST_LK = 0x9,
2252 CXST_BLK = 0xa,
2253 CXST_E2G = 0xb,
2254 CXST_E5G = 0xc,
2255 CXST_EBT = 0xd,
2256 CXST_ENULL = 0xe,
2257 CXST_WLK = 0xf,
2258 CXST_W1FDD = 0x10,
2259 CXST_B1FDD = 0x11,
2260 CXST_MAX = 0x12,
2261 };
2262
2263 enum rtw89_btc_cxevnt {
2264 CXEVNT_TDMA_ENTRY = 0x0,
2265 CXEVNT_WL_TMR,
2266 CXEVNT_B1_TMR,
2267 CXEVNT_B2_TMR,
2268 CXEVNT_B3_TMR,
2269 CXEVNT_B4_TMR,
2270 CXEVNT_W2B_TMR,
2271 CXEVNT_B2W_TMR,
2272 CXEVNT_BCN_EARLY,
2273 CXEVNT_A2DP_EMPTY,
2274 CXEVNT_LK_END,
2275 CXEVNT_RX_ISR,
2276 CXEVNT_RX_FC0,
2277 CXEVNT_RX_FC1,
2278 CXEVNT_BT_RELINK,
2279 CXEVNT_BT_RETRY,
2280 CXEVNT_E2G,
2281 CXEVNT_E5G,
2282 CXEVNT_EBT,
2283 CXEVNT_ENULL,
2284 CXEVNT_DRV_WLK,
2285 CXEVNT_BCN_OK,
2286 CXEVNT_BT_CHANGE,
2287 CXEVNT_EBT_EXTEND,
2288 CXEVNT_E2G_NULL1,
2289 CXEVNT_B1FDD_TMR,
2290 CXEVNT_MAX
2291 };
2292
2293 enum {
2294 CXBCN_ALL = 0x0,
2295 CXBCN_ALL_OK,
2296 CXBCN_BT_SLOT,
2297 CXBCN_BT_OK,
2298 CXBCN_MAX
2299 };
2300
2301 enum btc_slot_type {
2302 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2303 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2304 CXSTYPE_NUM,
2305 };
2306
2307 enum { /* TIME */
2308 CXT_BT = 0x0,
2309 CXT_WL = 0x1,
2310 CXT_MAX
2311 };
2312
2313 enum { /* TIME-A2DP */
2314 CXT_FLCTRL_OFF = 0x0,
2315 CXT_FLCTRL_ON = 0x1,
2316 CXT_FLCTRL_MAX
2317 };
2318
2319 enum { /* STEP TYPE */
2320 CXSTEP_NONE = 0x0,
2321 CXSTEP_EVNT = 0x1,
2322 CXSTEP_SLOT = 0x2,
2323 CXSTEP_MAX,
2324 };
2325
2326 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2327 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2328 RPT_BT_AFH_SEQ_LE = 0x20
2329 };
2330
2331 #define BTC_DBG_MAX1 32
2332 struct rtw89_btc_fbtc_gpio_dbg_v1 {
2333 u8 fver; /* btc_ver::fcxgpiodbg */
2334 u8 rsvd;
2335 __le16 rsvd2;
2336 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2337 __le32 pre_state; /* the debug signal is 1 or 0 */
2338 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2339 } __packed;
2340
2341 struct rtw89_btc_fbtc_gpio_dbg_v7 {
2342 u8 fver;
2343 u8 rsvd0;
2344 u8 rsvd1;
2345 u8 rsvd2;
2346
2347 u8 gpio_map[BTC_DBG_MAX1];
2348
2349 __le32 en_map;
2350 __le32 pre_state;
2351 } __packed;
2352
2353 union rtw89_btc_fbtc_gpio_dbg {
2354 struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2355 struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2356 };
2357
2358 struct rtw89_btc_fbtc_mreg_val_v1 {
2359 u8 fver; /* btc_ver::fcxmreg */
2360 u8 reg_num;
2361 __le16 rsvd;
2362 __le32 mreg_val[CXMREG_MAX];
2363 } __packed;
2364
2365 struct rtw89_btc_fbtc_mreg_val_v2 {
2366 u8 fver; /* btc_ver::fcxmreg */
2367 u8 reg_num;
2368 __le16 rsvd;
2369 __le32 mreg_val[CXMREG_MAX_V2];
2370 } __packed;
2371
2372 struct rtw89_btc_fbtc_mreg_val_v7 {
2373 u8 fver;
2374 u8 reg_num;
2375 u8 rsvd0;
2376 u8 rsvd1;
2377 __le32 mreg_val[CXMREG_MAX_V2];
2378 } __packed;
2379
2380 union rtw89_btc_fbtc_mreg_val {
2381 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2382 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2383 struct rtw89_btc_fbtc_mreg_val_v7 v7;
2384 };
2385
2386 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2387 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2388 .offset = cpu_to_le32(__offset), }
2389
2390 struct rtw89_btc_fbtc_mreg {
2391 __le16 type;
2392 __le16 bytes;
2393 __le32 offset;
2394 } __packed;
2395
2396 struct rtw89_btc_fbtc_slot {
2397 __le16 dur;
2398 __le32 cxtbl;
2399 __le16 cxtype;
2400 } __packed;
2401
2402 struct rtw89_btc_fbtc_slots {
2403 u8 fver; /* btc_ver::fcxslots */
2404 u8 tbl_num;
2405 __le16 rsvd;
2406 __le32 update_map;
2407 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2408 } __packed;
2409
2410 struct rtw89_btc_fbtc_slot_v7 {
2411 __le16 dur; /* slot duration */
2412 __le16 cxtype;
2413 __le32 cxtbl;
2414 } __packed;
2415
2416 struct rtw89_btc_fbtc_slot_u16 {
2417 __le16 dur; /* slot duration */
2418 __le16 cxtype;
2419 __le16 cxtbl_l16; /* coex table [15:0] */
2420 __le16 cxtbl_h16; /* coex table [31:16] */
2421 } __packed;
2422
2423 struct rtw89_btc_fbtc_1slot_v7 {
2424 u8 fver;
2425 u8 sid; /* slot id */
2426 __le16 rsvd;
2427 struct rtw89_btc_fbtc_slot_v7 slot;
2428 } __packed;
2429
2430 struct rtw89_btc_fbtc_slots_v7 {
2431 u8 fver;
2432 u8 slot_cnt;
2433 u8 rsvd0;
2434 u8 rsvd1;
2435 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2436 __le32 update_map;
2437 } __packed;
2438
2439 union rtw89_btc_fbtc_slots_info {
2440 struct rtw89_btc_fbtc_slots v1;
2441 struct rtw89_btc_fbtc_slots_v7 v7;
2442 } __packed;
2443
2444 struct rtw89_btc_fbtc_step {
2445 u8 type;
2446 u8 val;
2447 __le16 difft;
2448 } __packed;
2449
2450 struct rtw89_btc_fbtc_steps_v2 {
2451 u8 fver; /* btc_ver::fcxstep */
2452 u8 rsvd;
2453 __le16 cnt;
2454 __le16 pos_old;
2455 __le16 pos_new;
2456 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2457 } __packed;
2458
2459 struct rtw89_btc_fbtc_steps_v3 {
2460 u8 fver;
2461 u8 en;
2462 __le16 rsvd;
2463 __le32 cnt;
2464 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2465 } __packed;
2466
2467 union rtw89_btc_fbtc_steps_info {
2468 struct rtw89_btc_fbtc_steps_v2 v2;
2469 struct rtw89_btc_fbtc_steps_v3 v3;
2470 };
2471
2472 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2473 u8 fver; /* btc_ver::fcxcysta */
2474 u8 rsvd;
2475 __le16 cycles; /* total cycle number */
2476 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2477 __le16 a2dpept; /* a2dp empty cnt */
2478 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2479 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2480 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2481 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2482 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2483 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2484 __le16 tavg_a2dpept; /* avg a2dp empty time */
2485 __le16 tmax_a2dpept; /* max a2dp empty time */
2486 __le16 tavg_lk; /* avg leak-slot time */
2487 __le16 tmax_lk; /* max leak-slot time */
2488 __le32 slot_cnt[CXST_MAX]; /* slot count */
2489 __le32 bcn_cnt[CXBCN_MAX];
2490 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2491 __le32 collision_cnt; /* counter for event/timer occur at same time */
2492 __le32 skip_cnt;
2493 __le32 exception;
2494 __le32 except_cnt;
2495 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2496 } __packed;
2497
2498 struct rtw89_btc_fbtc_fdd_try_info {
2499 __le16 cycles[CXT_FLCTRL_MAX];
2500 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2501 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2502 } __packed;
2503
2504 struct rtw89_btc_fbtc_cycle_time_info {
2505 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2506 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2507 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2508 } __packed;
2509
2510 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2511 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2512 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2513 } __packed;
2514
2515 struct rtw89_btc_fbtc_a2dp_trx_stat {
2516 u8 empty_cnt;
2517 u8 retry_cnt;
2518 u8 tx_rate;
2519 u8 tx_cnt;
2520 u8 ack_cnt;
2521 u8 nack_cnt;
2522 u8 rsvd1;
2523 u8 rsvd2;
2524 } __packed;
2525
2526 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2527 u8 empty_cnt;
2528 u8 retry_cnt;
2529 u8 tx_rate;
2530 u8 tx_cnt;
2531 u8 ack_cnt;
2532 u8 nack_cnt;
2533 u8 no_empty_cnt;
2534 u8 rsvd;
2535 } __packed;
2536
2537 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2538 __le16 cnt; /* a2dp empty cnt */
2539 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2540 __le16 tavg; /* avg a2dp empty time */
2541 __le16 tmax; /* max a2dp empty time */
2542 } __packed;
2543
2544 struct rtw89_btc_fbtc_cycle_leak_info {
2545 __le32 cnt_rximr; /* the rximr occur at leak slot */
2546 __le16 tavg; /* avg leak-slot time */
2547 __le16 tmax; /* max leak-slot time */
2548 } __packed;
2549
2550 struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2551 __le16 tavg;
2552 __le16 tamx;
2553 __le32 cnt_rximr;
2554 } __packed;
2555
2556 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2557 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2558
2559 struct rtw89_btc_fbtc_cycle_fddt_info {
2560 __le16 train_cycle;
2561 __le16 tp;
2562
2563 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2564 s8 bt_tx_power; /* decrease Tx power (dB) */
2565 s8 bt_rx_gain; /* LNA constrain level */
2566 u8 no_empty_cnt;
2567
2568 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2569 u8 cn; /* condition_num */
2570 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2571 u8 train_result; /* refer to enum btc_fddt_check_map */
2572 } __packed;
2573
2574 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2575 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2576
2577 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2578 __le16 train_cycle;
2579 __le16 tp;
2580
2581 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2582 s8 bt_tx_power; /* decrease Tx power (dB) */
2583 s8 bt_rx_gain; /* LNA constrain level */
2584 u8 no_empty_cnt;
2585
2586 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2587 u8 cn; /* condition_num */
2588 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2589 u8 train_result; /* refer to enum btc_fddt_check_map */
2590 } __packed;
2591
2592 struct rtw89_btc_fbtc_fddt_cell_status {
2593 s8 wl_tx_pwr;
2594 s8 bt_tx_pwr;
2595 s8 bt_rx_gain;
2596 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2597 } __packed;
2598
2599 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2600 u8 fver;
2601 u8 rsvd;
2602 __le16 cycles; /* total cycle number */
2603 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2604 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2605 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2606 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2607 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2608 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2609 __le32 slot_cnt[CXST_MAX]; /* slot count */
2610 __le32 bcn_cnt[CXBCN_MAX];
2611 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2612 __le32 skip_cnt;
2613 __le32 except_cnt;
2614 __le32 except_map;
2615 } __packed;
2616
2617 #define FDD_TRAIN_WL_DIRECTION 2
2618 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2619 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2620
2621 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2622 u8 fver;
2623 u8 rsvd;
2624 u8 collision_cnt; /* counter for event/timer occur at the same time */
2625 u8 except_cnt;
2626
2627 __le16 skip_cnt;
2628 __le16 cycles; /* total cycle number */
2629
2630 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2631 __le16 slot_cnt[CXST_MAX]; /* slot count */
2632 __le16 bcn_cnt[CXBCN_MAX];
2633 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2634 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2635 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2636 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2637 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2638 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2639 [FDD_TRAIN_WL_RSSI_LEVEL]
2640 [FDD_TRAIN_BT_RSSI_LEVEL];
2641 __le32 except_map;
2642 } __packed;
2643
2644 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2645 u8 fver;
2646 u8 rsvd;
2647 u8 collision_cnt; /* counter for event/timer occur at the same time */
2648 u8 except_cnt;
2649 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2650
2651 __le16 skip_cnt;
2652 __le16 cycles; /* total cycle number */
2653
2654 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2655 __le16 slot_cnt[CXST_MAX]; /* slot count */
2656 __le16 bcn_cnt[CXBCN_MAX];
2657 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2658 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2659 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2660 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2661 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2662 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2663 [FDD_TRAIN_WL_RSSI_LEVEL]
2664 [FDD_TRAIN_BT_RSSI_LEVEL];
2665 __le32 except_map;
2666 } __packed;
2667
2668 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2669 u8 fver;
2670 u8 rsvd;
2671 u8 collision_cnt; /* counter for event/timer occur at the same time */
2672 u8 except_cnt;
2673
2674 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2675
2676 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2677
2678 __le16 skip_cnt;
2679 __le16 cycles; /* total cycle number */
2680
2681 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2682 __le16 slot_cnt[CXST_MAX]; /* slot count */
2683 __le16 bcn_cnt[CXBCN_MAX];
2684
2685 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2686 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2687 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2688
2689 __le32 except_map;
2690 } __packed;
2691
2692 union rtw89_btc_fbtc_cysta_info {
2693 struct rtw89_btc_fbtc_cysta_v2 v2;
2694 struct rtw89_btc_fbtc_cysta_v3 v3;
2695 struct rtw89_btc_fbtc_cysta_v4 v4;
2696 struct rtw89_btc_fbtc_cysta_v5 v5;
2697 struct rtw89_btc_fbtc_cysta_v7 v7;
2698 };
2699
2700 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2701 u8 fver; /* btc_ver::fcxnullsta */
2702 u8 rsvd;
2703 __le16 rsvd2;
2704 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2705 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2706 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2707 } __packed;
2708
2709 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2710 u8 fver; /* btc_ver::fcxnullsta */
2711 u8 rsvd;
2712 __le16 rsvd2;
2713 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2714 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2715 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2716 } __packed;
2717
2718 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2719 u8 fver;
2720 u8 rsvd0;
2721 u8 rsvd1;
2722 u8 rsvd2;
2723
2724 __le32 tmax[2];
2725 __le32 tavg[2];
2726 __le32 result[2][5];
2727 } __packed;
2728
2729 union rtw89_btc_fbtc_cynullsta_info {
2730 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2731 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2732 struct rtw89_btc_fbtc_cynullsta_v7 v7;
2733 };
2734
2735 struct rtw89_btc_fbtc_btver_v1 {
2736 u8 fver; /* btc_ver::fcxbtver */
2737 u8 rsvd;
2738 __le16 rsvd2;
2739 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2740 __le32 fw_ver;
2741 __le32 feature;
2742 } __packed;
2743
2744 struct rtw89_btc_fbtc_btver_v7 {
2745 u8 fver;
2746 u8 rsvd0;
2747 u8 rsvd1;
2748 u8 rsvd2;
2749
2750 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2751 __le32 fw_ver;
2752 __le32 feature;
2753 } __packed;
2754
2755 union rtw89_btc_fbtc_btver {
2756 struct rtw89_btc_fbtc_btver_v1 v1;
2757 struct rtw89_btc_fbtc_btver_v7 v7;
2758 } __packed;
2759
2760 struct rtw89_btc_fbtc_btafh {
2761 u8 fver; /* btc_ver::fcxbtafh */
2762 u8 rsvd;
2763 __le16 rsvd2;
2764 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2765 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2766 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2767 } __packed;
2768
2769 struct rtw89_btc_fbtc_btafh_v2 {
2770 u8 fver; /* btc_ver::fcxbtafh */
2771 u8 rsvd;
2772 u8 rsvd2;
2773 u8 map_type;
2774 u8 afh_l[4];
2775 u8 afh_m[4];
2776 u8 afh_h[4];
2777 u8 afh_le_a[4];
2778 u8 afh_le_b[4];
2779 } __packed;
2780
2781 struct rtw89_btc_fbtc_btafh_v7 {
2782 u8 fver;
2783 u8 map_type;
2784 u8 rsvd0;
2785 u8 rsvd1;
2786 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2787 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2788 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2789 u8 afh_le_a[4];
2790 u8 afh_le_b[4];
2791 } __packed;
2792
2793 struct rtw89_btc_fbtc_btdevinfo {
2794 u8 fver; /* btc_ver::fcxbtdevinfo */
2795 u8 rsvd;
2796 __le16 vendor_id;
2797 __le32 dev_name; /* only 24 bits valid */
2798 __le32 flush_time;
2799 } __packed;
2800
2801 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2802 struct rtw89_btc_rf_trx_para {
2803 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2804 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2805 u8 bt_tx_power; /* decrease Tx power (dB) */
2806 u8 bt_rx_gain; /* LNA constrain level */
2807 };
2808
2809 struct rtw89_btc_trx_info {
2810 u8 tx_lvl;
2811 u8 rx_lvl;
2812 u8 wl_rssi;
2813 u8 bt_rssi;
2814
2815 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2816 s8 rx_gain; /* rx gain table index (TBD.) */
2817 s8 bt_tx_power; /* decrease Tx power (dB) */
2818 s8 bt_rx_gain; /* LNA constrain level */
2819
2820 u8 cn; /* condition_num */
2821 s8 nhm;
2822 u8 bt_profile;
2823 u8 rsvd2;
2824
2825 u16 tx_rate;
2826 u16 rx_rate;
2827
2828 u32 tx_tp;
2829 u32 rx_tp;
2830 u32 rx_err_ratio;
2831 };
2832
2833 union rtw89_btc_fbtc_slot_u {
2834 struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2835 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2836 };
2837
2838 struct rtw89_btc_dm {
2839 union rtw89_btc_fbtc_slot_u slot;
2840 union rtw89_btc_fbtc_slot_u slot_now;
2841 struct rtw89_btc_fbtc_tdma tdma;
2842 struct rtw89_btc_fbtc_tdma tdma_now;
2843 struct rtw89_mac_ax_coex_gnt gnt;
2844 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
2845 struct rtw89_btc_rf_trx_para rf_trx_para;
2846 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2847 struct rtw89_btc_dm_step dm_step;
2848 struct rtw89_btc_wl_scc_ctrl wl_scc;
2849 struct rtw89_btc_trx_info trx_info;
2850 union rtw89_btc_dm_error_map error;
2851 u32 cnt_dm[BTC_DCNT_NUM];
2852 u32 cnt_notify[BTC_NCNT_NUM];
2853
2854 u32 update_slot_map;
2855 u32 set_ant_path;
2856 u32 e2g_slot_limit;
2857 u32 e2g_slot_nulltx_time;
2858
2859 u32 wl_only: 1;
2860 u32 wl_fw_cx_offload: 1;
2861 u32 freerun: 1;
2862 u32 fddt_train: 1;
2863 u32 wl_ps_ctrl: 2;
2864 u32 wl_mimo_ps: 1;
2865 u32 leak_ap: 1;
2866 u32 noisy_level: 3;
2867 u32 coex_info_map: 8;
2868 u32 bt_only: 1;
2869 u32 wl_btg_rx: 2;
2870 u32 trx_para_level: 8;
2871 u32 wl_stb_chg: 1;
2872 u32 pta_owner: 1;
2873
2874 u32 tdma_instant_excute: 1;
2875 u32 wl_btg_rx_rb: 2;
2876
2877 u16 slot_dur[CXST_MAX];
2878 u16 bt_slot_flood;
2879
2880 u8 run_reason;
2881 u8 run_action;
2882
2883 u8 wl_pre_agc: 2;
2884 u8 wl_lna2: 1;
2885 u8 wl_pre_agc_rb: 2;
2886 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
2887 u8 slot_req_more: 1;
2888 };
2889
2890 struct rtw89_btc_ctrl {
2891 u32 manual: 1;
2892 u32 igno_bt: 1;
2893 u32 always_freerun: 1;
2894 u32 trace_step: 16;
2895 u32 rsvd: 12;
2896 };
2897
2898 struct rtw89_btc_ctrl_v7 {
2899 u8 manual;
2900 u8 igno_bt;
2901 u8 always_freerun;
2902 u8 rsvd;
2903 } __packed;
2904
2905 union rtw89_btc_ctrl_list {
2906 struct rtw89_btc_ctrl ctrl;
2907 struct rtw89_btc_ctrl_v7 ctrl_v7;
2908 };
2909
2910 struct rtw89_btc_dbg {
2911 /* cmd "rb" */
2912 bool rb_done;
2913 u32 rb_val;
2914 };
2915
2916 enum rtw89_btc_btf_fw_event {
2917 BTF_EVNT_RPT = 0,
2918 BTF_EVNT_BT_INFO = 1,
2919 BTF_EVNT_BT_SCBD = 2,
2920 BTF_EVNT_BT_REG = 3,
2921 BTF_EVNT_CX_RUNINFO = 4,
2922 BTF_EVNT_BT_PSD = 5,
2923 BTF_EVNT_BUF_OVERFLOW,
2924 BTF_EVNT_C2H_LOOPBACK,
2925 BTF_EVNT_MAX,
2926 };
2927
2928 enum btf_fw_event_report {
2929 BTC_RPT_TYPE_CTRL = 0x0,
2930 BTC_RPT_TYPE_TDMA,
2931 BTC_RPT_TYPE_SLOT,
2932 BTC_RPT_TYPE_CYSTA,
2933 BTC_RPT_TYPE_STEP,
2934 BTC_RPT_TYPE_NULLSTA,
2935 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
2936 BTC_RPT_TYPE_MREG,
2937 BTC_RPT_TYPE_GPIO_DBG,
2938 BTC_RPT_TYPE_BT_VER,
2939 BTC_RPT_TYPE_BT_SCAN,
2940 BTC_RPT_TYPE_BT_AFH,
2941 BTC_RPT_TYPE_BT_DEVICE,
2942 BTC_RPT_TYPE_TEST,
2943 BTC_RPT_TYPE_MAX = 31,
2944
2945 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
2946 __BTC_RPT_TYPE_V0_MAX = 12,
2947 };
2948
2949 enum rtw_btc_btf_reg_type {
2950 REG_MAC = 0x0,
2951 REG_BB = 0x1,
2952 REG_RF = 0x2,
2953 REG_BT_RF = 0x3,
2954 REG_BT_MODEM = 0x4,
2955 REG_BT_BLUEWIZE = 0x5,
2956 REG_BT_VENDOR = 0x6,
2957 REG_BT_LE = 0x7,
2958 REG_MAX_TYPE,
2959 };
2960
2961 struct rtw89_btc_rpt_cmn_info {
2962 u32 rx_cnt;
2963 u32 rx_len;
2964 u32 req_len; /* expected rsp len */
2965 u8 req_fver; /* expected rsp fver */
2966 u8 rsp_fver; /* fver from fw */
2967 u8 valid;
2968 } __packed;
2969
2970 union rtw89_btc_fbtc_btafh_info {
2971 struct rtw89_btc_fbtc_btafh v1;
2972 struct rtw89_btc_fbtc_btafh_v2 v2;
2973 };
2974
2975 struct rtw89_btc_report_ctrl_state {
2976 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2977 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
2978 };
2979
2980 struct rtw89_btc_rpt_fbtc_tdma {
2981 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2982 union rtw89_btc_fbtc_tdma_le32 finfo;
2983 };
2984
2985 struct rtw89_btc_rpt_fbtc_slots {
2986 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2987 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
2988 };
2989
2990 struct rtw89_btc_rpt_fbtc_cysta {
2991 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2992 union rtw89_btc_fbtc_cysta_info finfo;
2993 };
2994
2995 struct rtw89_btc_rpt_fbtc_step {
2996 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2997 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
2998 };
2999
3000 struct rtw89_btc_rpt_fbtc_nullsta {
3001 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3002 union rtw89_btc_fbtc_cynullsta_info finfo;
3003 };
3004
3005 struct rtw89_btc_rpt_fbtc_mreg {
3006 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3007 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3008 };
3009
3010 struct rtw89_btc_rpt_fbtc_gpio_dbg {
3011 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3012 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3013 };
3014
3015 struct rtw89_btc_rpt_fbtc_btver {
3016 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3017 union rtw89_btc_fbtc_btver finfo; /* info from fw */
3018 };
3019
3020 struct rtw89_btc_rpt_fbtc_btscan {
3021 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3022 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3023 };
3024
3025 struct rtw89_btc_rpt_fbtc_btafh {
3026 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3027 union rtw89_btc_fbtc_btafh_info finfo;
3028 };
3029
3030 struct rtw89_btc_rpt_fbtc_btdev {
3031 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3032 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3033 };
3034
3035 enum rtw89_btc_btfre_type {
3036 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3037 BTFRE_UNDEF_TYPE,
3038 BTFRE_EXCEPTION,
3039 BTFRE_MAX,
3040 };
3041
3042 struct rtw89_btc_btf_fwinfo {
3043 u32 cnt_c2h;
3044 u32 cnt_h2c;
3045 u32 cnt_h2c_fail;
3046 u32 event[BTF_EVNT_MAX];
3047
3048 u32 err[BTFRE_MAX];
3049 u32 len_mismch;
3050 u32 fver_mismch;
3051 u32 rpt_en_map;
3052
3053 struct rtw89_btc_report_ctrl_state rpt_ctrl;
3054 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3055 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3056 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3057 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3058 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3059 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3060 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3061 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3062 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3063 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3064 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3065 };
3066
3067 struct rtw89_btc_ver {
3068 enum rtw89_core_chip_id chip_id;
3069 u32 fw_ver_code;
3070
3071 u8 fcxbtcrpt;
3072 u8 fcxtdma;
3073 u8 fcxslots;
3074 u8 fcxcysta;
3075 u8 fcxstep;
3076 u8 fcxnullsta;
3077 u8 fcxmreg;
3078 u8 fcxgpiodbg;
3079 u8 fcxbtver;
3080 u8 fcxbtscan;
3081 u8 fcxbtafh;
3082 u8 fcxbtdevinfo;
3083 u8 fwlrole;
3084 u8 frptmap;
3085 u8 fcxctrl;
3086 u8 fcxinit;
3087
3088 u8 fwevntrptl;
3089 u8 drvinfo_type;
3090 u16 info_buf;
3091 u8 max_role_num;
3092 };
3093
3094 #define RTW89_BTC_POLICY_MAXLEN 512
3095
3096 struct rtw89_btc {
3097 const struct rtw89_btc_ver *ver;
3098
3099 struct rtw89_btc_cx cx;
3100 struct rtw89_btc_dm dm;
3101 union rtw89_btc_ctrl_list ctrl;
3102 union rtw89_btc_module_info mdinfo;
3103 struct rtw89_btc_btf_fwinfo fwinfo;
3104 struct rtw89_btc_dbg dbg;
3105
3106 struct work_struct eapol_notify_work;
3107 struct work_struct arp_notify_work;
3108 struct work_struct dhcp_notify_work;
3109 struct work_struct icmp_notify_work;
3110
3111 u32 bt_req_len;
3112
3113 u8 policy[RTW89_BTC_POLICY_MAXLEN];
3114 u8 ant_type;
3115 u8 btg_pos;
3116 u16 policy_len;
3117 u16 policy_type;
3118 u32 hubmsg_cnt;
3119 bool bt_req_en;
3120 bool update_policy_force;
3121 bool lps;
3122 bool manual_ctrl;
3123 };
3124
3125 enum rtw89_btc_hmsg {
3126 RTW89_BTC_HMSG_TMR_EN = 0x0,
3127 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3128 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3129 RTW89_BTC_HMSG_FW_EV = 0x3,
3130 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3131 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3132
3133 NUM_OF_RTW89_BTC_HMSG,
3134 };
3135
3136 enum rtw89_ra_mode {
3137 RTW89_RA_MODE_CCK = BIT(0),
3138 RTW89_RA_MODE_OFDM = BIT(1),
3139 RTW89_RA_MODE_HT = BIT(2),
3140 RTW89_RA_MODE_VHT = BIT(3),
3141 RTW89_RA_MODE_HE = BIT(4),
3142 RTW89_RA_MODE_EHT = BIT(5),
3143 };
3144
3145 enum rtw89_ra_report_mode {
3146 RTW89_RA_RPT_MODE_LEGACY,
3147 RTW89_RA_RPT_MODE_HT,
3148 RTW89_RA_RPT_MODE_VHT,
3149 RTW89_RA_RPT_MODE_HE,
3150 RTW89_RA_RPT_MODE_EHT,
3151 };
3152
3153 enum rtw89_dig_noisy_level {
3154 RTW89_DIG_NOISY_LEVEL0 = -1,
3155 RTW89_DIG_NOISY_LEVEL1 = 0,
3156 RTW89_DIG_NOISY_LEVEL2 = 1,
3157 RTW89_DIG_NOISY_LEVEL3 = 2,
3158 RTW89_DIG_NOISY_LEVEL_MAX = 3,
3159 };
3160
3161 enum rtw89_gi_ltf {
3162 RTW89_GILTF_LGI_4XHE32 = 0,
3163 RTW89_GILTF_SGI_4XHE08 = 1,
3164 RTW89_GILTF_2XHE16 = 2,
3165 RTW89_GILTF_2XHE08 = 3,
3166 RTW89_GILTF_1XHE16 = 4,
3167 RTW89_GILTF_1XHE08 = 5,
3168 RTW89_GILTF_MAX
3169 };
3170
3171 enum rtw89_rx_frame_type {
3172 RTW89_RX_TYPE_MGNT = 0,
3173 RTW89_RX_TYPE_CTRL = 1,
3174 RTW89_RX_TYPE_DATA = 2,
3175 RTW89_RX_TYPE_RSVD = 3,
3176 };
3177
3178 enum rtw89_efuse_block {
3179 RTW89_EFUSE_BLOCK_SYS = 0,
3180 RTW89_EFUSE_BLOCK_RF = 1,
3181 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3182 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3183 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3184 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3185 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3186 RTW89_EFUSE_BLOCK_ADIE = 7,
3187
3188 RTW89_EFUSE_BLOCK_NUM,
3189 RTW89_EFUSE_BLOCK_IGNORE,
3190 };
3191
3192 struct rtw89_ra_info {
3193 u8 is_dis_ra:1;
3194 /* Bit0 : CCK
3195 * Bit1 : OFDM
3196 * Bit2 : HT
3197 * Bit3 : VHT
3198 * Bit4 : HE
3199 * Bit5 : EHT
3200 */
3201 u8 mode_ctrl:6;
3202 u8 bw_cap:3; /* enum rtw89_bandwidth */
3203 u8 macid;
3204 u8 dcm_cap:1;
3205 u8 er_cap:1;
3206 u8 init_rate_lv:2;
3207 u8 upd_all:1;
3208 u8 en_sgi:1;
3209 u8 ldpc_cap:1;
3210 u8 stbc_cap:1;
3211 u8 ss_num:3;
3212 u8 giltf:3;
3213 u8 upd_bw_nss_mask:1;
3214 u8 upd_mask:1;
3215 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3216 /* BFee CSI */
3217 u8 band_num;
3218 u8 ra_csi_rate_en:1;
3219 u8 fixed_csi_rate_en:1;
3220 u8 cr_tbl_sel:1;
3221 u8 fix_giltf_en:1;
3222 u8 fix_giltf:3;
3223 u8 rsvd2:1;
3224 u8 csi_mcs_ss_idx;
3225 u8 csi_mode:2;
3226 u8 csi_gi_ltf:3;
3227 u8 csi_bw:3;
3228 };
3229
3230 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3231 #define RTW89_PPDU_MAC_INFO_SIZE 8
3232 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3233 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3234
3235 #define RTW89_MAX_RX_AGG_NUM 64
3236 #define RTW89_MAX_TX_AGG_NUM 128
3237
3238 struct rtw89_ampdu_params {
3239 u16 agg_num;
3240 bool amsdu;
3241 };
3242
3243 struct rtw89_ra_report {
3244 struct rate_info txrate;
3245 u32 bit_rate;
3246 u16 hw_rate;
3247 bool might_fallback_legacy;
3248 };
3249
3250 DECLARE_EWMA(rssi, 10, 16);
3251 DECLARE_EWMA(evm, 10, 16);
3252 DECLARE_EWMA(snr, 10, 16);
3253
3254 struct rtw89_ba_cam_entry {
3255 struct list_head list;
3256 u8 tid;
3257 };
3258
3259 #define RTW89_MAX_ADDR_CAM_NUM 128
3260 #define RTW89_MAX_BSSID_CAM_NUM 20
3261 #define RTW89_MAX_SEC_CAM_NUM 128
3262 #define RTW89_MAX_BA_CAM_NUM 24
3263 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
3264
3265 struct rtw89_addr_cam_entry {
3266 u8 addr_cam_idx;
3267 u8 offset;
3268 u8 len;
3269 u8 valid : 1;
3270 u8 addr_mask : 6;
3271 u8 wapi : 1;
3272 u8 mask_sel : 2;
3273 u8 bssid_cam_idx: 6;
3274
3275 u8 sec_ent_mode;
3276 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3277 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3278 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3279 };
3280
3281 struct rtw89_bssid_cam_entry {
3282 u8 bssid[ETH_ALEN];
3283 u8 phy_idx;
3284 u8 bssid_cam_idx;
3285 u8 offset;
3286 u8 len;
3287 u8 valid : 1;
3288 u8 num;
3289 };
3290
3291 struct rtw89_sec_cam_entry {
3292 u8 sec_cam_idx;
3293 u8 offset;
3294 u8 len;
3295 u8 type : 4;
3296 u8 ext_key : 1;
3297 u8 spp_mode : 1;
3298 /* 256 bits */
3299 u8 key[32];
3300 };
3301
3302 struct rtw89_sta {
3303 u8 mac_id;
3304 bool disassoc;
3305 bool er_cap;
3306 struct rtw89_dev *rtwdev;
3307 struct rtw89_vif *rtwvif;
3308 struct rtw89_ra_info ra;
3309 struct rtw89_ra_report ra_report;
3310 int max_agg_wait;
3311 u8 prev_rssi;
3312 struct ewma_rssi avg_rssi;
3313 struct ewma_rssi rssi[RF_PATH_MAX];
3314 struct ewma_snr avg_snr;
3315 struct ewma_evm evm_min[RF_PATH_MAX];
3316 struct ewma_evm evm_max[RF_PATH_MAX];
3317 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
3318 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
3319 struct ieee80211_rx_status rx_status;
3320 u16 rx_hw_rate;
3321 __le32 htc_template;
3322 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3323 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3324 struct list_head ba_cam_list;
3325 struct sk_buff_head roc_queue;
3326
3327 bool use_cfg_mask;
3328 struct cfg80211_bitrate_mask mask;
3329
3330 bool cctl_tx_time;
3331 u32 ampdu_max_time:4;
3332 bool cctl_tx_retry_limit;
3333 u32 data_tx_cnt_lmt:6;
3334 };
3335
3336 struct rtw89_efuse {
3337 bool valid;
3338 bool power_k_valid;
3339 u8 xtal_cap;
3340 u8 addr[ETH_ALEN];
3341 u8 rfe_type;
3342 char country_code[2];
3343 };
3344
3345 struct rtw89_phy_rate_pattern {
3346 u64 ra_mask;
3347 u16 rate;
3348 u8 ra_mode;
3349 bool enable;
3350 };
3351
3352 struct rtw89_tx_wait_info {
3353 struct rcu_head rcu_head;
3354 struct completion completion;
3355 bool tx_done;
3356 };
3357
3358 struct rtw89_tx_skb_data {
3359 struct rtw89_tx_wait_info __rcu *wait;
3360 u8 hci_priv[];
3361 };
3362
3363 #define RTW89_ROC_IDLE_TIMEOUT 500
3364 #define RTW89_ROC_TX_TIMEOUT 30
3365 enum rtw89_roc_state {
3366 RTW89_ROC_IDLE,
3367 RTW89_ROC_NORMAL,
3368 RTW89_ROC_MGMT,
3369 };
3370
3371 struct rtw89_roc {
3372 struct ieee80211_channel chan;
3373 struct delayed_work roc_work;
3374 enum ieee80211_roc_type type;
3375 enum rtw89_roc_state state;
3376 int duration;
3377 };
3378
3379 #define RTW89_P2P_MAX_NOA_NUM 2
3380
3381 struct rtw89_p2p_ie_head {
3382 u8 eid;
3383 u8 ie_len;
3384 u8 oui[3];
3385 u8 oui_type;
3386 } __packed;
3387
3388 struct rtw89_noa_attr_head {
3389 u8 attr_type;
3390 __le16 attr_len;
3391 u8 index;
3392 u8 oppps_ctwindow;
3393 } __packed;
3394
3395 struct rtw89_p2p_noa_ie {
3396 struct rtw89_p2p_ie_head p2p_head;
3397 struct rtw89_noa_attr_head noa_head;
3398 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3399 } __packed;
3400
3401 struct rtw89_p2p_noa_setter {
3402 struct rtw89_p2p_noa_ie ie;
3403 u8 noa_count;
3404 u8 noa_index;
3405 };
3406
3407 struct rtw89_vif {
3408 struct list_head list;
3409 struct rtw89_dev *rtwdev;
3410 struct rtw89_roc roc;
3411 bool chanctx_assigned; /* only valid when running with chanctx_ops */
3412 enum rtw89_sub_entity_idx sub_entity_idx;
3413 enum rtw89_reg_6ghz_power reg_6ghz_power;
3414 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3415
3416 u8 mac_id;
3417 u8 port;
3418 u8 mac_addr[ETH_ALEN];
3419 u8 bssid[ETH_ALEN];
3420 __be32 ip_addr;
3421 u8 phy_idx;
3422 u8 mac_idx;
3423 u8 net_type;
3424 u8 wifi_role;
3425 u8 self_role;
3426 u8 wmm;
3427 u8 bcn_hit_cond;
3428 u8 hit_rule;
3429 u8 last_noa_nr;
3430 u64 sync_bcn_tsf;
3431 bool offchan;
3432 bool trigger;
3433 bool lsig_txop;
3434 u8 tgt_ind;
3435 u8 frm_tgt_ind;
3436 bool wowlan_pattern;
3437 bool wowlan_uc;
3438 bool wowlan_magic;
3439 bool is_hesta;
3440 bool last_a_ctrl;
3441 bool dyn_tb_bedge_en;
3442 bool pre_pwr_diff_en;
3443 bool pwr_diff_en;
3444 u8 def_tri_idx;
3445 u32 tdls_peer;
3446 struct work_struct update_beacon_work;
3447 struct rtw89_addr_cam_entry addr_cam;
3448 struct rtw89_bssid_cam_entry bssid_cam;
3449 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3450 struct rtw89_traffic_stats stats;
3451 struct rtw89_phy_rate_pattern rate_pattern;
3452 struct cfg80211_scan_request *scan_req;
3453 struct ieee80211_scan_ies *scan_ies;
3454 struct list_head general_pkt_list;
3455 struct rtw89_p2p_noa_setter p2p_noa;
3456 };
3457
3458 enum rtw89_lv1_rcvy_step {
3459 RTW89_LV1_RCVY_STEP_1,
3460 RTW89_LV1_RCVY_STEP_2,
3461 };
3462
3463 struct rtw89_hci_ops {
3464 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3465 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3466 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3467 void (*reset)(struct rtw89_dev *rtwdev);
3468 int (*start)(struct rtw89_dev *rtwdev);
3469 void (*stop)(struct rtw89_dev *rtwdev);
3470 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3471 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3472 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3473
3474 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3475 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3476 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3477 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3478 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3479 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3480
3481 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3482 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3483 int (*mac_post_init)(struct rtw89_dev *rtwdev);
3484 int (*deinit)(struct rtw89_dev *rtwdev);
3485
3486 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3487 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3488 void (*dump_err_status)(struct rtw89_dev *rtwdev);
3489 int (*napi_poll)(struct napi_struct *napi, int budget);
3490
3491 /* Deal with locks inside recovery_start and recovery_complete callbacks
3492 * by hci instance, and handle things which need to consider under SER.
3493 * e.g. turn on/off interrupts except for the one for halt notification.
3494 */
3495 void (*recovery_start)(struct rtw89_dev *rtwdev);
3496 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3497
3498 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3499 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3500 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3501 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3502 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3503 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3504 void (*disable_intr)(struct rtw89_dev *rtwdev);
3505 void (*enable_intr)(struct rtw89_dev *rtwdev);
3506 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3507 };
3508
3509 struct rtw89_hci_info {
3510 const struct rtw89_hci_ops *ops;
3511 enum rtw89_hci_type type;
3512 u32 rpwm_addr;
3513 u32 cpwm_addr;
3514 bool paused;
3515 };
3516
3517 struct rtw89_chip_ops {
3518 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3519 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3520 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3521 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3522 void (*bb_reset)(struct rtw89_dev *rtwdev,
3523 enum rtw89_phy_idx phy_idx);
3524 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3525 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3526 u32 addr, u32 mask);
3527 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3528 u32 addr, u32 mask, u32 data);
3529 void (*set_channel)(struct rtw89_dev *rtwdev,
3530 const struct rtw89_chan *chan,
3531 enum rtw89_mac_idx mac_idx,
3532 enum rtw89_phy_idx phy_idx);
3533 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3534 struct rtw89_channel_help_params *p,
3535 const struct rtw89_chan *chan,
3536 enum rtw89_mac_idx mac_idx,
3537 enum rtw89_phy_idx phy_idx);
3538 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3539 enum rtw89_efuse_block block);
3540 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3541 void (*fem_setup)(struct rtw89_dev *rtwdev);
3542 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3543 void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3544 void (*rfk_init)(struct rtw89_dev *rtwdev);
3545 void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3546 void (*rfk_channel)(struct rtw89_dev *rtwdev);
3547 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3548 enum rtw89_phy_idx phy_idx);
3549 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
3550 void (*rfk_track)(struct rtw89_dev *rtwdev);
3551 void (*power_trim)(struct rtw89_dev *rtwdev);
3552 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3553 const struct rtw89_chan *chan,
3554 enum rtw89_phy_idx phy_idx);
3555 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3556 enum rtw89_phy_idx phy_idx);
3557 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3558 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3559 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3560 enum rtw89_phy_idx phy_idx);
3561 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3562 struct rtw89_rx_phy_ppdu *phy_ppdu,
3563 struct ieee80211_rx_status *status);
3564 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3565 enum rtw89_phy_idx phy_idx);
3566 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3567 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3568 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3569 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3570 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3571 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3572 struct rtw89_rx_desc_info *desc_info,
3573 u8 *data, u32 data_offset);
3574 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3575 struct rtw89_tx_desc_info *desc_info,
3576 void *txdesc);
3577 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3578 struct rtw89_tx_desc_info *desc_info,
3579 void *txdesc);
3580 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3581 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3582 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3583 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3584 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3585 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3586 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3587 struct rtw89_vif *rtwvif,
3588 struct rtw89_sta *rtwsta);
3589 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3590 struct rtw89_vif *rtwvif,
3591 struct rtw89_sta *rtwsta);
3592 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3593 struct ieee80211_vif *vif,
3594 struct ieee80211_sta *sta);
3595 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3596 struct ieee80211_vif *vif,
3597 struct ieee80211_sta *sta);
3598 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3599 struct rtw89_vif *rtwvif,
3600 struct rtw89_sta *rtwsta);
3601 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3602 struct rtw89_vif *rtwvif);
3603 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3604 bool valid, struct ieee80211_ampdu_params *params);
3605
3606 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3607 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3608 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3609 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3610 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3611 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3612 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3613 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3614 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3615 };
3616
3617 enum rtw89_dma_ch {
3618 RTW89_DMA_ACH0 = 0,
3619 RTW89_DMA_ACH1 = 1,
3620 RTW89_DMA_ACH2 = 2,
3621 RTW89_DMA_ACH3 = 3,
3622 RTW89_DMA_ACH4 = 4,
3623 RTW89_DMA_ACH5 = 5,
3624 RTW89_DMA_ACH6 = 6,
3625 RTW89_DMA_ACH7 = 7,
3626 RTW89_DMA_B0MG = 8,
3627 RTW89_DMA_B0HI = 9,
3628 RTW89_DMA_B1MG = 10,
3629 RTW89_DMA_B1HI = 11,
3630 RTW89_DMA_H2C = 12,
3631 RTW89_DMA_CH_NUM = 13
3632 };
3633
3634 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3635
3636 enum rtw89_mlo_dbcc_mode {
3637 MLO_DBCC_NOT_SUPPORT = 1,
3638 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3639 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3640 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3641 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3642 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3643 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3644 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3645 DBCC_LEGACY = 0xffffffff,
3646 };
3647
3648 enum rtw89_scan_be_operation {
3649 RTW89_SCAN_OP_STOP,
3650 RTW89_SCAN_OP_START,
3651 RTW89_SCAN_OP_SETPARM,
3652 RTW89_SCAN_OP_GETRPT,
3653 RTW89_SCAN_OP_NUM
3654 };
3655
3656 enum rtw89_scan_be_mode {
3657 RTW89_SCAN_MODE_SA,
3658 RTW89_SCAN_MODE_MACC,
3659 RTW89_SCAN_MODE_NUM
3660 };
3661
3662 enum rtw89_scan_be_opmode {
3663 RTW89_SCAN_OPMODE_NONE,
3664 RTW89_SCAN_OPMODE_TBTT,
3665 RTW89_SCAN_OPMODE_INTV,
3666 RTW89_SCAN_OPMODE_CNT,
3667 RTW89_SCAN_OPMODE_NUM,
3668 };
3669
3670 struct rtw89_scan_option {
3671 bool enable;
3672 bool target_ch_mode;
3673 u8 num_macc_role;
3674 u8 num_opch;
3675 u8 repeat;
3676 u16 norm_pd;
3677 u16 slow_pd;
3678 u16 norm_cy;
3679 u8 opch_end;
3680 u64 prohib_chan;
3681 enum rtw89_phy_idx band;
3682 enum rtw89_scan_be_operation operation;
3683 enum rtw89_scan_be_mode scan_mode;
3684 enum rtw89_mlo_dbcc_mode mlo_mode;
3685 };
3686
3687 enum rtw89_qta_mode {
3688 RTW89_QTA_SCC,
3689 RTW89_QTA_DBCC,
3690 RTW89_QTA_DLFW,
3691 RTW89_QTA_WOW,
3692
3693 /* keep last */
3694 RTW89_QTA_INVALID,
3695 };
3696
3697 struct rtw89_hfc_ch_cfg {
3698 u16 min;
3699 u16 max;
3700 #define grp_0 0
3701 #define grp_1 1
3702 #define grp_num 2
3703 u8 grp;
3704 };
3705
3706 struct rtw89_hfc_ch_info {
3707 u16 aval;
3708 u16 used;
3709 };
3710
3711 struct rtw89_hfc_pub_cfg {
3712 u16 grp0;
3713 u16 grp1;
3714 u16 pub_max;
3715 u16 wp_thrd;
3716 };
3717
3718 struct rtw89_hfc_pub_info {
3719 u16 g0_used;
3720 u16 g1_used;
3721 u16 g0_aval;
3722 u16 g1_aval;
3723 u16 pub_aval;
3724 u16 wp_aval;
3725 };
3726
3727 struct rtw89_hfc_prec_cfg {
3728 u16 ch011_prec;
3729 u16 h2c_prec;
3730 u16 wp_ch07_prec;
3731 u16 wp_ch811_prec;
3732 u8 ch011_full_cond;
3733 u8 h2c_full_cond;
3734 u8 wp_ch07_full_cond;
3735 u8 wp_ch811_full_cond;
3736 };
3737
3738 struct rtw89_hfc_param {
3739 bool en;
3740 bool h2c_en;
3741 u8 mode;
3742 const struct rtw89_hfc_ch_cfg *ch_cfg;
3743 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3744 struct rtw89_hfc_pub_cfg pub_cfg;
3745 struct rtw89_hfc_pub_info pub_info;
3746 struct rtw89_hfc_prec_cfg prec_cfg;
3747 };
3748
3749 struct rtw89_hfc_param_ini {
3750 const struct rtw89_hfc_ch_cfg *ch_cfg;
3751 const struct rtw89_hfc_pub_cfg *pub_cfg;
3752 const struct rtw89_hfc_prec_cfg *prec_cfg;
3753 u8 mode;
3754 };
3755
3756 struct rtw89_dle_size {
3757 u16 pge_size;
3758 u16 lnk_pge_num;
3759 u16 unlnk_pge_num;
3760 /* for WiFi 7 chips below */
3761 u32 srt_ofst;
3762 };
3763
3764 struct rtw89_wde_quota {
3765 u16 hif;
3766 u16 wcpu;
3767 u16 pkt_in;
3768 u16 cpu_io;
3769 };
3770
3771 struct rtw89_ple_quota {
3772 u16 cma0_tx;
3773 u16 cma1_tx;
3774 u16 c2h;
3775 u16 h2c;
3776 u16 wcpu;
3777 u16 mpdu_proc;
3778 u16 cma0_dma;
3779 u16 cma1_dma;
3780 u16 bb_rpt;
3781 u16 wd_rel;
3782 u16 cpu_io;
3783 u16 tx_rpt;
3784 /* for WiFi 7 chips below */
3785 u16 h2d;
3786 };
3787
3788 struct rtw89_rsvd_quota {
3789 u16 mpdu_info_tbl;
3790 u16 b0_csi;
3791 u16 b1_csi;
3792 u16 b0_lmr;
3793 u16 b1_lmr;
3794 u16 b0_ftm;
3795 u16 b1_ftm;
3796 u16 b0_smr;
3797 u16 b1_smr;
3798 u16 others;
3799 };
3800
3801 struct rtw89_dle_rsvd_size {
3802 u32 srt_ofst;
3803 u32 size;
3804 };
3805
3806 struct rtw89_dle_mem {
3807 enum rtw89_qta_mode mode;
3808 const struct rtw89_dle_size *wde_size;
3809 const struct rtw89_dle_size *ple_size;
3810 const struct rtw89_wde_quota *wde_min_qt;
3811 const struct rtw89_wde_quota *wde_max_qt;
3812 const struct rtw89_ple_quota *ple_min_qt;
3813 const struct rtw89_ple_quota *ple_max_qt;
3814 /* for WiFi 7 chips below */
3815 const struct rtw89_rsvd_quota *rsvd_qt;
3816 const struct rtw89_dle_rsvd_size *rsvd0_size;
3817 const struct rtw89_dle_rsvd_size *rsvd1_size;
3818 };
3819
3820 struct rtw89_reg_def {
3821 u32 addr;
3822 u32 mask;
3823 };
3824
3825 struct rtw89_reg2_def {
3826 u32 addr;
3827 u32 data;
3828 };
3829
3830 struct rtw89_reg3_def {
3831 u32 addr;
3832 u32 mask;
3833 u32 data;
3834 };
3835
3836 struct rtw89_reg5_def {
3837 u8 flag; /* recognized by parsers */
3838 u8 path;
3839 u32 addr;
3840 u32 mask;
3841 u32 data;
3842 };
3843
3844 struct rtw89_reg_imr {
3845 u32 addr;
3846 u32 clr;
3847 u32 set;
3848 };
3849
3850 struct rtw89_phy_table {
3851 const struct rtw89_reg2_def *regs;
3852 u32 n_regs;
3853 enum rtw89_rf_path rf_path;
3854 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3855 enum rtw89_rf_path rf_path, void *data);
3856 };
3857
3858 struct rtw89_txpwr_table {
3859 const void *data;
3860 u32 size;
3861 void (*load)(struct rtw89_dev *rtwdev,
3862 const struct rtw89_txpwr_table *tbl);
3863 };
3864
3865 struct rtw89_txpwr_rule_2ghz {
3866 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3867 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3868 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3869 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3870 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3871 };
3872
3873 struct rtw89_txpwr_rule_5ghz {
3874 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3875 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3876 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3877 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3878 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3879 };
3880
3881 struct rtw89_txpwr_rule_6ghz {
3882 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3883 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3884 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3885 [RTW89_6G_CH_NUM];
3886 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3887 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3888 [RTW89_6G_CH_NUM];
3889 };
3890
3891 struct rtw89_tx_shape {
3892 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3893 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
3894 };
3895
3896 struct rtw89_rfe_parms {
3897 const struct rtw89_txpwr_table *byr_tbl;
3898 struct rtw89_txpwr_rule_2ghz rule_2ghz;
3899 struct rtw89_txpwr_rule_5ghz rule_5ghz;
3900 struct rtw89_txpwr_rule_6ghz rule_6ghz;
3901 struct rtw89_tx_shape tx_shape;
3902 };
3903
3904 struct rtw89_rfe_parms_conf {
3905 const struct rtw89_rfe_parms *rfe_parms;
3906 u8 rfe_type;
3907 };
3908
3909 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
3910
3911 struct rtw89_txpwr_conf {
3912 u8 rfe_type;
3913 u8 ent_sz;
3914 u32 num_ents;
3915 const void *data;
3916 };
3917
3918 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
3919
3920 #if defined(__linux__)
3921 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
3922 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \
3923 memcpy(&(entry), cursor, \
3924 min_t(u8, sizeof(entry), (conf)->ent_sz)); \
3925 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
3926 (cursor) += (conf)->ent_sz, \
3927 memcpy(&(entry), cursor, \
3928 min_t(u8, sizeof(entry), (conf)->ent_sz)))
3929 #elif defined(__FreeBSD__)
3930 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
3931 for (typecheck(const u8 *, cursor), (cursor) = (conf)->data, \
3932 memcpy(&(entry), cursor, \
3933 min_t(u8, sizeof(entry), (conf)->ent_sz)); \
3934 (cursor) < (const u8 *)(conf)->data + (conf)->num_ents * (conf)->ent_sz; \
3935 (cursor) += (conf)->ent_sz, \
3936 memcpy(&(entry), cursor, \
3937 min_t(u8, sizeof(entry), (conf)->ent_sz)))
3938 #endif
3939
3940 struct rtw89_txpwr_byrate_data {
3941 struct rtw89_txpwr_conf conf;
3942 struct rtw89_txpwr_table tbl;
3943 };
3944
3945 struct rtw89_txpwr_lmt_2ghz_data {
3946 struct rtw89_txpwr_conf conf;
3947 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3948 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3949 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3950 };
3951
3952 struct rtw89_txpwr_lmt_5ghz_data {
3953 struct rtw89_txpwr_conf conf;
3954 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3955 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3956 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3957 };
3958
3959 struct rtw89_txpwr_lmt_6ghz_data {
3960 struct rtw89_txpwr_conf conf;
3961 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3962 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3963 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3964 [RTW89_6G_CH_NUM];
3965 };
3966
3967 struct rtw89_txpwr_lmt_ru_2ghz_data {
3968 struct rtw89_txpwr_conf conf;
3969 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3970 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3971 };
3972
3973 struct rtw89_txpwr_lmt_ru_5ghz_data {
3974 struct rtw89_txpwr_conf conf;
3975 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3976 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3977 };
3978
3979 struct rtw89_txpwr_lmt_ru_6ghz_data {
3980 struct rtw89_txpwr_conf conf;
3981 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3982 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3983 [RTW89_6G_CH_NUM];
3984 };
3985
3986 struct rtw89_tx_shape_lmt_data {
3987 struct rtw89_txpwr_conf conf;
3988 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3989 };
3990
3991 struct rtw89_tx_shape_lmt_ru_data {
3992 struct rtw89_txpwr_conf conf;
3993 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
3994 };
3995
3996 struct rtw89_rfe_data {
3997 struct rtw89_txpwr_byrate_data byrate;
3998 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
3999 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4000 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4001 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4002 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4003 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4004 struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4005 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4006 struct rtw89_rfe_parms rfe_parms;
4007 };
4008
4009 struct rtw89_page_regs {
4010 u32 hci_fc_ctrl;
4011 u32 ch_page_ctrl;
4012 u32 ach_page_ctrl;
4013 u32 ach_page_info;
4014 u32 pub_page_info3;
4015 u32 pub_page_ctrl1;
4016 u32 pub_page_ctrl2;
4017 u32 pub_page_info1;
4018 u32 pub_page_info2;
4019 u32 wp_page_ctrl1;
4020 u32 wp_page_ctrl2;
4021 u32 wp_page_info1;
4022 };
4023
4024 struct rtw89_imr_info {
4025 u32 wdrls_imr_set;
4026 u32 wsec_imr_reg;
4027 u32 wsec_imr_set;
4028 u32 mpdu_tx_imr_set;
4029 u32 mpdu_rx_imr_set;
4030 u32 sta_sch_imr_set;
4031 u32 txpktctl_imr_b0_reg;
4032 u32 txpktctl_imr_b0_clr;
4033 u32 txpktctl_imr_b0_set;
4034 u32 txpktctl_imr_b1_reg;
4035 u32 txpktctl_imr_b1_clr;
4036 u32 txpktctl_imr_b1_set;
4037 u32 wde_imr_clr;
4038 u32 wde_imr_set;
4039 u32 ple_imr_clr;
4040 u32 ple_imr_set;
4041 u32 host_disp_imr_clr;
4042 u32 host_disp_imr_set;
4043 u32 cpu_disp_imr_clr;
4044 u32 cpu_disp_imr_set;
4045 u32 other_disp_imr_clr;
4046 u32 other_disp_imr_set;
4047 u32 bbrpt_com_err_imr_reg;
4048 u32 bbrpt_chinfo_err_imr_reg;
4049 u32 bbrpt_err_imr_set;
4050 u32 bbrpt_dfs_err_imr_reg;
4051 u32 ptcl_imr_clr;
4052 u32 ptcl_imr_set;
4053 u32 cdma_imr_0_reg;
4054 u32 cdma_imr_0_clr;
4055 u32 cdma_imr_0_set;
4056 u32 cdma_imr_1_reg;
4057 u32 cdma_imr_1_clr;
4058 u32 cdma_imr_1_set;
4059 u32 phy_intf_imr_reg;
4060 u32 phy_intf_imr_clr;
4061 u32 phy_intf_imr_set;
4062 u32 rmac_imr_reg;
4063 u32 rmac_imr_clr;
4064 u32 rmac_imr_set;
4065 u32 tmac_imr_reg;
4066 u32 tmac_imr_clr;
4067 u32 tmac_imr_set;
4068 };
4069
4070 struct rtw89_imr_table {
4071 const struct rtw89_reg_imr *regs;
4072 u32 n_regs;
4073 };
4074
4075 struct rtw89_xtal_info {
4076 u32 xcap_reg;
4077 u32 sc_xo_mask;
4078 u32 sc_xi_mask;
4079 };
4080
4081 struct rtw89_rrsr_cfgs {
4082 struct rtw89_reg3_def ref_rate;
4083 struct rtw89_reg3_def rsc;
4084 };
4085
4086 struct rtw89_dig_regs {
4087 u32 seg0_pd_reg;
4088 u32 pd_lower_bound_mask;
4089 u32 pd_spatial_reuse_en;
4090 u32 bmode_pd_reg;
4091 u32 bmode_cca_rssi_limit_en;
4092 u32 bmode_pd_lower_bound_reg;
4093 u32 bmode_rssi_nocca_low_th_mask;
4094 struct rtw89_reg_def p0_lna_init;
4095 struct rtw89_reg_def p1_lna_init;
4096 struct rtw89_reg_def p0_tia_init;
4097 struct rtw89_reg_def p1_tia_init;
4098 struct rtw89_reg_def p0_rxb_init;
4099 struct rtw89_reg_def p1_rxb_init;
4100 struct rtw89_reg_def p0_p20_pagcugc_en;
4101 struct rtw89_reg_def p0_s20_pagcugc_en;
4102 struct rtw89_reg_def p1_p20_pagcugc_en;
4103 struct rtw89_reg_def p1_s20_pagcugc_en;
4104 };
4105
4106 struct rtw89_edcca_regs {
4107 u32 edcca_level;
4108 u32 edcca_mask;
4109 u32 edcca_p_mask;
4110 u32 ppdu_level;
4111 u32 ppdu_mask;
4112 u32 rpt_a;
4113 u32 rpt_b;
4114 u32 rpt_sel;
4115 u32 rpt_sel_mask;
4116 u32 rpt_sel_be;
4117 u32 rpt_sel_be_mask;
4118 u32 tx_collision_t2r_st;
4119 u32 tx_collision_t2r_st_mask;
4120 };
4121
4122 struct rtw89_phy_ul_tb_info {
4123 bool dyn_tb_tri_en;
4124 u8 def_if_bandedge;
4125 };
4126
4127 struct rtw89_antdiv_stats {
4128 struct ewma_rssi cck_rssi_avg;
4129 struct ewma_rssi ofdm_rssi_avg;
4130 struct ewma_rssi non_legacy_rssi_avg;
4131 u16 pkt_cnt_cck;
4132 u16 pkt_cnt_ofdm;
4133 u16 pkt_cnt_non_legacy;
4134 u32 evm;
4135 };
4136
4137 struct rtw89_antdiv_info {
4138 struct rtw89_antdiv_stats target_stats;
4139 struct rtw89_antdiv_stats main_stats;
4140 struct rtw89_antdiv_stats aux_stats;
4141 u8 training_count;
4142 u8 rssi_pre;
4143 bool get_stats;
4144 };
4145
4146 enum rtw89_chanctx_state {
4147 RTW89_CHANCTX_STATE_MCC_START,
4148 RTW89_CHANCTX_STATE_MCC_STOP,
4149 };
4150
4151 enum rtw89_chanctx_callbacks {
4152 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4153 RTW89_CHANCTX_CALLBACK_RFK,
4154
4155 NUM_OF_RTW89_CHANCTX_CALLBACKS,
4156 };
4157
4158 struct rtw89_chanctx_listener {
4159 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4160 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4161 };
4162
4163 struct rtw89_chip_info {
4164 enum rtw89_core_chip_id chip_id;
4165 enum rtw89_chip_gen chip_gen;
4166 const struct rtw89_chip_ops *ops;
4167 const struct rtw89_mac_gen_def *mac_def;
4168 const struct rtw89_phy_gen_def *phy_def;
4169 const char *fw_basename;
4170 u8 fw_format_max;
4171 bool try_ce_fw;
4172 u8 bbmcu_nr;
4173 u32 needed_fw_elms;
4174 u32 fifo_size;
4175 bool small_fifo_size;
4176 u32 dle_scc_rsvd_size;
4177 u16 max_amsdu_limit;
4178 bool dis_2g_40m_ul_ofdma;
4179 u32 rsvd_ple_ofst;
4180 const struct rtw89_hfc_param_ini *hfc_param_ini;
4181 const struct rtw89_dle_mem *dle_mem;
4182 u8 wde_qempty_acq_grpnum;
4183 u8 wde_qempty_mgq_grpsel;
4184 u32 rf_base_addr[2];
4185 u8 support_macid_num;
4186 u8 support_chanctx_num;
4187 u8 support_bands;
4188 u16 support_bandwidths;
4189 bool support_unii4;
4190 bool support_rnr;
4191 bool ul_tb_waveform_ctrl;
4192 bool ul_tb_pwr_diff;
4193 bool hw_sec_hdr;
4194 u8 rf_path_num;
4195 u8 tx_nss;
4196 u8 rx_nss;
4197 u8 acam_num;
4198 u8 bcam_num;
4199 u8 scam_num;
4200 u8 bacam_num;
4201 u8 bacam_dynamic_num;
4202 enum rtw89_bacam_ver bacam_ver;
4203 u8 ppdu_max_usr;
4204
4205 u8 sec_ctrl_efuse_size;
4206 u32 physical_efuse_size;
4207 u32 logical_efuse_size;
4208 u32 limit_efuse_size;
4209 u32 dav_phy_efuse_size;
4210 u32 dav_log_efuse_size;
4211 u32 phycap_addr;
4212 u32 phycap_size;
4213 const struct rtw89_efuse_block_cfg *efuse_blocks;
4214
4215 const struct rtw89_pwr_cfg * const *pwr_on_seq;
4216 const struct rtw89_pwr_cfg * const *pwr_off_seq;
4217 const struct rtw89_phy_table *bb_table;
4218 const struct rtw89_phy_table *bb_gain_table;
4219 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4220 const struct rtw89_phy_table *nctl_table;
4221 const struct rtw89_rfk_tbl *nctl_post_table;
4222 const struct rtw89_phy_dig_gain_table *dig_table;
4223 const struct rtw89_dig_regs *dig_regs;
4224 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4225
4226 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4227 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4228 const struct rtw89_rfe_parms *dflt_parms;
4229 const struct rtw89_chanctx_listener *chanctx_listener;
4230
4231 u8 txpwr_factor_rf;
4232 u8 txpwr_factor_mac;
4233
4234 u32 para_ver;
4235 u32 wlcx_desired;
4236 u8 btcx_desired;
4237 u8 scbd;
4238 u8 mailbox;
4239
4240 u8 afh_guard_ch;
4241 const u8 *wl_rssi_thres;
4242 const u8 *bt_rssi_thres;
4243 u8 rssi_tol;
4244
4245 u8 mon_reg_num;
4246 const struct rtw89_btc_fbtc_mreg *mon_reg;
4247 u8 rf_para_ulink_num;
4248 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4249 u8 rf_para_dlink_num;
4250 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4251 u8 ps_mode_supported;
4252 u8 low_power_hci_modes;
4253
4254 u32 h2c_cctl_func_id;
4255 u32 hci_func_en_addr;
4256 u32 h2c_desc_size;
4257 u32 txwd_body_size;
4258 u32 txwd_info_size;
4259 u32 h2c_ctrl_reg;
4260 const u32 *h2c_regs;
4261 struct rtw89_reg_def h2c_counter_reg;
4262 u32 c2h_ctrl_reg;
4263 const u32 *c2h_regs;
4264 struct rtw89_reg_def c2h_counter_reg;
4265 const struct rtw89_page_regs *page_regs;
4266 const u32 *wow_reason_reg;
4267 bool cfo_src_fd;
4268 bool cfo_hw_comp;
4269 const struct rtw89_reg_def *dcfo_comp;
4270 u8 dcfo_comp_sft;
4271 const struct rtw89_imr_info *imr_info;
4272 const struct rtw89_imr_table *imr_dmac_table;
4273 const struct rtw89_imr_table *imr_cmac_table;
4274 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4275 struct rtw89_reg_def bss_clr_vld;
4276 u32 bss_clr_map_reg;
4277 u32 dma_ch_mask;
4278 const struct rtw89_edcca_regs *edcca_regs;
4279 const struct wiphy_wowlan_support *wowlan_stub;
4280 const struct rtw89_xtal_info *xtal_info;
4281 };
4282
4283 union rtw89_bus_info {
4284 const struct rtw89_pci_info *pci;
4285 };
4286
4287 struct rtw89_driver_info {
4288 const struct rtw89_chip_info *chip;
4289 const struct dmi_system_id *quirks;
4290 union rtw89_bus_info bus;
4291 };
4292
4293 enum rtw89_hcifc_mode {
4294 RTW89_HCIFC_POH = 0,
4295 RTW89_HCIFC_STF = 1,
4296 RTW89_HCIFC_SDIO = 2,
4297
4298 /* keep last */
4299 RTW89_HCIFC_MODE_INVALID,
4300 };
4301
4302 struct rtw89_dle_info {
4303 const struct rtw89_rsvd_quota *rsvd_qt;
4304 enum rtw89_qta_mode qta_mode;
4305 u16 ple_pg_size;
4306 u16 ple_free_pg;
4307 u16 c0_rx_qta;
4308 u16 c1_rx_qta;
4309 };
4310
4311 enum rtw89_host_rpr_mode {
4312 RTW89_RPR_MODE_POH = 0,
4313 RTW89_RPR_MODE_STF
4314 };
4315
4316 #define RTW89_COMPLETION_BUF_SIZE 40
4317 #define RTW89_WAIT_COND_IDLE UINT_MAX
4318
4319 struct rtw89_completion_data {
4320 bool err;
4321 u8 buf[RTW89_COMPLETION_BUF_SIZE];
4322 };
4323
4324 struct rtw89_wait_info {
4325 atomic_t cond;
4326 struct completion completion;
4327 struct rtw89_completion_data data;
4328 };
4329
4330 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4331
rtw89_init_wait(struct rtw89_wait_info * wait)4332 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4333 {
4334 init_completion(&wait->completion);
4335 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4336 }
4337
4338 struct rtw89_mac_info {
4339 struct rtw89_dle_info dle_info;
4340 struct rtw89_hfc_param hfc_param;
4341 enum rtw89_qta_mode qta_mode;
4342 u8 rpwm_seq_num;
4343 u8 cpwm_seq_num;
4344
4345 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4346 struct rtw89_wait_info fw_ofld_wait;
4347 };
4348
4349 enum rtw89_fwdl_check_type {
4350 RTW89_FWDL_CHECK_FREERTOS_DONE,
4351 RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4352 RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4353 RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4354 RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4355 };
4356
4357 enum rtw89_fw_type {
4358 RTW89_FW_NORMAL = 1,
4359 RTW89_FW_WOWLAN = 3,
4360 RTW89_FW_NORMAL_CE = 5,
4361 RTW89_FW_BBMCU0 = 64,
4362 RTW89_FW_BBMCU1 = 65,
4363 RTW89_FW_LOGFMT = 255,
4364 };
4365
4366 enum rtw89_fw_feature {
4367 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4368 RTW89_FW_FEATURE_SCAN_OFFLOAD,
4369 RTW89_FW_FEATURE_TX_WAKE,
4370 RTW89_FW_FEATURE_CRASH_TRIGGER,
4371 RTW89_FW_FEATURE_NO_PACKET_DROP,
4372 RTW89_FW_FEATURE_NO_DEEP_PS,
4373 RTW89_FW_FEATURE_NO_LPS_PG,
4374 RTW89_FW_FEATURE_BEACON_FILTER,
4375 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4376 RTW89_FW_FEATURE_WOW_REASON_V1,
4377 };
4378
4379 struct rtw89_fw_suit {
4380 enum rtw89_fw_type type;
4381 const u8 *data;
4382 u32 size;
4383 u8 major_ver;
4384 u8 minor_ver;
4385 u8 sub_ver;
4386 u8 sub_idex;
4387 u16 build_year;
4388 u16 build_mon;
4389 u16 build_date;
4390 u16 build_hour;
4391 u16 build_min;
4392 u8 cmd_ver;
4393 u8 hdr_ver;
4394 u32 commitid;
4395 };
4396
4397 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
4398 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4399 #define RTW89_FW_SUIT_VER_CODE(s) \
4400 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4401
4402 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
4403 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
4404 (mfw_hdr)->ver.minor, \
4405 (mfw_hdr)->ver.sub, \
4406 (mfw_hdr)->ver.idx)
4407
4408 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
4409 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
4410 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
4411 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
4412 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4413
4414 struct rtw89_fw_req_info {
4415 const struct firmware *firmware;
4416 struct completion completion;
4417 };
4418
4419 struct rtw89_fw_log {
4420 struct rtw89_fw_suit suit;
4421 bool enable;
4422 u32 last_fmt_id;
4423 u32 fmt_count;
4424 const __le32 *fmt_ids;
4425 const char *(*fmts)[];
4426 };
4427
4428 struct rtw89_fw_elm_info {
4429 struct rtw89_phy_table *bb_tbl;
4430 struct rtw89_phy_table *bb_gain;
4431 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4432 struct rtw89_phy_table *rf_nctl;
4433 struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4434 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4435 };
4436
4437 enum rtw89_fw_mss_dev_type {
4438 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4439 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4440 };
4441
4442 struct rtw89_fw_secure {
4443 bool secure_boot;
4444 u32 sb_sel_mgn;
4445 u8 mss_dev_type;
4446 u8 mss_cust_idx;
4447 u8 mss_key_num;
4448 };
4449
4450 struct rtw89_fw_info {
4451 struct rtw89_fw_req_info req;
4452 int fw_format;
4453 u8 h2c_seq;
4454 u8 rec_seq;
4455 u8 h2c_counter;
4456 u8 c2h_counter;
4457 struct rtw89_fw_suit normal;
4458 struct rtw89_fw_suit wowlan;
4459 struct rtw89_fw_suit bbmcu0;
4460 struct rtw89_fw_suit bbmcu1;
4461 struct rtw89_fw_log log;
4462 u32 feature_map;
4463 struct rtw89_fw_elm_info elm_info;
4464 struct rtw89_fw_secure sec;
4465 };
4466
4467 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4468 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4469
4470 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4471 ((_fw)->feature_map |= BIT(_fw_feature))
4472
4473 struct rtw89_cam_info {
4474 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4475 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4476 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4477 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4478 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4479 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4480 };
4481
4482 enum rtw89_sar_sources {
4483 RTW89_SAR_SOURCE_NONE,
4484 RTW89_SAR_SOURCE_COMMON,
4485
4486 RTW89_SAR_SOURCE_NR,
4487 };
4488
4489 enum rtw89_sar_subband {
4490 RTW89_SAR_2GHZ_SUBBAND,
4491 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4492 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4493 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
4494 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4495 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4496 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4497 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4498 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4499 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4500
4501 RTW89_SAR_SUBBAND_NR,
4502 };
4503
4504 struct rtw89_sar_cfg_common {
4505 bool set[RTW89_SAR_SUBBAND_NR];
4506 s32 cfg[RTW89_SAR_SUBBAND_NR];
4507 };
4508
4509 struct rtw89_sar_info {
4510 /* used to decide how to acces SAR cfg union */
4511 enum rtw89_sar_sources src;
4512
4513 /* reserved for different knids of SAR cfg struct.
4514 * supposed that a single cfg struct cannot handle various SAR sources.
4515 */
4516 union {
4517 struct rtw89_sar_cfg_common cfg_common;
4518 };
4519 };
4520
4521 enum rtw89_tas_state {
4522 RTW89_TAS_STATE_DPR_OFF,
4523 RTW89_TAS_STATE_DPR_ON,
4524 RTW89_TAS_STATE_DPR_FORBID,
4525 };
4526
4527 #define RTW89_TAS_MAX_WINDOW 50
4528 struct rtw89_tas_info {
4529 s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
4530 s32 total_txpwr;
4531 u8 cur_idx;
4532 s8 dpr_gap;
4533 s8 delta;
4534 enum rtw89_tas_state state;
4535 bool enable;
4536 };
4537
4538 struct rtw89_chanctx_cfg {
4539 enum rtw89_sub_entity_idx idx;
4540 int ref_count;
4541 };
4542
4543 enum rtw89_chanctx_changes {
4544 RTW89_CHANCTX_REMOTE_STA_CHANGE,
4545 RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4546 RTW89_CHANCTX_P2P_PS_CHANGE,
4547 RTW89_CHANCTX_BT_SLOT_CHANGE,
4548 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4549
4550 NUM_OF_RTW89_CHANCTX_CHANGES,
4551 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4552 };
4553
4554 enum rtw89_entity_mode {
4555 RTW89_ENTITY_MODE_SCC,
4556 RTW89_ENTITY_MODE_MCC_PREPARE,
4557 RTW89_ENTITY_MODE_MCC,
4558
4559 NUM_OF_RTW89_ENTITY_MODE,
4560 RTW89_ENTITY_MODE_INVALID = -EINVAL,
4561 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
4562 };
4563
4564 struct rtw89_sub_entity {
4565 struct cfg80211_chan_def chandef;
4566 struct rtw89_chan chan;
4567 struct rtw89_chan_rcd rcd;
4568
4569 /* only assigned when running with chanctx_ops */
4570 struct rtw89_chanctx_cfg *cfg;
4571 };
4572
4573 struct rtw89_edcca_bak {
4574 u8 a;
4575 u8 p;
4576 u8 ppdu;
4577 u8 th_old;
4578 };
4579
4580 enum rtw89_dm_type {
4581 RTW89_DM_DYNAMIC_EDCCA,
4582 };
4583
4584 struct rtw89_hal {
4585 u32 rx_fltr;
4586 u8 cv;
4587 u8 acv;
4588 u32 antenna_tx;
4589 u32 antenna_rx;
4590 u8 tx_nss;
4591 u8 rx_nss;
4592 bool tx_path_diversity;
4593 bool ant_diversity;
4594 bool ant_diversity_fixed;
4595 bool support_cckpd;
4596 bool support_igi;
4597 atomic_t roc_entity_idx;
4598
4599 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
4600 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
4601 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
4602 struct cfg80211_chan_def roc_chandef;
4603
4604 bool entity_active;
4605 bool entity_pause;
4606 enum rtw89_entity_mode entity_mode;
4607
4608 struct rtw89_edcca_bak edcca_bak;
4609 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
4610 };
4611
4612 #define RTW89_MAX_MAC_ID_NUM 128
4613 #define RTW89_MAX_PKT_OFLD_NUM 255
4614
4615 enum rtw89_flags {
4616 RTW89_FLAG_POWERON,
4617 RTW89_FLAG_DMAC_FUNC,
4618 RTW89_FLAG_CMAC0_FUNC,
4619 RTW89_FLAG_CMAC1_FUNC,
4620 RTW89_FLAG_FW_RDY,
4621 RTW89_FLAG_RUNNING,
4622 RTW89_FLAG_PROBE_DONE,
4623 RTW89_FLAG_BFEE_MON,
4624 RTW89_FLAG_BFEE_EN,
4625 RTW89_FLAG_BFEE_TIMER_KEEP,
4626 RTW89_FLAG_NAPI_RUNNING,
4627 RTW89_FLAG_LEISURE_PS,
4628 RTW89_FLAG_LOW_POWER_MODE,
4629 RTW89_FLAG_INACTIVE_PS,
4630 RTW89_FLAG_CRASH_SIMULATING,
4631 RTW89_FLAG_SER_HANDLING,
4632 RTW89_FLAG_WOWLAN,
4633 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
4634 RTW89_FLAG_CHANGING_INTERFACE,
4635
4636 NUM_OF_RTW89_FLAGS,
4637 };
4638
4639 enum rtw89_quirks {
4640 RTW89_QUIRK_PCI_BER,
4641
4642 NUM_OF_RTW89_QUIRKS,
4643 };
4644
4645 enum rtw89_pkt_drop_sel {
4646 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4647 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4648 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4649 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4650 RTW89_PKT_DROP_SEL_MACID_ALL,
4651 RTW89_PKT_DROP_SEL_MG0_ONCE,
4652 RTW89_PKT_DROP_SEL_HIQ_ONCE,
4653 RTW89_PKT_DROP_SEL_HIQ_PORT,
4654 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
4655 RTW89_PKT_DROP_SEL_BAND,
4656 RTW89_PKT_DROP_SEL_BAND_ONCE,
4657 RTW89_PKT_DROP_SEL_REL_MACID,
4658 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
4659 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
4660 };
4661
4662 struct rtw89_pkt_drop_params {
4663 enum rtw89_pkt_drop_sel sel;
4664 enum rtw89_mac_idx mac_band;
4665 u8 macid;
4666 u8 port;
4667 u8 mbssid;
4668 bool tf_trs;
4669 u32 macid_band_sel[4];
4670 };
4671
4672 struct rtw89_pkt_stat {
4673 u16 beacon_nr;
4674 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
4675 };
4676
4677 DECLARE_EWMA(thermal, 4, 4);
4678
4679 struct rtw89_phy_stat {
4680 struct ewma_thermal avg_thermal[RF_PATH_MAX];
4681 struct rtw89_pkt_stat cur_pkt_stat;
4682 struct rtw89_pkt_stat last_pkt_stat;
4683 };
4684
4685 enum rtw89_rfk_report_state {
4686 RTW89_RFK_STATE_START = 0x0,
4687 RTW89_RFK_STATE_OK = 0x1,
4688 RTW89_RFK_STATE_FAIL = 0x2,
4689 RTW89_RFK_STATE_TIMEOUT = 0x3,
4690 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
4691 };
4692
4693 struct rtw89_rfk_wait_info {
4694 struct completion completion;
4695 ktime_t start_time;
4696 enum rtw89_rfk_report_state state;
4697 u8 version;
4698 };
4699
4700 #define RTW89_DACK_PATH_NR 2
4701 #define RTW89_DACK_IDX_NR 2
4702 #define RTW89_DACK_MSBK_NR 16
4703 struct rtw89_dack_info {
4704 bool dack_done;
4705 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
4706 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4707 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4708 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4709 u32 dack_cnt;
4710 bool addck_timeout[RTW89_DACK_PATH_NR];
4711 bool dadck_timeout[RTW89_DACK_PATH_NR];
4712 bool msbk_timeout[RTW89_DACK_PATH_NR];
4713 };
4714
4715 enum rtw89_rfk_chs_nrs {
4716 __RTW89_RFK_CHS_NR_V0 = 2,
4717 __RTW89_RFK_CHS_NR_V1 = 3,
4718
4719 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
4720 };
4721
4722 struct rtw89_rfk_mcc_info {
4723 u8 ch[RTW89_RFK_CHS_NR];
4724 u8 band[RTW89_RFK_CHS_NR];
4725 u8 bw[RTW89_RFK_CHS_NR];
4726 u8 table_idx;
4727 };
4728
4729 #define RTW89_IQK_CHS_NR 2
4730 #define RTW89_IQK_PATH_NR 4
4731
4732 struct rtw89_lck_info {
4733 u8 thermal[RF_PATH_MAX];
4734 };
4735
4736 struct rtw89_rx_dck_info {
4737 u8 thermal[RF_PATH_MAX];
4738 };
4739
4740 struct rtw89_iqk_info {
4741 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4742 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4743 bool lok_fail[RTW89_IQK_PATH_NR];
4744 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4745 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4746 u32 iqk_fail_cnt;
4747 bool is_iqk_init;
4748 u32 iqk_channel[RTW89_IQK_CHS_NR];
4749 u8 iqk_band[RTW89_IQK_PATH_NR];
4750 u8 iqk_ch[RTW89_IQK_PATH_NR];
4751 u8 iqk_bw[RTW89_IQK_PATH_NR];
4752 u8 iqk_times;
4753 u8 version;
4754 u32 nb_txcfir[RTW89_IQK_PATH_NR];
4755 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
4756 u32 bp_txkresult[RTW89_IQK_PATH_NR];
4757 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
4758 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
4759 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
4760 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
4761 bool is_nbiqk;
4762 bool iqk_fft_en;
4763 bool iqk_xym_en;
4764 bool iqk_sram_en;
4765 bool iqk_cfir_en;
4766 u32 syn1to2;
4767 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4768 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
4769 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4770 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4771 };
4772
4773 #define RTW89_DPK_RF_PATH 2
4774 #define RTW89_DPK_AVG_THERMAL_NUM 8
4775 #define RTW89_DPK_BKUP_NUM 2
4776 struct rtw89_dpk_bkup_para {
4777 enum rtw89_band band;
4778 enum rtw89_bandwidth bw;
4779 u8 ch;
4780 bool path_ok;
4781 u8 mdpd_en;
4782 u8 txagc_dpk;
4783 u8 ther_dpk;
4784 u8 gs;
4785 u16 pwsf;
4786 };
4787
4788 struct rtw89_dpk_info {
4789 bool is_dpk_enable;
4790 bool is_dpk_reload_en;
4791 u8 dpk_gs[RTW89_PHY_MAX];
4792 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4793 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4794 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4795 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4796 u8 cur_idx[RTW89_DPK_RF_PATH];
4797 u8 cur_k_set;
4798 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4799 u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
4800 u32 dpk_order[RTW89_DPK_RF_PATH];
4801 };
4802
4803 struct rtw89_fem_info {
4804 bool elna_2g;
4805 bool elna_5g;
4806 bool epa_2g;
4807 bool epa_5g;
4808 bool epa_6g;
4809 };
4810
4811 struct rtw89_phy_ch_info {
4812 u8 rssi_min;
4813 u16 rssi_min_macid;
4814 u8 pre_rssi_min;
4815 u8 rssi_max;
4816 u16 rssi_max_macid;
4817 u8 rxsc_160;
4818 u8 rxsc_80;
4819 u8 rxsc_40;
4820 u8 rxsc_20;
4821 u8 rxsc_l;
4822 u8 is_noisy;
4823 };
4824
4825 struct rtw89_agc_gaincode_set {
4826 u8 lna_idx;
4827 u8 tia_idx;
4828 u8 rxb_idx;
4829 };
4830
4831 #define IGI_RSSI_TH_NUM 5
4832 #define FA_TH_NUM 4
4833 #define LNA_GAIN_NUM 7
4834 #define TIA_GAIN_NUM 2
4835 struct rtw89_dig_info {
4836 struct rtw89_agc_gaincode_set cur_gaincode;
4837 bool force_gaincode_idx_en;
4838 struct rtw89_agc_gaincode_set force_gaincode;
4839 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4840 u16 fa_th[FA_TH_NUM];
4841 u8 igi_rssi;
4842 u8 igi_fa_rssi;
4843 u8 fa_rssi_ofst;
4844 u8 dyn_igi_max;
4845 u8 dyn_igi_min;
4846 bool dyn_pd_th_en;
4847 u8 dyn_pd_th_max;
4848 u8 pd_low_th_ofst;
4849 u8 ib_pbk;
4850 s8 ib_pkpwr;
4851 s8 lna_gain_a[LNA_GAIN_NUM];
4852 s8 lna_gain_g[LNA_GAIN_NUM];
4853 s8 *lna_gain;
4854 s8 tia_gain_a[TIA_GAIN_NUM];
4855 s8 tia_gain_g[TIA_GAIN_NUM];
4856 s8 *tia_gain;
4857 bool is_linked_pre;
4858 bool bypass_dig;
4859 };
4860
4861 enum rtw89_multi_cfo_mode {
4862 RTW89_PKT_BASED_AVG_MODE = 0,
4863 RTW89_ENTRY_BASED_AVG_MODE = 1,
4864 RTW89_TP_BASED_AVG_MODE = 2,
4865 };
4866
4867 enum rtw89_phy_cfo_status {
4868 RTW89_PHY_DCFO_STATE_NORMAL = 0,
4869 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4870 RTW89_PHY_DCFO_STATE_HOLD = 2,
4871 RTW89_PHY_DCFO_STATE_MAX
4872 };
4873
4874 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4875 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4876 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4877 };
4878
4879 struct rtw89_cfo_tracking_info {
4880 u16 cfo_timer_ms;
4881 bool cfo_trig_by_timer_en;
4882 enum rtw89_phy_cfo_status phy_cfo_status;
4883 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
4884 u8 phy_cfo_trk_cnt;
4885 bool is_adjust;
4886 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
4887 bool apply_compensation;
4888 u8 crystal_cap;
4889 u8 crystal_cap_default;
4890 u8 def_x_cap;
4891 s8 x_cap_ofst;
4892 u32 sta_cfo_tolerance;
4893 s32 cfo_tail[CFO_TRACK_MAX_USER];
4894 u16 cfo_cnt[CFO_TRACK_MAX_USER];
4895 s32 cfo_avg_pre;
4896 s32 cfo_avg[CFO_TRACK_MAX_USER];
4897 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
4898 s32 dcfo_avg;
4899 s32 dcfo_avg_pre;
4900 u32 packet_count;
4901 u32 packet_count_pre;
4902 s32 residual_cfo_acc;
4903 u8 phy_cfotrk_state;
4904 u8 phy_cfotrk_cnt;
4905 bool divergence_lock_en;
4906 u8 x_cap_lb;
4907 u8 x_cap_ub;
4908 u8 lock_cnt;
4909 };
4910
4911 enum rtw89_tssi_mode {
4912 RTW89_TSSI_NORMAL = 0,
4913 RTW89_TSSI_SCAN = 1,
4914 };
4915
4916 enum rtw89_tssi_alimk_band {
4917 TSSI_ALIMK_2G = 0,
4918 TSSI_ALIMK_5GL,
4919 TSSI_ALIMK_5GM,
4920 TSSI_ALIMK_5GH,
4921 TSSI_ALIMK_MAX
4922 };
4923
4924 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
4925 #define TSSI_TRIM_CH_GROUP_NUM 8
4926 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
4927
4928 #define TSSI_CCK_CH_GROUP_NUM 6
4929 #define TSSI_MCS_2G_CH_GROUP_NUM 5
4930 #define TSSI_MCS_5G_CH_GROUP_NUM 14
4931 #define TSSI_MCS_6G_CH_GROUP_NUM 32
4932 #define TSSI_MCS_CH_GROUP_NUM \
4933 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
4934 #define TSSI_MAX_CH_NUM 67
4935 #define TSSI_ALIMK_VALUE_NUM 8
4936
4937 struct rtw89_tssi_info {
4938 u8 thermal[RF_PATH_MAX];
4939 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
4940 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
4941 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
4942 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
4943 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
4944 s8 extra_ofst[RF_PATH_MAX];
4945 bool tssi_tracking_check[RF_PATH_MAX];
4946 u8 default_txagc_offset[RF_PATH_MAX];
4947 u32 base_thermal[RF_PATH_MAX];
4948 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
4949 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
4950 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
4951 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
4952 u32 tssi_alimk_time;
4953 };
4954
4955 struct rtw89_power_trim_info {
4956 bool pg_thermal_trim;
4957 bool pg_pa_bias_trim;
4958 u8 thermal_trim[RF_PATH_MAX];
4959 u8 pa_bias_trim[RF_PATH_MAX];
4960 u8 pad_bias_trim[RF_PATH_MAX];
4961 };
4962
4963 struct rtw89_regd {
4964 char alpha2[3];
4965 u8 txpwr_regd[RTW89_BAND_NUM];
4966 };
4967
4968 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
4969 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
4970 #define RTW89_5GHZ_UNII4_START_INDEX 25
4971
4972 struct rtw89_regulatory_info {
4973 const struct rtw89_regd *regd;
4974 enum rtw89_reg_6ghz_power reg_6ghz_power;
4975 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
4976 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
4977 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
4978 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
4979 };
4980
4981 enum rtw89_ifs_clm_application {
4982 RTW89_IFS_CLM_INIT = 0,
4983 RTW89_IFS_CLM_BACKGROUND = 1,
4984 RTW89_IFS_CLM_ACS = 2,
4985 RTW89_IFS_CLM_DIG = 3,
4986 RTW89_IFS_CLM_TDMA_DIG = 4,
4987 RTW89_IFS_CLM_DBG = 5,
4988 RTW89_IFS_CLM_DBG_MANUAL = 6
4989 };
4990
4991 enum rtw89_env_racing_lv {
4992 RTW89_RAC_RELEASE = 0,
4993 RTW89_RAC_LV_1 = 1,
4994 RTW89_RAC_LV_2 = 2,
4995 RTW89_RAC_LV_3 = 3,
4996 RTW89_RAC_LV_4 = 4,
4997 RTW89_RAC_MAX_NUM = 5
4998 };
4999
5000 struct rtw89_ccx_para_info {
5001 enum rtw89_env_racing_lv rac_lv;
5002 u16 mntr_time;
5003 u8 nhm_manual_th_ofst;
5004 u8 nhm_manual_th0;
5005 enum rtw89_ifs_clm_application ifs_clm_app;
5006 u32 ifs_clm_manual_th_times;
5007 u32 ifs_clm_manual_th0;
5008 u8 fahm_manual_th_ofst;
5009 u8 fahm_manual_th0;
5010 u8 fahm_numer_opt;
5011 u8 fahm_denom_opt;
5012 };
5013
5014 enum rtw89_ccx_edcca_opt_sc_idx {
5015 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5016 RTW89_CCX_EDCCA_SEG0_S1 = 1,
5017 RTW89_CCX_EDCCA_SEG0_S2 = 2,
5018 RTW89_CCX_EDCCA_SEG0_S3 = 3,
5019 RTW89_CCX_EDCCA_SEG1_P0 = 4,
5020 RTW89_CCX_EDCCA_SEG1_S1 = 5,
5021 RTW89_CCX_EDCCA_SEG1_S2 = 6,
5022 RTW89_CCX_EDCCA_SEG1_S3 = 7
5023 };
5024
5025 enum rtw89_ccx_edcca_opt_bw_idx {
5026 RTW89_CCX_EDCCA_BW20_0 = 0,
5027 RTW89_CCX_EDCCA_BW20_1 = 1,
5028 RTW89_CCX_EDCCA_BW20_2 = 2,
5029 RTW89_CCX_EDCCA_BW20_3 = 3,
5030 RTW89_CCX_EDCCA_BW20_4 = 4,
5031 RTW89_CCX_EDCCA_BW20_5 = 5,
5032 RTW89_CCX_EDCCA_BW20_6 = 6,
5033 RTW89_CCX_EDCCA_BW20_7 = 7
5034 };
5035
5036 #define RTW89_NHM_TH_NUM 11
5037 #define RTW89_FAHM_TH_NUM 11
5038 #define RTW89_NHM_RPT_NUM 12
5039 #define RTW89_FAHM_RPT_NUM 12
5040 #define RTW89_IFS_CLM_NUM 4
5041 struct rtw89_env_monitor_info {
5042 u8 ccx_watchdog_result;
5043 bool ccx_ongoing;
5044 u8 ccx_rac_lv;
5045 bool ccx_manual_ctrl;
5046 u16 ifs_clm_mntr_time;
5047 enum rtw89_ifs_clm_application ifs_clm_app;
5048 u16 ccx_period;
5049 u8 ccx_unit_idx;
5050 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5051 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5052 u16 ifs_clm_tx;
5053 u16 ifs_clm_edcca_excl_cca;
5054 u16 ifs_clm_ofdmfa;
5055 u16 ifs_clm_ofdmcca_excl_fa;
5056 u16 ifs_clm_cckfa;
5057 u16 ifs_clm_cckcca_excl_fa;
5058 u16 ifs_clm_total_ifs;
5059 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5060 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5061 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5062 u8 ifs_clm_tx_ratio;
5063 u8 ifs_clm_edcca_excl_cca_ratio;
5064 u8 ifs_clm_cck_fa_ratio;
5065 u8 ifs_clm_ofdm_fa_ratio;
5066 u8 ifs_clm_cck_cca_excl_fa_ratio;
5067 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5068 u16 ifs_clm_cck_fa_permil;
5069 u16 ifs_clm_ofdm_fa_permil;
5070 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5071 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5072 };
5073
5074 enum rtw89_ser_rcvy_step {
5075 RTW89_SER_DRV_STOP_TX,
5076 RTW89_SER_DRV_STOP_RX,
5077 RTW89_SER_DRV_STOP_RUN,
5078 RTW89_SER_HAL_STOP_DMA,
5079 RTW89_SER_SUPPRESS_LOG,
5080 RTW89_NUM_OF_SER_FLAGS
5081 };
5082
5083 struct rtw89_ser {
5084 u8 state;
5085 u8 alarm_event;
5086 bool prehandle_l1;
5087
5088 struct work_struct ser_hdl_work;
5089 struct delayed_work ser_alarm_work;
5090 const struct state_ent *st_tbl;
5091 const struct event_ent *ev_tbl;
5092 struct list_head msg_q;
5093 spinlock_t msg_q_lock; /* lock when read/write ser msg */
5094 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5095 };
5096
5097 enum rtw89_mac_ax_ps_mode {
5098 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5099 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5100 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
5101 RTW89_MAC_AX_PS_MODE_MAX = 3,
5102 };
5103
5104 enum rtw89_last_rpwm_mode {
5105 RTW89_LAST_RPWM_PS = 0x0,
5106 RTW89_LAST_RPWM_ACTIVE = 0x6,
5107 };
5108
5109 struct rtw89_lps_parm {
5110 u8 macid;
5111 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5112 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5113 };
5114
5115 struct rtw89_ppdu_sts_info {
5116 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
5117 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
5118 };
5119
5120 struct rtw89_early_h2c {
5121 struct list_head list;
5122 u8 *h2c;
5123 u16 h2c_len;
5124 };
5125
5126 struct rtw89_hw_scan_info {
5127 struct ieee80211_vif *scanning_vif;
5128 struct list_head pkt_list[NUM_NL80211_BANDS];
5129 struct rtw89_chan op_chan;
5130 bool abort;
5131 u32 last_chan_idx;
5132 };
5133
5134 enum rtw89_phy_bb_gain_band {
5135 RTW89_BB_GAIN_BAND_2G = 0,
5136 RTW89_BB_GAIN_BAND_5G_L = 1,
5137 RTW89_BB_GAIN_BAND_5G_M = 2,
5138 RTW89_BB_GAIN_BAND_5G_H = 3,
5139 RTW89_BB_GAIN_BAND_6G_L = 4,
5140 RTW89_BB_GAIN_BAND_6G_M = 5,
5141 RTW89_BB_GAIN_BAND_6G_H = 6,
5142 RTW89_BB_GAIN_BAND_6G_UH = 7,
5143
5144 RTW89_BB_GAIN_BAND_NR,
5145 };
5146
5147 enum rtw89_phy_gain_band_be {
5148 RTW89_BB_GAIN_BAND_2G_BE = 0,
5149 RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5150 RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5151 RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5152 RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5153 RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5154 RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5155 RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5156 RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5157 RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5158 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5159 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5160
5161 RTW89_BB_GAIN_BAND_NR_BE,
5162 };
5163
5164 enum rtw89_phy_bb_bw_be {
5165 RTW89_BB_BW_20_40 = 0,
5166 RTW89_BB_BW_80_160_320 = 1,
5167
5168 RTW89_BB_BW_NR_BE,
5169 };
5170
5171 enum rtw89_bw20_sc {
5172 RTW89_BW20_SC_20M = 1,
5173 RTW89_BW20_SC_40M = 2,
5174 RTW89_BW20_SC_80M = 4,
5175 RTW89_BW20_SC_160M = 8,
5176 RTW89_BW20_SC_320M = 16,
5177 };
5178
5179 enum rtw89_cmac_table_bw {
5180 RTW89_CMAC_BW_20M = 0,
5181 RTW89_CMAC_BW_40M = 1,
5182 RTW89_CMAC_BW_80M = 2,
5183 RTW89_CMAC_BW_160M = 3,
5184 RTW89_CMAC_BW_320M = 4,
5185
5186 RTW89_CMAC_BW_NR,
5187 };
5188
5189 enum rtw89_phy_bb_rxsc_num {
5190 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5191 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5192 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5193 };
5194
5195 struct rtw89_phy_bb_gain_info {
5196 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5197 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5198 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5199 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5200 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5201 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5202 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5203 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5204 [RTW89_BB_RXSC_NUM_40];
5205 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5206 [RTW89_BB_RXSC_NUM_80];
5207 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5208 [RTW89_BB_RXSC_NUM_160];
5209 };
5210
5211 struct rtw89_phy_bb_gain_info_be {
5212 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5213 [LNA_GAIN_NUM];
5214 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5215 [TIA_GAIN_NUM];
5216 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5217 [RF_PATH_MAX][LNA_GAIN_NUM];
5218 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5219 [RF_PATH_MAX][LNA_GAIN_NUM];
5220 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5221 [RF_PATH_MAX][LNA_GAIN_NUM + 1];
5222 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5223 [RTW89_BW20_SC_20M];
5224 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5225 [RTW89_BW20_SC_40M];
5226 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5227 [RTW89_BW20_SC_80M];
5228 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5229 [RTW89_BW20_SC_160M];
5230 };
5231
5232 struct rtw89_phy_efuse_gain {
5233 bool offset_valid;
5234 bool comp_valid;
5235 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5236 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
5237 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
5238 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5239 };
5240
5241 #define RTW89_MAX_PATTERN_NUM 18
5242 #define RTW89_MAX_PATTERN_MASK_SIZE 4
5243 #define RTW89_MAX_PATTERN_SIZE 128
5244
5245 struct rtw89_wow_cam_info {
5246 bool r_w;
5247 u8 idx;
5248 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5249 u16 crc;
5250 bool negative_pattern_match;
5251 bool skip_mac_hdr;
5252 bool uc;
5253 bool mc;
5254 bool bc;
5255 bool valid;
5256 };
5257
5258 struct rtw89_wow_key_info {
5259 u8 ptk_tx_iv[8];
5260 u8 valid_check;
5261 u8 symbol_check_en;
5262 u8 gtk_keyidx;
5263 u8 rsvd[5];
5264 u8 ptk_rx_iv[8];
5265 u8 gtk_rx_iv[4][8];
5266 } __packed;
5267
5268 struct rtw89_wow_gtk_info {
5269 u8 kck[32];
5270 u8 kek[32];
5271 u8 tk1[16];
5272 u8 txmickey[8];
5273 u8 rxmickey[8];
5274 __le32 igtk_keyid;
5275 __le64 ipn;
5276 u8 igtk[2][32];
5277 u8 psk[32];
5278 } __packed;
5279
5280 struct rtw89_wow_aoac_report {
5281 u8 rpt_ver;
5282 u8 sec_type;
5283 u8 key_idx;
5284 u8 pattern_idx;
5285 u8 rekey_ok;
5286 u8 ptk_tx_iv[8];
5287 u8 eapol_key_replay_count[8];
5288 u8 gtk[32];
5289 u8 ptk_rx_iv[8];
5290 u8 gtk_rx_iv[4][8];
5291 u64 igtk_key_id;
5292 u64 igtk_ipn;
5293 u8 igtk[32];
5294 u8 csa_pri_ch;
5295 u8 csa_bw;
5296 u8 csa_ch_offset;
5297 u8 csa_chsw_failed;
5298 u8 csa_ch_band;
5299 };
5300
5301 struct rtw89_wow_param {
5302 struct ieee80211_vif *wow_vif;
5303 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5304 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5305 struct rtw89_wow_key_info key_info;
5306 struct rtw89_wow_gtk_info gtk_info;
5307 struct rtw89_wow_aoac_report aoac_rpt;
5308 u8 pattern_cnt;
5309 u8 ptk_alg;
5310 u8 gtk_alg;
5311 u8 ptk_keyidx;
5312 u8 akm;
5313 };
5314
5315 struct rtw89_mcc_limit {
5316 bool enable;
5317 u16 max_tob; /* TU; max time offset behind */
5318 u16 max_toa; /* TU; max time offset ahead */
5319 u16 max_dur; /* TU */
5320 };
5321
5322 struct rtw89_mcc_policy {
5323 u8 c2h_rpt;
5324 u8 tx_null_early;
5325 u8 dis_tx_null;
5326 u8 in_curr_ch;
5327 u8 dis_sw_retry;
5328 u8 sw_retry_count;
5329 };
5330
5331 struct rtw89_mcc_role {
5332 struct rtw89_vif *rtwvif;
5333 struct rtw89_mcc_policy policy;
5334 struct rtw89_mcc_limit limit;
5335
5336 /* only valid when running with FW MRC mechanism */
5337 u8 slot_idx;
5338
5339 /* byte-array in LE order for FW */
5340 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5341
5342 u16 duration; /* TU */
5343 u16 beacon_interval; /* TU */
5344 bool is_2ghz;
5345 bool is_go;
5346 bool is_gc;
5347 };
5348
5349 struct rtw89_mcc_bt_role {
5350 u16 duration; /* TU */
5351 };
5352
5353 struct rtw89_mcc_courtesy {
5354 bool enable;
5355 u8 slot_num;
5356 u8 macid_src;
5357 u8 macid_tgt;
5358 };
5359
5360 enum rtw89_mcc_plan {
5361 RTW89_MCC_PLAN_TAIL_BT,
5362 RTW89_MCC_PLAN_MID_BT,
5363 RTW89_MCC_PLAN_NO_BT,
5364
5365 NUM_OF_RTW89_MCC_PLAN,
5366 };
5367
5368 struct rtw89_mcc_pattern {
5369 s16 tob_ref; /* TU; time offset behind of reference role */
5370 s16 toa_ref; /* TU; time offset ahead of reference role */
5371 s16 tob_aux; /* TU; time offset behind of auxiliary role */
5372 s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5373
5374 enum rtw89_mcc_plan plan;
5375 struct rtw89_mcc_courtesy courtesy;
5376 };
5377
5378 struct rtw89_mcc_sync {
5379 bool enable;
5380 u16 offset; /* TU */
5381 u8 macid_src;
5382 u8 band_src;
5383 u8 port_src;
5384 u8 macid_tgt;
5385 u8 band_tgt;
5386 u8 port_tgt;
5387 };
5388
5389 struct rtw89_mcc_config {
5390 struct rtw89_mcc_pattern pattern;
5391 struct rtw89_mcc_sync sync;
5392 u64 start_tsf;
5393 u16 mcc_interval; /* TU */
5394 u16 beacon_offset; /* TU */
5395 };
5396
5397 enum rtw89_mcc_mode {
5398 RTW89_MCC_MODE_GO_STA,
5399 RTW89_MCC_MODE_GC_STA,
5400 };
5401
5402 struct rtw89_mcc_info {
5403 struct rtw89_wait_info wait;
5404
5405 u8 group;
5406 enum rtw89_mcc_mode mode;
5407 struct rtw89_mcc_role role_ref; /* reference role */
5408 struct rtw89_mcc_role role_aux; /* auxiliary role */
5409 struct rtw89_mcc_bt_role bt_role;
5410 struct rtw89_mcc_config config;
5411 };
5412
5413 struct rtw89_dev {
5414 struct ieee80211_hw *hw;
5415 struct device *dev;
5416 const struct ieee80211_ops *ops;
5417
5418 bool dbcc_en;
5419 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
5420 struct rtw89_hw_scan_info scan_info;
5421 const struct rtw89_chip_info *chip;
5422 const struct rtw89_pci_info *pci_info;
5423 const struct rtw89_rfe_parms *rfe_parms;
5424 struct rtw89_hal hal;
5425 struct rtw89_mcc_info mcc;
5426 struct rtw89_mac_info mac;
5427 struct rtw89_fw_info fw;
5428 struct rtw89_hci_info hci;
5429 struct rtw89_efuse efuse;
5430 struct rtw89_traffic_stats stats;
5431 struct rtw89_rfe_data *rfe_data;
5432
5433 /* ensures exclusive access from mac80211 callbacks */
5434 struct mutex mutex;
5435 struct list_head rtwvifs_list;
5436 /* used to protect rf read write */
5437 struct mutex rf_mutex;
5438 struct workqueue_struct *txq_wq;
5439 struct work_struct txq_work;
5440 struct delayed_work txq_reinvoke_work;
5441 /* used to protect ba_list and forbid_ba_list */
5442 spinlock_t ba_lock;
5443 /* txqs to setup ba session */
5444 struct list_head ba_list;
5445 /* txqs to forbid ba session */
5446 struct list_head forbid_ba_list;
5447 struct work_struct ba_work;
5448 /* used to protect rpwm */
5449 spinlock_t rpwm_lock;
5450
5451 struct rtw89_cam_info cam_info;
5452
5453 struct sk_buff_head c2h_queue;
5454 struct work_struct c2h_work;
5455 struct work_struct ips_work;
5456 struct work_struct load_firmware_work;
5457 struct work_struct cancel_6ghz_probe_work;
5458
5459 struct list_head early_h2c_list;
5460
5461 struct rtw89_ser ser;
5462
5463 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
5464 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
5465 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
5466 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
5467 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
5468
5469 struct rtw89_phy_stat phystat;
5470 struct rtw89_rfk_wait_info rfk_wait;
5471 struct rtw89_dack_info dack;
5472 struct rtw89_iqk_info iqk;
5473 struct rtw89_dpk_info dpk;
5474 struct rtw89_rfk_mcc_info rfk_mcc;
5475 struct rtw89_lck_info lck;
5476 struct rtw89_rx_dck_info rx_dck;
5477 bool is_tssi_mode[RF_PATH_MAX];
5478 bool is_bt_iqk_timeout;
5479
5480 struct rtw89_fem_info fem;
5481 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
5482 struct rtw89_tssi_info tssi;
5483 struct rtw89_power_trim_info pwr_trim;
5484
5485 struct rtw89_cfo_tracking_info cfo_tracking;
5486 struct rtw89_env_monitor_info env_monitor;
5487 struct rtw89_dig_info dig;
5488 struct rtw89_phy_ch_info ch_info;
5489 union {
5490 struct rtw89_phy_bb_gain_info ax;
5491 struct rtw89_phy_bb_gain_info_be be;
5492 } bb_gain;
5493 struct rtw89_phy_efuse_gain efuse_gain;
5494 struct rtw89_phy_ul_tb_info ul_tb_info;
5495 struct rtw89_antdiv_info antdiv;
5496
5497 struct delayed_work track_work;
5498 struct delayed_work chanctx_work;
5499 struct delayed_work coex_act1_work;
5500 struct delayed_work coex_bt_devinfo_work;
5501 struct delayed_work coex_rfk_chk_work;
5502 struct delayed_work cfo_track_work;
5503 struct delayed_work forbid_ba_work;
5504 struct delayed_work roc_work;
5505 struct delayed_work antdiv_work;
5506 struct rtw89_ppdu_sts_info ppdu_sts;
5507 u8 total_sta_assoc;
5508 bool scanning;
5509
5510 struct rtw89_regulatory_info regulatory;
5511 struct rtw89_sar_info sar;
5512 struct rtw89_tas_info tas;
5513
5514 struct rtw89_btc btc;
5515 enum rtw89_ps_mode ps_mode;
5516 bool lps_enabled;
5517
5518 struct rtw89_wow_param wow;
5519
5520 /* napi structure */
5521 struct net_device *netdev;
5522 struct napi_struct napi;
5523 int napi_budget_countdown;
5524
5525 /* HCI related data, keep last */
5526 u8 priv[] __aligned(sizeof(void *));
5527 };
5528
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)5529 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
5530 struct rtw89_core_tx_request *tx_req)
5531 {
5532 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
5533 }
5534
rtw89_hci_reset(struct rtw89_dev * rtwdev)5535 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
5536 {
5537 rtwdev->hci.ops->reset(rtwdev);
5538 }
5539
rtw89_hci_start(struct rtw89_dev * rtwdev)5540 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
5541 {
5542 return rtwdev->hci.ops->start(rtwdev);
5543 }
5544
rtw89_hci_stop(struct rtw89_dev * rtwdev)5545 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
5546 {
5547 rtwdev->hci.ops->stop(rtwdev);
5548 }
5549
rtw89_hci_deinit(struct rtw89_dev * rtwdev)5550 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
5551 {
5552 return rtwdev->hci.ops->deinit(rtwdev);
5553 }
5554
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)5555 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
5556 {
5557 rtwdev->hci.ops->pause(rtwdev, pause);
5558 }
5559
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)5560 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
5561 {
5562 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
5563 }
5564
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)5565 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
5566 {
5567 rtwdev->hci.ops->recalc_int_mit(rtwdev);
5568 }
5569
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)5570 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
5571 {
5572 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
5573 }
5574
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)5575 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
5576 {
5577 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
5578 }
5579
rtw89_hci_mac_pre_deinit(struct rtw89_dev * rtwdev)5580 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
5581 {
5582 return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
5583 }
5584
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)5585 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
5586 bool drop)
5587 {
5588 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5589 return;
5590
5591 if (rtwdev->hci.ops->flush_queues)
5592 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
5593 }
5594
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)5595 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
5596 {
5597 if (rtwdev->hci.ops->recovery_start)
5598 rtwdev->hci.ops->recovery_start(rtwdev);
5599 }
5600
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)5601 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
5602 {
5603 if (rtwdev->hci.ops->recovery_complete)
5604 rtwdev->hci.ops->recovery_complete(rtwdev);
5605 }
5606
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)5607 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
5608 {
5609 if (rtwdev->hci.ops->enable_intr)
5610 rtwdev->hci.ops->enable_intr(rtwdev);
5611 }
5612
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)5613 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
5614 {
5615 if (rtwdev->hci.ops->disable_intr)
5616 rtwdev->hci.ops->disable_intr(rtwdev);
5617 }
5618
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)5619 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
5620 {
5621 if (rtwdev->hci.ops->ctrl_txdma_ch)
5622 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
5623 }
5624
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)5625 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
5626 {
5627 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
5628 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
5629 }
5630
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)5631 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
5632 {
5633 if (rtwdev->hci.ops->ctrl_trxhci)
5634 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
5635 }
5636
rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)5637 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
5638 {
5639 int ret = 0;
5640
5641 if (rtwdev->hci.ops->poll_txdma_ch_idle)
5642 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
5643 return ret;
5644 }
5645
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)5646 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
5647 {
5648 if (rtwdev->hci.ops->clr_idx_all)
5649 rtwdev->hci.ops->clr_idx_all(rtwdev);
5650 }
5651
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)5652 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
5653 {
5654 int ret = 0;
5655
5656 if (rtwdev->hci.ops->rst_bdram)
5657 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
5658 return ret;
5659 }
5660
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)5661 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
5662 {
5663 if (rtwdev->hci.ops->clear)
5664 rtwdev->hci.ops->clear(rtwdev, pdev);
5665 }
5666
5667 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)5668 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
5669 {
5670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
5671
5672 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
5673 }
5674
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)5675 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
5676 {
5677 return rtwdev->hci.ops->read8(rtwdev, addr);
5678 }
5679
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)5680 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
5681 {
5682 return rtwdev->hci.ops->read16(rtwdev, addr);
5683 }
5684
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)5685 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
5686 {
5687 return rtwdev->hci.ops->read32(rtwdev, addr);
5688 }
5689
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)5690 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
5691 {
5692 rtwdev->hci.ops->write8(rtwdev, addr, data);
5693 }
5694
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)5695 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
5696 {
5697 rtwdev->hci.ops->write16(rtwdev, addr, data);
5698 }
5699
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)5700 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
5701 {
5702 rtwdev->hci.ops->write32(rtwdev, addr, data);
5703 }
5704
5705 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5706 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5707 {
5708 u8 val;
5709
5710 val = rtw89_read8(rtwdev, addr);
5711 rtw89_write8(rtwdev, addr, val | bit);
5712 }
5713
5714 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5715 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5716 {
5717 u16 val;
5718
5719 val = rtw89_read16(rtwdev, addr);
5720 rtw89_write16(rtwdev, addr, val | bit);
5721 }
5722
5723 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5724 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5725 {
5726 u32 val;
5727
5728 val = rtw89_read32(rtwdev, addr);
5729 rtw89_write32(rtwdev, addr, val | bit);
5730 }
5731
5732 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)5733 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5734 {
5735 u8 val;
5736
5737 val = rtw89_read8(rtwdev, addr);
5738 rtw89_write8(rtwdev, addr, val & ~bit);
5739 }
5740
5741 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)5742 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5743 {
5744 u16 val;
5745
5746 val = rtw89_read16(rtwdev, addr);
5747 rtw89_write16(rtwdev, addr, val & ~bit);
5748 }
5749
5750 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)5751 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5752 {
5753 u32 val;
5754
5755 val = rtw89_read32(rtwdev, addr);
5756 rtw89_write32(rtwdev, addr, val & ~bit);
5757 }
5758
5759 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5760 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5761 {
5762 u32 shift = __ffs(mask);
5763 u32 orig;
5764 u32 ret;
5765
5766 orig = rtw89_read32(rtwdev, addr);
5767 ret = (orig & mask) >> shift;
5768
5769 return ret;
5770 }
5771
5772 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5773 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5774 {
5775 u32 shift = __ffs(mask);
5776 u32 orig;
5777 u32 ret;
5778
5779 orig = rtw89_read16(rtwdev, addr);
5780 ret = (orig & mask) >> shift;
5781
5782 return ret;
5783 }
5784
5785 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)5786 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5787 {
5788 u32 shift = __ffs(mask);
5789 u32 orig;
5790 u32 ret;
5791
5792 orig = rtw89_read8(rtwdev, addr);
5793 ret = (orig & mask) >> shift;
5794
5795 return ret;
5796 }
5797
5798 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)5799 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
5800 {
5801 u32 shift = __ffs(mask);
5802 u32 orig;
5803 u32 set;
5804
5805 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
5806
5807 orig = rtw89_read32(rtwdev, addr);
5808 set = (orig & ~mask) | ((data << shift) & mask);
5809 rtw89_write32(rtwdev, addr, set);
5810 }
5811
5812 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)5813 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
5814 {
5815 u32 shift;
5816 u16 orig, set;
5817
5818 mask &= 0xffff;
5819 shift = __ffs(mask);
5820
5821 orig = rtw89_read16(rtwdev, addr);
5822 set = (orig & ~mask) | ((data << shift) & mask);
5823 rtw89_write16(rtwdev, addr, set);
5824 }
5825
5826 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)5827 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
5828 {
5829 u32 shift;
5830 u8 orig, set;
5831
5832 mask &= 0xff;
5833 shift = __ffs(mask);
5834
5835 orig = rtw89_read8(rtwdev, addr);
5836 set = (orig & ~mask) | ((data << shift) & mask);
5837 rtw89_write8(rtwdev, addr, set);
5838 }
5839
5840 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)5841 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5842 u32 addr, u32 mask)
5843 {
5844 u32 val;
5845
5846 mutex_lock(&rtwdev->rf_mutex);
5847 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
5848 mutex_unlock(&rtwdev->rf_mutex);
5849
5850 return val;
5851 }
5852
5853 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)5854 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5855 u32 addr, u32 mask, u32 data)
5856 {
5857 mutex_lock(&rtwdev->rf_mutex);
5858 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
5859 mutex_unlock(&rtwdev->rf_mutex);
5860 }
5861
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)5862 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
5863 {
5864 void *p = rtwtxq;
5865
5866 return container_of(p, struct ieee80211_txq, drv_priv);
5867 }
5868
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)5869 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
5870 struct ieee80211_txq *txq)
5871 {
5872 struct rtw89_txq *rtwtxq;
5873
5874 if (!txq)
5875 return;
5876
5877 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
5878 INIT_LIST_HEAD(&rtwtxq->list);
5879 }
5880
rtwvif_to_vif(struct rtw89_vif * rtwvif)5881 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
5882 {
5883 void *p = rtwvif;
5884
5885 return container_of(p, struct ieee80211_vif, drv_priv);
5886 }
5887
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)5888 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
5889 {
5890 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
5891 }
5892
vif_to_rtwvif_safe(struct ieee80211_vif * vif)5893 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
5894 {
5895 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
5896 }
5897
rtwsta_to_sta(struct rtw89_sta * rtwsta)5898 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
5899 {
5900 void *p = rtwsta;
5901
5902 return container_of(p, struct ieee80211_sta, drv_priv);
5903 }
5904
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)5905 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
5906 {
5907 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
5908 }
5909
sta_to_rtwsta_safe(struct ieee80211_sta * sta)5910 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
5911 {
5912 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
5913 }
5914
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)5915 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
5916 {
5917 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
5918 return RATE_INFO_BW_160;
5919 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
5920 return RATE_INFO_BW_80;
5921 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
5922 return RATE_INFO_BW_40;
5923 else
5924 return RATE_INFO_BW_20;
5925 }
5926
5927 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)5928 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
5929 {
5930 switch (hw_band) {
5931 default:
5932 case RTW89_BAND_2G:
5933 return NL80211_BAND_2GHZ;
5934 case RTW89_BAND_5G:
5935 return NL80211_BAND_5GHZ;
5936 case RTW89_BAND_6G:
5937 return NL80211_BAND_6GHZ;
5938 }
5939 }
5940
5941 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)5942 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
5943 {
5944 switch (nl_band) {
5945 default:
5946 case NL80211_BAND_2GHZ:
5947 return RTW89_BAND_2G;
5948 case NL80211_BAND_5GHZ:
5949 return RTW89_BAND_5G;
5950 case NL80211_BAND_6GHZ:
5951 return RTW89_BAND_6G;
5952 }
5953 }
5954
5955 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)5956 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
5957 {
5958 switch (width) {
5959 default:
5960 WARN(1, "Not support bandwidth %d\n", width);
5961 fallthrough;
5962 case NL80211_CHAN_WIDTH_20_NOHT:
5963 case NL80211_CHAN_WIDTH_20:
5964 return RTW89_CHANNEL_WIDTH_20;
5965 case NL80211_CHAN_WIDTH_40:
5966 return RTW89_CHANNEL_WIDTH_40;
5967 case NL80211_CHAN_WIDTH_80:
5968 return RTW89_CHANNEL_WIDTH_80;
5969 case NL80211_CHAN_WIDTH_160:
5970 return RTW89_CHANNEL_WIDTH_160;
5971 }
5972 }
5973
5974 static inline
rtw89_he_rua_to_ru_alloc(u16 rua)5975 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
5976 {
5977 switch (rua) {
5978 default:
5979 WARN(1, "Invalid RU allocation: %d\n", rua);
5980 fallthrough;
5981 case 0 ... 36:
5982 return NL80211_RATE_INFO_HE_RU_ALLOC_26;
5983 case 37 ... 52:
5984 return NL80211_RATE_INFO_HE_RU_ALLOC_52;
5985 case 53 ... 60:
5986 return NL80211_RATE_INFO_HE_RU_ALLOC_106;
5987 case 61 ... 64:
5988 return NL80211_RATE_INFO_HE_RU_ALLOC_242;
5989 case 65 ... 66:
5990 return NL80211_RATE_INFO_HE_RU_ALLOC_484;
5991 case 67:
5992 return NL80211_RATE_INFO_HE_RU_ALLOC_996;
5993 case 68:
5994 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
5995 }
5996 }
5997
5998 static inline
rtw89_get_addr_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5999 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
6000 struct rtw89_sta *rtwsta)
6001 {
6002 if (rtwsta) {
6003 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
6004
6005 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
6006 return &rtwsta->addr_cam;
6007 }
6008 return &rtwvif->addr_cam;
6009 }
6010
6011 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)6012 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
6013 struct rtw89_sta *rtwsta)
6014 {
6015 if (rtwsta) {
6016 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
6017
6018 if (sta->tdls)
6019 return &rtwsta->bssid_cam;
6020 }
6021 return &rtwvif->bssid_cam;
6022 }
6023
6024 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6025 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
6026 struct rtw89_channel_help_params *p,
6027 const struct rtw89_chan *chan,
6028 enum rtw89_mac_idx mac_idx,
6029 enum rtw89_phy_idx phy_idx)
6030 {
6031 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
6032 mac_idx, phy_idx);
6033 }
6034
6035 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6036 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
6037 struct rtw89_channel_help_params *p,
6038 const struct rtw89_chan *chan,
6039 enum rtw89_mac_idx mac_idx,
6040 enum rtw89_phy_idx phy_idx)
6041 {
6042 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
6043 mac_idx, phy_idx);
6044 }
6045
6046 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)6047 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
6048 enum rtw89_sub_entity_idx idx)
6049 {
6050 struct rtw89_hal *hal = &rtwdev->hal;
6051 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx);
6052
6053 if (roc_idx == idx)
6054 return &hal->roc_chandef;
6055
6056 return &hal->sub[idx].chandef;
6057 }
6058
6059 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)6060 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
6061 enum rtw89_sub_entity_idx idx)
6062 {
6063 struct rtw89_hal *hal = &rtwdev->hal;
6064
6065 return &hal->sub[idx].chan;
6066 }
6067
6068 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)6069 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
6070 enum rtw89_sub_entity_idx idx)
6071 {
6072 struct rtw89_hal *hal = &rtwdev->hal;
6073
6074 return &hal->sub[idx].rcd;
6075 }
6076
6077 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)6078 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
6079 {
6080 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
6081 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
6082
6083 if (rtwvif)
6084 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
6085 else
6086 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
6087 }
6088
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)6089 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
6090 {
6091 const struct rtw89_chip_info *chip = rtwdev->chip;
6092
6093 if (chip->ops->fem_setup)
6094 chip->ops->fem_setup(rtwdev);
6095 }
6096
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)6097 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
6098 {
6099 const struct rtw89_chip_info *chip = rtwdev->chip;
6100
6101 if (chip->ops->rfe_gpio)
6102 chip->ops->rfe_gpio(rtwdev);
6103 }
6104
rtw89_chip_rfk_hw_init(struct rtw89_dev * rtwdev)6105 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
6106 {
6107 const struct rtw89_chip_info *chip = rtwdev->chip;
6108
6109 if (chip->ops->rfk_hw_init)
6110 chip->ops->rfk_hw_init(rtwdev);
6111 }
6112
6113 static inline
rtw89_chip_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6114 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6115 {
6116 const struct rtw89_chip_info *chip = rtwdev->chip;
6117
6118 if (chip->ops->bb_preinit)
6119 chip->ops->bb_preinit(rtwdev, phy_idx);
6120 }
6121
6122 static inline
rtw89_chip_bb_postinit(struct rtw89_dev * rtwdev)6123 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
6124 {
6125 const struct rtw89_chip_info *chip = rtwdev->chip;
6126
6127 if (!chip->ops->bb_postinit)
6128 return;
6129
6130 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
6131
6132 if (rtwdev->dbcc_en)
6133 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
6134 }
6135
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)6136 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
6137 {
6138 const struct rtw89_chip_info *chip = rtwdev->chip;
6139
6140 if (chip->ops->bb_sethw)
6141 chip->ops->bb_sethw(rtwdev);
6142 }
6143
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)6144 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
6145 {
6146 const struct rtw89_chip_info *chip = rtwdev->chip;
6147
6148 if (chip->ops->rfk_init)
6149 chip->ops->rfk_init(rtwdev);
6150 }
6151
rtw89_chip_rfk_init_late(struct rtw89_dev * rtwdev)6152 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
6153 {
6154 const struct rtw89_chip_info *chip = rtwdev->chip;
6155
6156 if (chip->ops->rfk_init_late)
6157 chip->ops->rfk_init_late(rtwdev);
6158 }
6159
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev)6160 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
6161 {
6162 const struct rtw89_chip_info *chip = rtwdev->chip;
6163
6164 if (chip->ops->rfk_channel)
6165 chip->ops->rfk_channel(rtwdev);
6166 }
6167
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6168 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
6169 enum rtw89_phy_idx phy_idx)
6170 {
6171 const struct rtw89_chip_info *chip = rtwdev->chip;
6172
6173 if (chip->ops->rfk_band_changed)
6174 chip->ops->rfk_band_changed(rtwdev, phy_idx);
6175 }
6176
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,bool start)6177 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
6178 {
6179 const struct rtw89_chip_info *chip = rtwdev->chip;
6180
6181 if (chip->ops->rfk_scan)
6182 chip->ops->rfk_scan(rtwdev, start);
6183 }
6184
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)6185 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
6186 {
6187 const struct rtw89_chip_info *chip = rtwdev->chip;
6188
6189 if (chip->ops->rfk_track)
6190 chip->ops->rfk_track(rtwdev);
6191 }
6192
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)6193 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
6194 {
6195 const struct rtw89_chip_info *chip = rtwdev->chip;
6196
6197 if (chip->ops->set_txpwr_ctrl)
6198 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
6199 }
6200
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)6201 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
6202 {
6203 const struct rtw89_chip_info *chip = rtwdev->chip;
6204
6205 if (chip->ops->power_trim)
6206 chip->ops->power_trim(rtwdev);
6207 }
6208
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)6209 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
6210 enum rtw89_phy_idx phy_idx)
6211 {
6212 const struct rtw89_chip_info *chip = rtwdev->chip;
6213
6214 if (chip->ops->init_txpwr_unit)
6215 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
6216 }
6217
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)6218 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
6219 enum rtw89_rf_path rf_path)
6220 {
6221 const struct rtw89_chip_info *chip = rtwdev->chip;
6222
6223 if (!chip->ops->get_thermal)
6224 return 0x10;
6225
6226 return chip->ops->get_thermal(rtwdev, rf_path);
6227 }
6228
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)6229 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
6230 struct rtw89_rx_phy_ppdu *phy_ppdu,
6231 struct ieee80211_rx_status *status)
6232 {
6233 const struct rtw89_chip_info *chip = rtwdev->chip;
6234
6235 if (chip->ops->query_ppdu)
6236 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
6237 }
6238
rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6239 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
6240 enum rtw89_phy_idx phy_idx)
6241 {
6242 const struct rtw89_chip_info *chip = rtwdev->chip;
6243
6244 if (chip->ops->ctrl_nbtg_bt_tx)
6245 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
6246 }
6247
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)6248 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
6249 {
6250 const struct rtw89_chip_info *chip = rtwdev->chip;
6251
6252 if (chip->ops->cfg_txrx_path)
6253 chip->ops->cfg_txrx_path(rtwdev);
6254 }
6255
6256 static inline
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)6257 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
6258 struct ieee80211_vif *vif)
6259 {
6260 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6261 const struct rtw89_chip_info *chip = rtwdev->chip;
6262
6263 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
6264 return;
6265
6266 if (chip->ops->set_txpwr_ul_tb_offset)
6267 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
6268 }
6269
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)6270 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
6271 const struct rtw89_txpwr_table *tbl)
6272 {
6273 tbl->load(rtwdev, tbl);
6274 }
6275
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)6276 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
6277 {
6278 const struct rtw89_regd *regd = rtwdev->regulatory.regd;
6279
6280 return regd->txpwr_regd[band];
6281 }
6282
rtw89_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)6283 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
6284 enum rtw89_phy_idx phy_idx)
6285 {
6286 const struct rtw89_chip_info *chip = rtwdev->chip;
6287
6288 if (chip->ops->ctrl_btg_bt_rx)
6289 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
6290 }
6291
6292 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)6293 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
6294 struct rtw89_rx_desc_info *desc_info,
6295 u8 *data, u32 data_offset)
6296 {
6297 const struct rtw89_chip_info *chip = rtwdev->chip;
6298
6299 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
6300 }
6301
6302 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6303 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
6304 struct rtw89_tx_desc_info *desc_info,
6305 void *txdesc)
6306 {
6307 const struct rtw89_chip_info *chip = rtwdev->chip;
6308
6309 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
6310 }
6311
6312 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)6313 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
6314 struct rtw89_tx_desc_info *desc_info,
6315 void *txdesc)
6316 {
6317 const struct rtw89_chip_info *chip = rtwdev->chip;
6318
6319 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
6320 }
6321
6322 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)6323 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
6324 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
6325 {
6326 const struct rtw89_chip_info *chip = rtwdev->chip;
6327
6328 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
6329 }
6330
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)6331 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6332 {
6333 const struct rtw89_chip_info *chip = rtwdev->chip;
6334
6335 chip->ops->cfg_ctrl_path(rtwdev, wl);
6336 }
6337
6338 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)6339 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
6340 u32 *tx_en, enum rtw89_sch_tx_sel sel)
6341 {
6342 const struct rtw89_chip_info *chip = rtwdev->chip;
6343
6344 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
6345 }
6346
6347 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)6348 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
6349 {
6350 const struct rtw89_chip_info *chip = rtwdev->chip;
6351
6352 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
6353 }
6354
6355 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)6356 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
6357 struct rtw89_vif *rtwvif,
6358 struct rtw89_sta *rtwsta)
6359 {
6360 const struct rtw89_chip_info *chip = rtwdev->chip;
6361
6362 if (!chip->ops->h2c_dctl_sec_cam)
6363 return 0;
6364 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
6365 }
6366
get_hdr_bssid(struct ieee80211_hdr * hdr)6367 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
6368 {
6369 __le16 fc = hdr->frame_control;
6370
6371 if (ieee80211_has_tods(fc))
6372 return hdr->addr1;
6373 else if (ieee80211_has_fromds(fc))
6374 return hdr->addr2;
6375 else
6376 return hdr->addr3;
6377 }
6378
rtw89_sta_has_beamformer_cap(struct ieee80211_sta * sta)6379 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
6380 {
6381 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
6382 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
6383 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
6384 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
6385 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
6386 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
6387 return true;
6388 return false;
6389 }
6390
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)6391 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
6392 #if defined(__linux__)
6393 enum rtw89_fw_type type)
6394 #elif defined(__FreeBSD__)
6395 const enum rtw89_fw_type type)
6396 #endif
6397 {
6398 struct rtw89_fw_info *fw_info = &rtwdev->fw;
6399
6400 switch (type) {
6401 case RTW89_FW_WOWLAN:
6402 return &fw_info->wowlan;
6403 case RTW89_FW_LOGFMT:
6404 return &fw_info->log.suit;
6405 case RTW89_FW_BBMCU0:
6406 return &fw_info->bbmcu0;
6407 case RTW89_FW_BBMCU1:
6408 return &fw_info->bbmcu1;
6409 default:
6410 break;
6411 }
6412
6413 return &fw_info->normal;
6414 }
6415
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)6416 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
6417 unsigned int length)
6418 {
6419 struct sk_buff *skb;
6420
6421 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
6422 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
6423 if (!skb)
6424 return NULL;
6425
6426 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
6427 return skb;
6428 }
6429
6430 return dev_alloc_skb(length);
6431 }
6432
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)6433 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
6434 struct rtw89_tx_skb_data *skb_data,
6435 bool tx_done)
6436 {
6437 struct rtw89_tx_wait_info *wait;
6438
6439 rcu_read_lock();
6440
6441 wait = rcu_dereference(skb_data->wait);
6442 if (!wait)
6443 goto out;
6444
6445 wait->tx_done = tx_done;
6446 complete(&wait->completion);
6447
6448 out:
6449 rcu_read_unlock();
6450 }
6451
rtw89_is_mlo_1_1(struct rtw89_dev * rtwdev)6452 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
6453 {
6454 switch (rtwdev->mlo_dbcc_mode) {
6455 case MLO_1_PLUS_1_1RF:
6456 case MLO_1_PLUS_1_2RF:
6457 case DBCC_LEGACY:
6458 return true;
6459 default:
6460 return false;
6461 }
6462 }
6463
rtw89_is_rtl885xb(struct rtw89_dev * rtwdev)6464 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
6465 {
6466 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
6467
6468 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
6469 return true;
6470
6471 return false;
6472 }
6473
6474 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6475 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
6476 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
6477 struct sk_buff *skb, bool fwdl);
6478 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
6479 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
6480 int qsel, unsigned int timeout);
6481 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
6482 struct rtw89_tx_desc_info *desc_info,
6483 void *txdesc);
6484 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
6485 struct rtw89_tx_desc_info *desc_info,
6486 void *txdesc);
6487 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
6488 struct rtw89_tx_desc_info *desc_info,
6489 void *txdesc);
6490 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
6491 struct rtw89_tx_desc_info *desc_info,
6492 void *txdesc);
6493 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
6494 struct rtw89_tx_desc_info *desc_info,
6495 void *txdesc);
6496 void rtw89_core_rx(struct rtw89_dev *rtwdev,
6497 struct rtw89_rx_desc_info *desc_info,
6498 struct sk_buff *skb);
6499 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
6500 struct rtw89_rx_desc_info *desc_info,
6501 u8 *data, u32 data_offset);
6502 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
6503 struct rtw89_rx_desc_info *desc_info,
6504 u8 *data, u32 data_offset);
6505 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
6506 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
6507 int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
6508 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
6509 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
6510 struct ieee80211_vif *vif,
6511 struct ieee80211_sta *sta);
6512 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
6513 struct ieee80211_vif *vif,
6514 struct ieee80211_sta *sta);
6515 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
6516 struct ieee80211_vif *vif,
6517 struct ieee80211_sta *sta);
6518 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
6519 struct ieee80211_vif *vif,
6520 struct ieee80211_sta *sta);
6521 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
6522 struct ieee80211_vif *vif,
6523 struct ieee80211_sta *sta);
6524 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
6525 struct ieee80211_sta *sta,
6526 struct cfg80211_tid_config *tid_config);
6527 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
6528 int rtw89_core_init(struct rtw89_dev *rtwdev);
6529 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
6530 int rtw89_core_register(struct rtw89_dev *rtwdev);
6531 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
6532 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
6533 u32 bus_data_size,
6534 const struct rtw89_chip_info *chip);
6535 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
6536 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
6537 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
6538 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
6539 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
6540 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
6541 struct rtw89_chan *chan);
6542 int rtw89_set_channel(struct rtw89_dev *rtwdev);
6543 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6544 struct rtw89_chan *chan);
6545 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
6546 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
6547 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
6548 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
6549 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
6550 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
6551 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
6552 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
6553 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
6554 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
6555 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
6556 int rtw89_regd_init(struct rtw89_dev *rtwdev,
6557 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
6558 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
6559 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
6560 struct rtw89_traffic_stats *stats);
6561 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
6562 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
6563 const struct rtw89_completion_data *data);
6564 int rtw89_core_start(struct rtw89_dev *rtwdev);
6565 void rtw89_core_stop(struct rtw89_dev *rtwdev);
6566 void rtw89_core_update_beacon_work(struct work_struct *work);
6567 void rtw89_roc_work(struct work_struct *work);
6568 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6569 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6570 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6571 const u8 *mac_addr, bool hw_scan);
6572 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
6573 struct ieee80211_vif *vif, bool hw_scan);
6574 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6575 bool active);
6576 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
6577 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
6578
6579 #if defined(__linux__)
6580 #define rtw89_static_assert(_x) static_assert(_x)
6581 #elif defined(__FreeBSD__)
6582 #define rtw89_static_assert(_x) _Static_assert(_x, "bad array size")
6583 #endif
6584
6585 #endif
6586