xref: /freebsd/sys/dev/bnxt/bnxt_en/bnxt.h (revision 3d8bbe00)
1 /*-
2  * Broadcom NetXtreme-C/E network driver.
3  *
4  * Copyright (c) 2016 Broadcom, All Rights Reserved.
5  * The term Broadcom refers to Broadcom Limited and/or its subsidiaries
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26  * THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #ifndef _BNXT_H
31 #define _BNXT_H
32 
33 #include <sys/param.h>
34 #include <sys/socket.h>
35 #include <sys/sysctl.h>
36 #include <sys/taskqueue.h>
37 #include <sys/bitstring.h>
38 
39 #include <machine/bus.h>
40 
41 #include <net/ethernet.h>
42 #include <net/if.h>
43 #include <net/if_var.h>
44 #include <net/iflib.h>
45 #include <linux/types.h>
46 
47 #include "hsi_struct_def.h"
48 #include "bnxt_dcb.h"
49 #include "bnxt_auxbus_compat.h"
50 
51 #define DFLT_HWRM_CMD_TIMEOUT		500
52 
53 /* PCI IDs */
54 #define BROADCOM_VENDOR_ID	0x14E4
55 
56 #define BCM57301	0x16c8
57 #define BCM57302	0x16c9
58 #define BCM57304	0x16ca
59 #define BCM57311	0x16ce
60 #define BCM57312	0x16cf
61 #define BCM57314	0x16df
62 #define BCM57402	0x16d0
63 #define BCM57402_NPAR	0x16d4
64 #define BCM57404	0x16d1
65 #define BCM57404_NPAR	0x16e7
66 #define BCM57406	0x16d2
67 #define BCM57406_NPAR	0x16e8
68 #define BCM57407	0x16d5
69 #define BCM57407_NPAR	0x16ea
70 #define BCM57407_SFP	0x16e9
71 #define BCM57412	0x16d6
72 #define BCM57412_NPAR1	0x16de
73 #define BCM57412_NPAR2	0x16eb
74 #define BCM57414	0x16d7
75 #define BCM57414_NPAR1	0x16ec
76 #define BCM57414_NPAR2	0x16ed
77 #define BCM57416	0x16d8
78 #define BCM57416_NPAR1	0x16ee
79 #define BCM57416_NPAR2	0x16ef
80 #define BCM57416_SFP	0x16e3
81 #define BCM57417	0x16d9
82 #define BCM57417_NPAR1	0x16c0
83 #define BCM57417_NPAR2	0x16cc
84 #define BCM57417_SFP	0x16e2
85 #define BCM57454	0x1614
86 #define BCM58700	0x16cd
87 #define BCM57508  	0x1750
88 #define BCM57504  	0x1751
89 #define BCM57502  	0x1752
90 #define NETXTREME_C_VF1	0x16cb
91 #define NETXTREME_C_VF2	0x16e1
92 #define NETXTREME_C_VF3	0x16e5
93 #define NETXTREME_E_VF1	0x16c1
94 #define NETXTREME_E_VF2	0x16d3
95 #define NETXTREME_E_VF3	0x16dc
96 
97 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)				\
98 	(((data1) &							\
99 	  HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
100 	 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
101 
102 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1)						\
103 	(((data1) &									\
104 	  HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK)  >>	\
105 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
106 
107 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2)						\
108 	(((data2) &									\
109 	  HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>	\
110 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
111 
112 #define BNXT_EVENT_DBR_EPOCH(data)										\
113 	(((data) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK) >>	\
114 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT)
115 
116 #define BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2)						\
117 	(((data2) &										\
118 	  HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK) >>	\
119 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT)
120 
121 #define EVENT_DATA2_NVM_ERR_ADDR(data2)						\
122 	(((data2) &								\
123 	  HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK) >>	\
124 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT)
125 
126 #define EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1)					\
127 	(((data1) &										\
128 	  HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR) ==		\
129 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING)
130 
131 #define EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1)						\
132 	(((data1) &									\
133 	  HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) ==	\
134 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE)
135 
136 #define EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1)						\
137 	(((data1) &									\
138 	  HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) ==	\
139 	 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE)
140 
141 #define EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1)			\
142 	((data1) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK)
143 
144 #define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2)				\
145 	((data2) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK)
146 
147 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)                   \
148 	(((data1) &                                                     \
149 	  HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
150 	HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
151 
152 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)                  \
153 	((data2) &                                                      \
154 	HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
155 
156 #define EVENT_DATA1_RECOVERY_ENABLED(data1)				\
157 	!!((data1) &							\
158 	   HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
159 
160 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)				\
161 	!!((data1) &							\
162 	   HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
163 
164 #define INVALID_STATS_CTX_ID     -1
165 
166 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power
167  * of two. The hardware has no particular limitation. */
168 #define BNXT_MAX_RXD	((INT32_MAX >> 1) + 1)
169 #define BNXT_MAX_TXD	((INT32_MAX >> 1) + 1)
170 
171 #define CSUM_OFFLOAD		(CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
172 				 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
173 				 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
174 
175 #define BNXT_MAX_MTU	9600
176 
177 #define BNXT_RSS_HASH_TYPE_TCPV4	0
178 #define BNXT_RSS_HASH_TYPE_UDPV4	1
179 #define BNXT_RSS_HASH_TYPE_IPV4		2
180 #define BNXT_RSS_HASH_TYPE_TCPV6	3
181 #define BNXT_RSS_HASH_TYPE_UDPV6	4
182 #define BNXT_RSS_HASH_TYPE_IPV6		5
183 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F)
184 
185 #define BNXT_NO_MORE_WOL_FILTERS	0xFFFF
186 #define bnxt_wol_supported(softc)	(!((softc)->flags & BNXT_FLAG_VF) && \
187 					  ((softc)->flags & BNXT_FLAG_WOL_CAP ))
188 
189 /* 64-bit doorbell */
190 #define DBR_INDEX_MASK                                  0x0000000000ffffffULL
191 #define DBR_PI_LO_MASK                                  0xff000000UL
192 #define DBR_PI_LO_SFT                                   24
193 #define DBR_XID_MASK                                    0x000fffff00000000ULL
194 #define DBR_XID_SFT                                     32
195 #define DBR_PI_HI_MASK                                  0xf0000000000000ULL
196 #define DBR_PI_HI_SFT                                   52
197 #define DBR_PATH_L2                                     (0x1ULL << 56)
198 #define DBR_VALID                                       (0x1ULL << 58)
199 #define DBR_TYPE_SQ                                     (0x0ULL << 60)
200 #define DBR_TYPE_RQ                                     (0x1ULL << 60)
201 #define DBR_TYPE_SRQ                                    (0x2ULL << 60)
202 #define DBR_TYPE_SRQ_ARM                                (0x3ULL << 60)
203 #define DBR_TYPE_CQ                                     (0x4ULL << 60)
204 #define DBR_TYPE_CQ_ARMSE                               (0x5ULL << 60)
205 #define DBR_TYPE_CQ_ARMALL                              (0x6ULL << 60)
206 #define DBR_TYPE_CQ_ARMENA                              (0x7ULL << 60)
207 #define DBR_TYPE_SRQ_ARMENA                             (0x8ULL << 60)
208 #define DBR_TYPE_CQ_CUTOFF_ACK                          (0x9ULL << 60)
209 #define DBR_TYPE_NQ                                     (0xaULL << 60)
210 #define DBR_TYPE_NQ_ARM                                 (0xbULL << 60)
211 #define DBR_TYPE_PUSH_START                             (0xcULL << 60)
212 #define DBR_TYPE_PUSH_END                               (0xdULL << 60)
213 #define DBR_TYPE_NULL                                   (0xfULL << 60)
214 
215 #define BNXT_MAX_L2_QUEUES				128
216 #define BNXT_ROCE_IRQ_COUNT				9
217 
218 #define BNXT_MAX_NUM_QUEUES (BNXT_MAX_L2_QUEUES + BNXT_ROCE_IRQ_COUNT)
219 
220 /* Completion related defines */
221 #define CMP_VALID(cmp, v_bit) \
222 	((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) )
223 
224 /* Chip class phase 5 */
225 #define BNXT_CHIP_P5(sc) ((sc->flags & BNXT_FLAG_CHIP_P5))
226 
227 #define DB_PF_OFFSET_P5                                 0x10000
228 #define DB_VF_OFFSET_P5                                 0x4000
229 #define NQ_VALID(cmp, v_bit) \
230 	((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) )
231 
232 #ifndef DIV_ROUND_UP
233 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
234 #endif
235 #ifndef roundup
236 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
237 #endif
238 
239 #define NEXT_CP_CONS_V(ring, cons, v_bit) do {				    \
240 	if (__predict_false(++(cons) == (ring)->ring_size))		    \
241 		((cons) = 0, (v_bit) = !v_bit);				    \
242 } while (0)
243 
244 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \
245 								0 : idx + 1)
246 
247 #define CMPL_PREFETCH_NEXT(cpr, idx)					    \
248 	__builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\
249 	    (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) &		    \
250 	    ((cpr)->ring.ring_size - 1)])
251 
252 /* Lock macros */
253 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \
254     mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF)
255 #define BNXT_HWRM_LOCK(_softc)		mtx_lock(&(_softc)->hwrm_lock)
256 #define BNXT_HWRM_UNLOCK(_softc)	mtx_unlock(&(_softc)->hwrm_lock)
257 #define BNXT_HWRM_LOCK_DESTROY(_softc)	mtx_destroy(&(_softc)->hwrm_lock)
258 #define BNXT_HWRM_LOCK_ASSERT(_softc)	mtx_assert(&(_softc)->hwrm_lock,    \
259     MA_OWNED)
260 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info)				    \
261 	((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) ||       \
262          (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) ||       \
263 	 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg))
264 
265 /* Chip info */
266 #define BNXT_TSO_SIZE	UINT16_MAX
267 
268 #define min_t(type, x, y) ({                    \
269         type __min1 = (x);                      \
270         type __min2 = (y);                      \
271         __min1 < __min2 ? __min1 : __min2; })
272 
273 #define max_t(type, x, y) ({                    \
274         type __max1 = (x);                      \
275         type __max2 = (y);                      \
276         __max1 > __max2 ? __max1 : __max2; })
277 
278 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
279 
280 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do {			\
281 	if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed)	\
282 		ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL);	\
283 } while(0)
284 
285 #define BNXT_MIN_FRAME_SIZE	52	/* Frames must be padded to this size for some A0 chips */
286 
287 #define BNXT_RX_STATS_EXT_OFFSET(counter)		\
288 	(offsetof(struct rx_port_stats_ext, counter) / 8)
289 
290 #define BNXT_RX_STATS_EXT_NUM_LEGACY			\
291 	BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
292 
293 #define BNXT_TX_STATS_EXT_OFFSET(counter)		\
294 	(offsetof(struct tx_port_stats_ext, counter) / 8)
295 
296 extern const char bnxt_driver_version[];
297 typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx);
298 typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx);
299 typedef void (*bnxt_doorbell_rx_cq)(void *, bool);
300 typedef void (*bnxt_doorbell_tx_cq)(void *, bool);
301 typedef void (*bnxt_doorbell_nq)(void *, bool);
302 
303 typedef struct bnxt_doorbell_ops {
304         bnxt_doorbell_tx bnxt_db_tx;
305         bnxt_doorbell_rx bnxt_db_rx;
306         bnxt_doorbell_rx_cq bnxt_db_rx_cq;
307         bnxt_doorbell_tx_cq bnxt_db_tx_cq;
308         bnxt_doorbell_nq bnxt_db_nq;
309 } bnxt_dooorbell_ops_t;
310 /* NVRAM access */
311 enum bnxt_nvm_directory_type {
312 	BNX_DIR_TYPE_UNUSED = 0,
313 	BNX_DIR_TYPE_PKG_LOG = 1,
314 	BNX_DIR_TYPE_UPDATE = 2,
315 	BNX_DIR_TYPE_CHIMP_PATCH = 3,
316 	BNX_DIR_TYPE_BOOTCODE = 4,
317 	BNX_DIR_TYPE_VPD = 5,
318 	BNX_DIR_TYPE_EXP_ROM_MBA = 6,
319 	BNX_DIR_TYPE_AVS = 7,
320 	BNX_DIR_TYPE_PCIE = 8,
321 	BNX_DIR_TYPE_PORT_MACRO = 9,
322 	BNX_DIR_TYPE_APE_FW = 10,
323 	BNX_DIR_TYPE_APE_PATCH = 11,
324 	BNX_DIR_TYPE_KONG_FW = 12,
325 	BNX_DIR_TYPE_KONG_PATCH = 13,
326 	BNX_DIR_TYPE_BONO_FW = 14,
327 	BNX_DIR_TYPE_BONO_PATCH = 15,
328 	BNX_DIR_TYPE_TANG_FW = 16,
329 	BNX_DIR_TYPE_TANG_PATCH = 17,
330 	BNX_DIR_TYPE_BOOTCODE_2 = 18,
331 	BNX_DIR_TYPE_CCM = 19,
332 	BNX_DIR_TYPE_PCI_CFG = 20,
333 	BNX_DIR_TYPE_TSCF_UCODE = 21,
334 	BNX_DIR_TYPE_ISCSI_BOOT = 22,
335 	BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24,
336 	BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25,
337 	BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26,
338 	BNX_DIR_TYPE_EXT_PHY = 27,
339 	BNX_DIR_TYPE_SHARED_CFG = 40,
340 	BNX_DIR_TYPE_PORT_CFG = 41,
341 	BNX_DIR_TYPE_FUNC_CFG = 42,
342 	BNX_DIR_TYPE_MGMT_CFG = 48,
343 	BNX_DIR_TYPE_MGMT_DATA = 49,
344 	BNX_DIR_TYPE_MGMT_WEB_DATA = 50,
345 	BNX_DIR_TYPE_MGMT_WEB_META = 51,
346 	BNX_DIR_TYPE_MGMT_EVENT_LOG = 52,
347 	BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53
348 };
349 
350 enum bnxnvm_pkglog_field_index {
351 	BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP	= 0,
352 	BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION		= 1,
353 	BNX_PKG_LOG_FIELD_IDX_PKG_VERSION		= 2,
354 	BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP		= 3,
355 	BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM		= 4,
356 	BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS		= 5,
357 	BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK		= 6
358 };
359 
360 #define BNX_DIR_ORDINAL_FIRST		0
361 #define BNX_DIR_EXT_NONE		0
362 
363 struct bnxt_bar_info {
364 	struct resource		*res;
365 	bus_space_tag_t		tag;
366 	bus_space_handle_t	handle;
367 	bus_size_t		size;
368 	int			rid;
369 };
370 
371 struct bnxt_flow_ctrl {
372 	bool rx;
373 	bool tx;
374 	bool autoneg;
375 };
376 
377 struct bnxt_link_info {
378 	uint8_t		media_type;
379 	uint8_t		transceiver;
380 	uint8_t		phy_addr;
381 	uint8_t		phy_link_status;
382 	uint8_t		wire_speed;
383 	uint8_t		loop_back;
384 	uint8_t		link_up;
385 	uint8_t		last_link_up;
386 	uint8_t		duplex;
387 	uint8_t		last_duplex;
388 	uint8_t		last_phy_type;
389 	struct bnxt_flow_ctrl   flow_ctrl;
390 	struct bnxt_flow_ctrl   last_flow_ctrl;
391 	uint8_t		duplex_setting;
392 	uint8_t		auto_mode;
393 #define PHY_VER_LEN		3
394 	uint8_t		phy_ver[PHY_VER_LEN];
395 	uint8_t		phy_type;
396 #define BNXT_PHY_STATE_ENABLED		0
397 #define BNXT_PHY_STATE_DISABLED		1
398 	uint8_t		phy_state;
399 
400 	uint16_t	link_speed;
401 	uint16_t	support_speeds;
402 	uint16_t	support_pam4_speeds;
403 	uint16_t	auto_link_speeds;
404 	uint16_t	auto_pam4_link_speeds;
405 	uint16_t	force_link_speed;
406 	uint16_t	force_pam4_link_speed;
407 	bool		force_pam4_speed_set_by_user;
408 
409 	uint16_t	advertising;
410 	uint16_t	advertising_pam4;
411 
412 	uint32_t	preemphasis;
413 	uint16_t	support_auto_speeds;
414 	uint16_t	support_force_speeds;
415 	uint16_t	support_pam4_auto_speeds;
416 	uint16_t	support_pam4_force_speeds;
417 #define BNXT_SIG_MODE_NRZ	HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ
418 #define BNXT_SIG_MODE_PAM4	HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
419 	uint8_t		req_signal_mode;
420 
421 	uint8_t		active_fec_sig_mode;
422 	uint8_t		sig_mode;
423 
424 	/* copy of requested setting */
425 	uint8_t		autoneg;
426 #define BNXT_AUTONEG_SPEED	1
427 #define BNXT_AUTONEG_FLOW_CTRL	2
428 	uint8_t		req_duplex;
429 	uint16_t	req_link_speed;
430 	uint8_t		module_status;
431 	struct hwrm_port_phy_qcfg_output    phy_qcfg_resp;
432 };
433 
434 enum bnxt_phy_type {
435 	BNXT_MEDIA_CR = 0,
436 	BNXT_MEDIA_LR,
437 	BNXT_MEDIA_SR,
438 	BNXT_MEDIA_KR,
439 	BNXT_MEDIA_END
440 };
441 
442 enum bnxt_cp_type {
443 	BNXT_DEFAULT,
444 	BNXT_TX,
445 	BNXT_RX,
446 	BNXT_SHARED
447 };
448 
449 struct bnxt_queue_info {
450 	uint8_t		queue_id;
451 	uint8_t		queue_profile;
452 };
453 
454 struct bnxt_func_info {
455 	uint32_t	fw_fid;
456 	uint8_t		mac_addr[ETHER_ADDR_LEN];
457 	uint16_t	max_rsscos_ctxs;
458 	uint16_t	max_cp_rings;
459 	uint16_t	max_tx_rings;
460 	uint16_t	max_rx_rings;
461 	uint16_t	max_hw_ring_grps;
462 	uint16_t	max_irqs;
463 	uint16_t	max_l2_ctxs;
464 	uint16_t	max_vnics;
465 	uint16_t	max_stat_ctxs;
466 };
467 
468 struct bnxt_pf_info {
469 #define BNXT_FIRST_PF_FID	1
470 #define BNXT_FIRST_VF_FID	128
471 	uint8_t		port_id;
472 	uint32_t	first_vf_id;
473 	uint16_t	active_vfs;
474 	uint16_t	max_vfs;
475 	uint32_t	max_encap_records;
476 	uint32_t	max_decap_records;
477 	uint32_t	max_tx_em_flows;
478 	uint32_t	max_tx_wm_flows;
479 	uint32_t	max_rx_em_flows;
480 	uint32_t	max_rx_wm_flows;
481 	unsigned long	*vf_event_bmap;
482 	uint16_t	hwrm_cmd_req_pages;
483 	void		*hwrm_cmd_req_addr[4];
484 	bus_addr_t	hwrm_cmd_req_dma_addr[4];
485 };
486 
487 struct bnxt_vf_info {
488 	uint16_t	fw_fid;
489 	uint8_t		mac_addr[ETHER_ADDR_LEN];
490 	uint16_t	max_rsscos_ctxs;
491 	uint16_t	max_cp_rings;
492 	uint16_t	max_tx_rings;
493 	uint16_t	max_rx_rings;
494 	uint16_t	max_hw_ring_grps;
495 	uint16_t	max_l2_ctxs;
496 	uint16_t	max_irqs;
497 	uint16_t	max_vnics;
498 	uint16_t	max_stat_ctxs;
499 	uint32_t	vlan;
500 #define BNXT_VF_QOS		0x1
501 #define BNXT_VF_SPOOFCHK	0x2
502 #define BNXT_VF_LINK_FORCED	0x4
503 #define BNXT_VF_LINK_UP		0x8
504 	uint32_t	flags;
505 	uint32_t	func_flags; /* func cfg flags */
506 	uint32_t	min_tx_rate;
507 	uint32_t	max_tx_rate;
508 	void		*hwrm_cmd_req_addr;
509 	bus_addr_t	hwrm_cmd_req_dma_addr;
510 };
511 
512 #define BNXT_PF(softc)		(!((softc)->flags & BNXT_FLAG_VF))
513 #define BNXT_VF(softc)		((softc)->flags & BNXT_FLAG_VF)
514 
515 struct bnxt_vlan_tag {
516 	SLIST_ENTRY(bnxt_vlan_tag) next;
517 	uint64_t	filter_id;
518 	uint16_t	tag;
519 };
520 
521 struct bnxt_vnic_info {
522 	uint16_t	id;
523 	uint16_t	def_ring_grp;
524 	uint16_t	cos_rule;
525 	uint16_t	lb_rule;
526 	uint16_t	mru;
527 
528 	uint32_t	rx_mask;
529 	struct iflib_dma_info mc_list;
530 	int		mc_list_count;
531 #define BNXT_MAX_MC_ADDRS		16
532 
533 	uint32_t	flags;
534 #define BNXT_VNIC_FLAG_DEFAULT		0x01
535 #define BNXT_VNIC_FLAG_BD_STALL		0x02
536 #define BNXT_VNIC_FLAG_VLAN_STRIP	0x04
537 
538 	uint64_t	filter_id;
539 
540 	uint16_t	rss_id;
541 	uint32_t	rss_hash_type;
542 	uint8_t		rss_hash_key[HW_HASH_KEY_SIZE];
543 	struct iflib_dma_info rss_hash_key_tbl;
544 	struct iflib_dma_info	rss_grp_tbl;
545 	SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags;
546 	struct iflib_dma_info vlan_tag_list;
547 };
548 
549 struct bnxt_grp_info {
550 	uint16_t	stats_ctx;
551 	uint16_t	grp_id;
552 	uint16_t	rx_ring_id;
553 	uint16_t	cp_ring_id;
554 	uint16_t	ag_ring_id;
555 };
556 
557 struct bnxt_ring {
558 	uint64_t		paddr;
559 	vm_offset_t		doorbell;
560 	caddr_t			vaddr;
561 	struct bnxt_softc	*softc;
562 	uint32_t		ring_size;	/* Must be a power of two */
563 	uint16_t		id;		/* Logical ID */
564 	uint16_t		phys_id;
565 	uint16_t		idx;
566 	struct bnxt_full_tpa_start *tpa_start;
567 };
568 
569 struct bnxt_cp_ring {
570 	struct bnxt_ring	ring;
571 	struct if_irq		irq;
572 	uint32_t		cons;
573 	bool			v_bit;		/* Value of valid bit */
574 	struct ctx_hw_stats	*stats;
575 	uint32_t		stats_ctx_id;
576 	uint32_t		last_idx;	/* Used by RX rings only
577 						 * set to the last read pidx
578 						 */
579 	uint64_t 		int_count;
580 };
581 
582 struct bnxt_full_tpa_start {
583 	struct rx_tpa_start_cmpl low;
584 	struct rx_tpa_start_cmpl_hi high;
585 };
586 
587 /* All the version information for the part */
588 #define BNXT_VERSTR_SIZE	(3*3+2+1)	/* ie: "255.255.255\0" */
589 #define BNXT_NAME_SIZE		17
590 #define FW_VER_STR_LEN          32
591 #define BC_HWRM_STR_LEN         21
592 struct bnxt_ver_info {
593 	uint8_t		hwrm_if_major;
594 	uint8_t		hwrm_if_minor;
595 	uint8_t		hwrm_if_update;
596 	char		hwrm_if_ver[BNXT_VERSTR_SIZE];
597 	char		driver_hwrm_if_ver[BNXT_VERSTR_SIZE];
598 	char		mgmt_fw_ver[FW_VER_STR_LEN];
599 	char		netctrl_fw_ver[FW_VER_STR_LEN];
600 	char		roce_fw_ver[FW_VER_STR_LEN];
601 	char		fw_ver_str[FW_VER_STR_LEN];
602 	char		phy_ver[BNXT_VERSTR_SIZE];
603 	char		pkg_ver[64];
604 
605 	char		hwrm_fw_name[BNXT_NAME_SIZE];
606 	char		mgmt_fw_name[BNXT_NAME_SIZE];
607 	char		netctrl_fw_name[BNXT_NAME_SIZE];
608 	char		roce_fw_name[BNXT_NAME_SIZE];
609 	char		phy_vendor[BNXT_NAME_SIZE];
610 	char		phy_partnumber[BNXT_NAME_SIZE];
611 
612 	uint16_t	chip_num;
613 	uint8_t		chip_rev;
614 	uint8_t		chip_metal;
615 	uint8_t		chip_bond_id;
616 	uint8_t		chip_type;
617 
618 	uint8_t		hwrm_min_major;
619 	uint8_t		hwrm_min_minor;
620 	uint8_t		hwrm_min_update;
621 	uint64_t	fw_ver_code;
622 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)			\
623 	((uint64_t)(maj) << 48 | (uint64_t)(min) << 32 | (uint64_t)(bld) << 16 | (rsv))
624 #define BNXT_FW_MAJ(softc)	((softc)->ver_info->fw_ver_code >> 48)
625 #define BNXT_FW_MIN(softc)	(((softc)->ver_info->fw_ver_code >> 32) & 0xffff)
626 #define BNXT_FW_BLD(softc)	(((softc)->ver_info->fw_ver_code >> 16) & 0xffff)
627 #define BNXT_FW_RSV(softc)	(((softc)->ver_info->fw_ver_code) & 0xffff)
628 
629 	struct sysctl_ctx_list	ver_ctx;
630 	struct sysctl_oid	*ver_oid;
631 };
632 
633 struct bnxt_nvram_info {
634 	uint16_t	mfg_id;
635 	uint16_t	device_id;
636 	uint32_t	sector_size;
637 	uint32_t	size;
638 	uint32_t	reserved_size;
639 	uint32_t	available_size;
640 
641 	struct sysctl_ctx_list	nvm_ctx;
642 	struct sysctl_oid	*nvm_oid;
643 };
644 
645 struct bnxt_func_qcfg {
646 	uint16_t alloc_completion_rings;
647 	uint16_t alloc_tx_rings;
648 	uint16_t alloc_rx_rings;
649 	uint16_t alloc_vnics;
650 };
651 
652 struct bnxt_hw_lro {
653 	uint16_t enable;
654 	uint16_t is_mode_gro;
655 	uint16_t max_agg_segs;
656 	uint16_t max_aggs;
657 	uint32_t min_agg_len;
658 };
659 
660 /* The hardware supports certain page sizes.  Use the supported page sizes
661  * to allocate the rings.
662  */
663 #if (PAGE_SHIFT < 12)
664 #define BNXT_PAGE_SHIFT 12
665 #elif (PAGE_SHIFT <= 13)
666 #define BNXT_PAGE_SHIFT PAGE_SHIFT
667 #elif (PAGE_SHIFT < 16)
668 #define BNXT_PAGE_SHIFT 13
669 #else
670 #define BNXT_PAGE_SHIFT 16
671 #endif
672 
673 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
674 
675 #define MAX_CTX_PAGES	(BNXT_PAGE_SIZE / 8)
676 #define MAX_CTX_TOTAL_PAGES	(MAX_CTX_PAGES * MAX_CTX_PAGES)
677 
678 struct bnxt_ring_mem_info {
679 	int			nr_pages;
680 	int			page_size;
681 	uint16_t		flags;
682 #define BNXT_RMEM_VALID_PTE_FLAG        1
683 #define BNXT_RMEM_RING_PTE_FLAG         2
684 #define BNXT_RMEM_USE_FULL_PAGE_FLAG    4
685 	uint16_t		depth;
686 	struct bnxt_ctx_mem_type	*ctx_mem;
687 
688 	struct iflib_dma_info	*pg_arr;
689 	struct iflib_dma_info	pg_tbl;
690 
691 	int			vmem_size;
692 	void			**vmem;
693 };
694 
695 struct bnxt_ctx_pg_info {
696 	uint32_t		entries;
697 	uint32_t		nr_pages;
698 	struct iflib_dma_info   ctx_arr[MAX_CTX_PAGES];
699 	struct bnxt_ring_mem_info ring_mem;
700 	struct bnxt_ctx_pg_info **ctx_pg_tbl;
701 };
702 
703 #define BNXT_MAX_TQM_SP_RINGS		1
704 #define BNXT_MAX_TQM_FP_LEGACY_RINGS	8
705 #define BNXT_MAX_TQM_FP_RINGS		9
706 #define BNXT_MAX_TQM_LEGACY_RINGS	\
707 	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS)
708 #define BNXT_MAX_TQM_RINGS		\
709 	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
710 
711 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN	256
712 #define BNXT_BACKING_STORE_CFG_LEN		\
713 	sizeof(struct hwrm_func_backing_store_cfg_input)
714 
715 #define BNXT_SET_CTX_PAGE_ATTR(attr)					\
716 do {									\
717 	if (BNXT_PAGE_SIZE == 0x2000)					\
718 		attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_SRQ_PG_SIZE_PG_8K;	\
719 	else if (BNXT_PAGE_SIZE == 0x10000)				\
720 		attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_64K;	\
721 	else								\
722 		attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_4K;	\
723 } while (0)
724 
725 struct bnxt_ctx_mem_type {
726 	u16	type;
727 	u16	entry_size;
728 	u32	flags;
729 #define BNXT_CTX_MEM_TYPE_VALID HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID
730 	u32	instance_bmap;
731 	u8	init_value;
732 	u8	entry_multiple;
733 	u16	init_offset;
734 #define	BNXT_CTX_INIT_INVALID_OFFSET	0xffff
735 	u32	max_entries;
736 	u32	min_entries;
737 	u8	split_entry_cnt;
738 #define BNXT_MAX_SPLIT_ENTRY	4
739 	union {
740 		struct {
741 			u32	qp_l2_entries;
742 			u32	qp_qp1_entries;
743 		};
744 		u32	srq_l2_entries;
745 		u32	cq_l2_entries;
746 		u32	vnic_entries;
747 		struct {
748 			u32	mrav_av_entries;
749 			u32	mrav_num_entries_units;
750 		};
751 		u32	split[BNXT_MAX_SPLIT_ENTRY];
752 	};
753 	struct bnxt_ctx_pg_info	*pg_info;
754 };
755 
756 #define BNXT_CTX_QP	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP
757 #define BNXT_CTX_SRQ	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ
758 #define BNXT_CTX_CQ	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ
759 #define BNXT_CTX_VNIC	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC
760 #define BNXT_CTX_STAT	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT
761 #define BNXT_CTX_STQM	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING
762 #define BNXT_CTX_FTQM	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING
763 #define BNXT_CTX_MRAV	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV
764 #define BNXT_CTX_TIM	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM
765 #define BNXT_CTX_TKC	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC
766 #define BNXT_CTX_RKC	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC
767 #define BNXT_CTX_MTQM	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING
768 #define BNXT_CTX_SQDBS	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW
769 #define BNXT_CTX_RQDBS	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW
770 #define BNXT_CTX_SRQDBS	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW
771 #define BNXT_CTX_CQDBS	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW
772 #define BNXT_CTX_QTKC	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC
773 #define BNXT_CTX_QRKC	HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC
774 #define BNXT_CTX_MAX	(BNXT_CTX_TIM + 1)
775 
776 struct bnxt_ctx_mem_info {
777 	u8	tqm_fp_rings_count;
778 
779 	u32	flags;
780 	#define BNXT_CTX_FLAG_INITED	0x01
781 	struct bnxt_ctx_mem_type	ctx_arr[BNXT_CTX_MAX];
782 };
783 
784 struct bnxt_hw_resc {
785 	uint16_t	min_rsscos_ctxs;
786 	uint16_t	max_rsscos_ctxs;
787 	uint16_t	min_cp_rings;
788 	uint16_t	max_cp_rings;
789 	uint16_t	resv_cp_rings;
790 	uint16_t	min_tx_rings;
791 	uint16_t	max_tx_rings;
792 	uint16_t	resv_tx_rings;
793 	uint16_t	max_tx_sch_inputs;
794 	uint16_t	min_rx_rings;
795 	uint16_t	max_rx_rings;
796 	uint16_t	resv_rx_rings;
797 	uint16_t	min_hw_ring_grps;
798 	uint16_t	max_hw_ring_grps;
799 	uint16_t	resv_hw_ring_grps;
800 	uint16_t	min_l2_ctxs;
801 	uint16_t	max_l2_ctxs;
802 	uint16_t	min_vnics;
803 	uint16_t	max_vnics;
804 	uint16_t	resv_vnics;
805 	uint16_t	min_stat_ctxs;
806 	uint16_t	max_stat_ctxs;
807 	uint16_t	resv_stat_ctxs;
808 	uint16_t	max_nqs;
809 	uint16_t	max_irqs;
810 	uint16_t	resv_irqs;
811 };
812 
813 enum bnxt_type_ets {
814 	BNXT_TYPE_ETS_TSA = 0,
815 	BNXT_TYPE_ETS_PRI2TC,
816 	BNXT_TYPE_ETS_TCBW,
817 	BNXT_TYPE_ETS_MAX
818 };
819 
820 static const char *const BNXT_ETS_TYPE_STR[] = {
821 	"tsa",
822 	"pri2tc",
823 	"tcbw",
824 };
825 
826 static const char *const BNXT_ETS_HELP_STR[] = {
827 	"X is 1 (strict),  0 (ets)",
828 	"TC values for pri 0 to 7",
829 	"TC BW values for pri 0 to 7, Sum should be 100",
830 };
831 
832 #define BNXT_HWRM_MAX_REQ_LEN		(softc->hwrm_max_req_len)
833 
834 struct bnxt_softc_list {
835 	SLIST_ENTRY(bnxt_softc_list) next;
836 	struct bnxt_softc *softc;
837 };
838 
839 #ifndef BIT_ULL
840 #define BIT_ULL(nr)		(1ULL << (nr))
841 #endif
842 
843 struct bnxt_aux_dev {
844 	struct auxiliary_device aux_dev;
845 	struct bnxt_en_dev *edev;
846 	int id;
847 };
848 
849 struct bnxt_msix_tbl {
850 	uint32_t entry;
851 	uint32_t vector;
852 };
853 
854 enum bnxt_health_severity {
855 	SEVERITY_NORMAL = 0,
856 	SEVERITY_WARNING,
857 	SEVERITY_RECOVERABLE,
858 	SEVERITY_FATAL,
859 };
860 
861 enum bnxt_health_remedy {
862 	REMEDY_DEVLINK_RECOVER,
863 	REMEDY_POWER_CYCLE_DEVICE,
864 	REMEDY_POWER_CYCLE_HOST,
865 	REMEDY_FW_UPDATE,
866 	REMEDY_HW_REPLACE,
867 };
868 
869 struct bnxt_fw_health {
870 	u32 flags;
871 	u32 polling_dsecs;
872 	u32 master_func_wait_dsecs;
873 	u32 normal_func_wait_dsecs;
874 	u32 post_reset_wait_dsecs;
875 	u32 post_reset_max_wait_dsecs;
876 	u32 regs[4];
877 	u32 mapped_regs[4];
878 #define BNXT_FW_HEALTH_REG		0
879 #define BNXT_FW_HEARTBEAT_REG		1
880 #define BNXT_FW_RESET_CNT_REG		2
881 #define BNXT_FW_RESET_INPROG_REG	3
882 	u32 fw_reset_inprog_reg_mask;
883 	u32 last_fw_heartbeat;
884 	u32 last_fw_reset_cnt;
885 	u8 enabled:1;
886 	u8 primary:1;
887 	u8 status_reliable:1;
888 	u8 resets_reliable:1;
889 	u8 tmr_multiplier;
890 	u8 tmr_counter;
891 	u8 fw_reset_seq_cnt;
892 	u32 fw_reset_seq_regs[16];
893 	u32 fw_reset_seq_vals[16];
894 	u32 fw_reset_seq_delay_msec[16];
895 	u32 echo_req_data1;
896 	u32 echo_req_data2;
897 	struct devlink_health_reporter	*fw_reporter;
898 	struct mutex lock;
899 	enum bnxt_health_severity severity;
900 	enum bnxt_health_remedy remedy;
901 	u32 arrests;
902 	u32 discoveries;
903 	u32 survivals;
904 	u32 fatalities;
905 	u32 diagnoses;
906 };
907 
908 #define BNXT_FW_HEALTH_REG_TYPE_MASK	3
909 #define BNXT_FW_HEALTH_REG_TYPE_CFG	0
910 #define BNXT_FW_HEALTH_REG_TYPE_GRC	1
911 #define BNXT_FW_HEALTH_REG_TYPE_BAR0	2
912 #define BNXT_FW_HEALTH_REG_TYPE_BAR1	3
913 
914 #define BNXT_FW_HEALTH_REG_TYPE(reg)	((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
915 #define BNXT_FW_HEALTH_REG_OFF(reg)	((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
916 
917 #define BNXT_FW_HEALTH_WIN_BASE		0x3000
918 #define BNXT_FW_HEALTH_WIN_MAP_OFF	8
919 
920 #define BNXT_FW_HEALTH_WIN_OFF(reg)	(BNXT_FW_HEALTH_WIN_BASE +	\
921 					 ((reg) & BNXT_GRC_OFFSET_MASK))
922 
923 #define BNXT_FW_STATUS_HEALTH_MSK	0xffff
924 #define BNXT_FW_STATUS_HEALTHY		0x8000
925 #define BNXT_FW_STATUS_SHUTDOWN		0x100000
926 #define BNXT_FW_STATUS_RECOVERING	0x400000
927 
928 #define BNXT_FW_IS_HEALTHY(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
929 					 BNXT_FW_STATUS_HEALTHY)
930 
931 #define BNXT_FW_IS_BOOTING(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
932 					 BNXT_FW_STATUS_HEALTHY)
933 
934 #define BNXT_FW_IS_ERR(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
935 					 BNXT_FW_STATUS_HEALTHY)
936 
937 #define BNXT_FW_IS_RECOVERING(sts)	(BNXT_FW_IS_ERR(sts) &&		       \
938 					 ((sts) & BNXT_FW_STATUS_RECOVERING))
939 
940 #define BNXT_FW_RETRY			5
941 #define BNXT_FW_IF_RETRY		10
942 #define BNXT_FW_SLOT_RESET_RETRY	4
943 
944 #define BNXT_GRCPF_REG_CHIMP_COMM		0x0
945 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x100
946 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT		0x400
947 #define BNXT_GRCPF_REG_SYNC_TIME		0x480
948 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ		0x488
949 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_MSK	0xffffffUL
950 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_SFT	0
951 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_MSK	0x1f000000UL
952 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_SFT	24
953 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_MSK	0x20000000UL
954 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_SFT	29
955 
956 #define BNXT_GRC_REG_STATUS_P5			0x520
957 
958 #define BNXT_GRCPF_REG_KONG_COMM		0xA00
959 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER	0xB00
960 
961 #define BNXT_CAG_REG_LEGACY_INT_STATUS		0x4014
962 #define BNXT_CAG_REG_BASE			0x300000
963 
964 #define BNXT_GRC_REG_CHIP_NUM			0x48
965 #define BNXT_GRC_REG_BASE			0x260000
966 
967 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER		0x640180c
968 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER		0x6401810
969 
970 #define BNXT_GRC_BASE_MASK			0xfffff000
971 #define BNXT_GRC_OFFSET_MASK			0x00000ffc
972 struct bnxt_softc {
973 	device_t	dev;
974 	if_ctx_t	ctx;
975 	if_softc_ctx_t	scctx;
976 	if_shared_ctx_t	sctx;
977 	if_t ifp;
978 	uint32_t	domain;
979 	uint32_t	bus;
980 	uint32_t	slot;
981 	uint32_t	function;
982 	uint32_t	dev_fn;
983 	struct ifmedia	*media;
984 	struct bnxt_ctx_mem_info *ctx_mem;
985 	struct bnxt_hw_resc hw_resc;
986 	struct bnxt_softc_list list;
987 
988 	struct bnxt_bar_info	hwrm_bar;
989 	struct bnxt_bar_info	doorbell_bar;
990 	struct bnxt_link_info	link_info;
991 #define BNXT_FLAG_VF				0x0001
992 #define BNXT_FLAG_NPAR				0x0002
993 #define BNXT_FLAG_WOL_CAP			0x0004
994 #define BNXT_FLAG_SHORT_CMD			0x0008
995 #define BNXT_FLAG_FW_CAP_NEW_RM			0x0010
996 #define BNXT_FLAG_CHIP_P5			0x0020
997 #define BNXT_FLAG_TPA				0x0040
998 #define BNXT_FLAG_FW_CAP_EXT_STATS		0x0080
999 #define BNXT_FLAG_MULTI_HOST			0x0100
1000 #define BNXT_FLAG_MULTI_ROOT			0x0200
1001 #define BNXT_FLAG_ROCEV1_CAP			0x0400
1002 #define BNXT_FLAG_ROCEV2_CAP			0x0800
1003 #define BNXT_FLAG_ROCE_CAP			(BNXT_FLAG_ROCEV1_CAP | BNXT_FLAG_ROCEV2_CAP)
1004 	uint32_t		flags;
1005 #define BNXT_STATE_LINK_CHANGE  (0)
1006 #define BNXT_STATE_MAX		(BNXT_STATE_LINK_CHANGE + 1)
1007 	bitstr_t 		*state_bv;
1008 
1009 	uint32_t		total_irqs;
1010 	struct bnxt_msix_tbl	*irq_tbl;
1011 
1012 	struct bnxt_func_info	func;
1013 	struct bnxt_func_qcfg	fn_qcfg;
1014 	struct bnxt_pf_info	pf;
1015 	struct bnxt_vf_info	vf;
1016 
1017 	uint16_t		hwrm_cmd_seq;
1018 	uint32_t		hwrm_cmd_timeo;	/* milliseconds */
1019 	struct iflib_dma_info	hwrm_cmd_resp;
1020 	struct iflib_dma_info	hwrm_short_cmd_req_addr;
1021 	/* Interrupt info for HWRM */
1022 	struct if_irq		irq;
1023 	struct mtx		hwrm_lock;
1024 	uint16_t		hwrm_max_req_len;
1025 	uint16_t		hwrm_max_ext_req_len;
1026 	uint32_t		hwrm_spec_code;
1027 
1028 #define BNXT_MAX_QUEUE	8
1029 	uint8_t			max_tc;
1030 	uint8_t			max_lltc;
1031 	struct bnxt_queue_info  tx_q_info[BNXT_MAX_QUEUE];
1032 	struct bnxt_queue_info  rx_q_info[BNXT_MAX_QUEUE];
1033 	uint8_t			tc_to_qidx[BNXT_MAX_QUEUE];
1034 	uint8_t			tx_q_ids[BNXT_MAX_QUEUE];
1035 	uint8_t			rx_q_ids[BNXT_MAX_QUEUE];
1036 	uint8_t			tx_max_q;
1037 	uint8_t			rx_max_q;
1038 	uint8_t			is_asym_q;
1039 
1040 	struct bnxt_ieee_ets	*ieee_ets;
1041 	struct bnxt_ieee_pfc    *ieee_pfc;
1042 	uint8_t			dcbx_cap;
1043 	uint8_t			default_pri;
1044 	uint8_t			max_dscp_value;
1045 
1046 	uint64_t		admin_ticks;
1047 	struct iflib_dma_info	hw_rx_port_stats;
1048 	struct iflib_dma_info	hw_tx_port_stats;
1049 	struct rx_port_stats	*rx_port_stats;
1050 	struct tx_port_stats	*tx_port_stats;
1051 
1052 	struct iflib_dma_info	hw_tx_port_stats_ext;
1053 	struct iflib_dma_info	hw_rx_port_stats_ext;
1054 	struct tx_port_stats_ext *tx_port_stats_ext;
1055 	struct rx_port_stats_ext *rx_port_stats_ext;
1056 
1057 	uint16_t		fw_rx_stats_ext_size;
1058 	uint16_t		fw_tx_stats_ext_size;
1059 	uint16_t		hw_ring_stats_size;
1060 
1061 	uint8_t			tx_pri2cos_idx[8];
1062 	uint8_t			rx_pri2cos_idx[8];
1063 	bool			pri2cos_valid;
1064 
1065 	uint64_t		tx_bytes_pri[8];
1066 	uint64_t		tx_packets_pri[8];
1067 	uint64_t		rx_bytes_pri[8];
1068 	uint64_t		rx_packets_pri[8];
1069 
1070 	uint8_t			port_count;
1071 	int			num_cp_rings;
1072 
1073 	struct bnxt_cp_ring	*nq_rings;
1074 
1075 	struct bnxt_ring	*tx_rings;
1076 	struct bnxt_cp_ring	*tx_cp_rings;
1077 	struct iflib_dma_info	tx_stats[BNXT_MAX_NUM_QUEUES];
1078 	int			ntxqsets;
1079 
1080 	struct bnxt_vnic_info	vnic_info;
1081 	struct bnxt_ring	*ag_rings;
1082 	struct bnxt_ring	*rx_rings;
1083 	struct bnxt_cp_ring	*rx_cp_rings;
1084 	struct bnxt_grp_info	*grp_info;
1085 	struct iflib_dma_info	rx_stats[BNXT_MAX_NUM_QUEUES];
1086 	int			nrxqsets;
1087 	uint16_t		rx_buf_size;
1088 
1089 	struct bnxt_cp_ring	def_cp_ring;
1090 	struct bnxt_cp_ring	def_nq_ring;
1091 	struct iflib_dma_info	def_cp_ring_mem;
1092 	struct iflib_dma_info	def_nq_ring_mem;
1093 	struct grouptask	def_cp_task;
1094 	int			db_size;
1095 	int			legacy_db_size;
1096 	struct bnxt_doorbell_ops db_ops;
1097 
1098 	struct sysctl_ctx_list	hw_stats;
1099 	struct sysctl_oid	*hw_stats_oid;
1100 	struct sysctl_ctx_list	hw_lro_ctx;
1101 	struct sysctl_oid	*hw_lro_oid;
1102 	struct sysctl_ctx_list	flow_ctrl_ctx;
1103 	struct sysctl_oid	*flow_ctrl_oid;
1104 	struct sysctl_ctx_list	dcb_ctx;
1105 	struct sysctl_oid	*dcb_oid;
1106 
1107 	struct bnxt_ver_info	*ver_info;
1108 	struct bnxt_nvram_info	*nvm_info;
1109 	bool wol;
1110 	bool is_dev_init;
1111 	struct bnxt_hw_lro	hw_lro;
1112 	uint8_t wol_filter_id;
1113 	uint16_t		rx_coal_usecs;
1114 	uint16_t		rx_coal_usecs_irq;
1115 	uint16_t               	rx_coal_frames;
1116 	uint16_t               	rx_coal_frames_irq;
1117 	uint16_t               	tx_coal_usecs;
1118 	uint16_t               	tx_coal_usecs_irq;
1119 	uint16_t               	tx_coal_frames;
1120 	uint16_t		tx_coal_frames_irq;
1121 
1122 #define BNXT_USEC_TO_COAL_TIMER(x)      ((x) * 25 / 2)
1123 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1124 #define BNXT_MIN_STATS_COAL_TICKS         250000
1125 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1126 
1127 	uint64_t		fw_cap;
1128 	#define BNXT_FW_CAP_SHORT_CMD			BIT_ULL(0)
1129 	#define BNXT_FW_CAP_LLDP_AGENT			BIT_ULL(1)
1130 	#define BNXT_FW_CAP_DCBX_AGENT			BIT_ULL(2)
1131 	#define BNXT_FW_CAP_NEW_RM			BIT_ULL(3)
1132 	#define BNXT_FW_CAP_IF_CHANGE			BIT_ULL(4)
1133 	#define BNXT_FW_CAP_LINK_ADMIN			BIT_ULL(5)
1134 	#define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED	BIT_ULL(6)
1135 	#define BNXT_FW_CAP_KONG_MB_CHNL		BIT_ULL(7)
1136 	#define BNXT_FW_CAP_ADMIN_MTU			BIT_ULL(8)
1137 	#define BNXT_FW_CAP_ADMIN_PF			BIT_ULL(9)
1138 	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		BIT_ULL(10)
1139 	#define BNXT_FW_CAP_TRUSTED_VF			BIT_ULL(11)
1140 	#define BNXT_FW_CAP_VF_VNIC_NOTIFY		BIT_ULL(12)
1141 	#define BNXT_FW_CAP_ERROR_RECOVERY		BIT_ULL(13)
1142 	#define BNXT_FW_CAP_PKG_VER			BIT_ULL(14)
1143 	#define BNXT_FW_CAP_CFA_ADV_FLOW		BIT_ULL(15)
1144 	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	BIT_ULL(16)
1145 	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	BIT_ULL(17)
1146 	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		BIT_ULL(18)
1147 	#define BNXT_FW_CAP_SECURE_MODE			BIT_ULL(19)
1148 	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		BIT_ULL(20)
1149 	#define BNXT_FW_CAP_HOT_RESET			BIT_ULL(21)
1150 	#define BNXT_FW_CAP_CRASHDUMP			BIT_ULL(23)
1151 	#define BNXT_FW_CAP_VLAN_RX_STRIP		BIT_ULL(24)
1152 	#define BNXT_FW_CAP_VLAN_TX_INSERT		BIT_ULL(25)
1153 	#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED	BIT_ULL(26)
1154 	#define BNXT_FW_CAP_CFA_EEM			BIT_ULL(27)
1155 	#define BNXT_FW_CAP_DBG_QCAPS			BIT_ULL(29)
1156 	#define BNXT_FW_CAP_RING_MONITOR		BIT_ULL(30)
1157 	#define BNXT_FW_CAP_ECN_STATS			BIT_ULL(31)
1158 	#define BNXT_FW_CAP_TRUFLOW			BIT_ULL(32)
1159 	#define BNXT_FW_CAP_VF_CFG_FOR_PF		BIT_ULL(33)
1160 	#define BNXT_FW_CAP_PTP_PPS			BIT_ULL(34)
1161 	#define BNXT_FW_CAP_HOT_RESET_IF		BIT_ULL(35)
1162 	#define BNXT_FW_CAP_LIVEPATCH			BIT_ULL(36)
1163 	#define BNXT_FW_CAP_NPAR_1_2			BIT_ULL(37)
1164 	#define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA		BIT_ULL(38)
1165 	#define BNXT_FW_CAP_PTP_RTC			BIT_ULL(39)
1166 	#define	BNXT_FW_CAP_TRUFLOW_EN			BIT_ULL(40)
1167 	#define BNXT_TRUFLOW_EN(bp)	((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN)
1168 	#define BNXT_FW_CAP_RX_ALL_PKT_TS		BIT_ULL(41)
1169 	#define BNXT_FW_CAP_BACKING_STORE_V2		BIT_ULL(42)
1170 	#define BNXT_FW_CAP_DBR_SUPPORTED		BIT_ULL(43)
1171 	#define BNXT_FW_CAP_GENERIC_STATS		BIT_ULL(44)
1172 	#define BNXT_FW_CAP_DBR_PACING_SUPPORTED	BIT_ULL(45)
1173 	#define BNXT_FW_CAP_PTP_PTM			BIT_ULL(46)
1174 	#define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO	BIT_ULL(47)
1175 	#define BNXT_FW_CAP_ENABLE_RDMA_SRIOV		BIT_ULL(48)
1176 	#define BNXT_FW_CAP_RSS_TCAM			BIT_ULL(49)
1177 	uint32_t		lpi_tmr_lo;
1178 	uint32_t		lpi_tmr_hi;
1179 	/* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
1180 	uint16_t		phy_flags;
1181 #define BNXT_PHY_FL_EEE_CAP             HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED
1182 #define BNXT_PHY_FL_EXT_LPBK            HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED
1183 #define BNXT_PHY_FL_AN_PHY_LPBK         HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED
1184 #define BNXT_PHY_FL_SHARED_PORT_CFG     HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED
1185 #define BNXT_PHY_FL_PORT_STATS_NO_RESET HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
1186 #define BNXT_PHY_FL_NO_PHY_LPBK         HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
1187 #define BNXT_PHY_FL_FW_MANAGED_LKDN     HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN
1188 #define BNXT_PHY_FL_NO_FCS              HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS
1189 #define BNXT_PHY_FL_NO_PAUSE            (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED << 8)
1190 #define BNXT_PHY_FL_NO_PFC              (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED << 8)
1191 #define BNXT_PHY_FL_BANK_SEL            (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED << 8)
1192 	struct bnxt_aux_dev     *aux_dev;
1193 	struct net_device	*net_dev;
1194 	struct mtx		en_ops_lock;
1195 	uint8_t			port_partition_type;
1196 	struct bnxt_en_dev	*edev;
1197 	unsigned long		state;
1198 #define BNXT_STATE_OPEN			0
1199 #define BNXT_STATE_IN_SP_TASK		1
1200 #define BNXT_STATE_READ_STATS		2
1201 #define BNXT_STATE_FW_RESET_DET 	3
1202 #define BNXT_STATE_IN_FW_RESET		4
1203 #define BNXT_STATE_ABORT_ERR		5
1204 #define BNXT_STATE_FW_FATAL_COND	6
1205 #define BNXT_STATE_DRV_REGISTERED	7
1206 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN	8
1207 #define BNXT_STATE_NAPI_DISABLED	9
1208 #define BNXT_STATE_L2_FILTER_RETRY	10
1209 #define BNXT_STATE_FW_ACTIVATE		11
1210 #define BNXT_STATE_RECOVER		12
1211 #define BNXT_STATE_FW_NON_FATAL_COND	13
1212 #define BNXT_STATE_FW_ACTIVATE_RESET	14
1213 #define BNXT_STATE_HALF_OPEN		15
1214 #define BNXT_NO_FW_ACCESS(bp)		\
1215 	test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state)
1216 	struct pci_dev			*pdev;
1217 
1218 	struct work_struct	sp_task;
1219 	unsigned long		sp_event;
1220 #define BNXT_RX_MASK_SP_EVENT		0
1221 #define BNXT_RX_NTP_FLTR_SP_EVENT	1
1222 #define BNXT_LINK_CHNG_SP_EVENT		2
1223 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT	3
1224 #define BNXT_VXLAN_ADD_PORT_SP_EVENT	4
1225 #define BNXT_VXLAN_DEL_PORT_SP_EVENT	5
1226 #define BNXT_RESET_TASK_SP_EVENT	6
1227 #define BNXT_RST_RING_SP_EVENT		7
1228 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT	8
1229 #define BNXT_PERIODIC_STATS_SP_EVENT	9
1230 #define BNXT_HWRM_PORT_MODULE_SP_EVENT	10
1231 #define BNXT_RESET_TASK_SILENT_SP_EVENT	11
1232 #define BNXT_GENEVE_ADD_PORT_SP_EVENT	12
1233 #define BNXT_GENEVE_DEL_PORT_SP_EVENT	13
1234 #define BNXT_LINK_SPEED_CHNG_SP_EVENT	14
1235 #define BNXT_FLOW_STATS_SP_EVENT	15
1236 #define BNXT_UPDATE_PHY_SP_EVENT	16
1237 #define BNXT_RING_COAL_NOW_SP_EVENT	17
1238 #define BNXT_FW_RESET_NOTIFY_SP_EVENT	18
1239 #define BNXT_FW_EXCEPTION_SP_EVENT	19
1240 #define BNXT_VF_VNIC_CHANGE_SP_EVENT	20
1241 #define BNXT_LINK_CFG_CHANGE_SP_EVENT	21
1242 #define BNXT_PTP_CURRENT_TIME_EVENT	22
1243 #define BNXT_FW_ECHO_REQUEST_SP_EVENT	23
1244 #define BNXT_VF_CFG_CHNG_SP_EVENT	24
1245 
1246 	struct delayed_work	fw_reset_task;
1247 	int			fw_reset_state;
1248 #define BNXT_FW_RESET_STATE_POLL_VF	1
1249 #define BNXT_FW_RESET_STATE_RESET_FW	2
1250 #define BNXT_FW_RESET_STATE_ENABLE_DEV	3
1251 #define BNXT_FW_RESET_STATE_POLL_FW	4
1252 #define BNXT_FW_RESET_STATE_OPENING	5
1253 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN	6
1254 	u16			fw_reset_min_dsecs;
1255 #define BNXT_DFLT_FW_RST_MIN_DSECS	20
1256 	u16			fw_reset_max_dsecs;
1257 #define BNXT_DFLT_FW_RST_MAX_DSECS	60
1258 	unsigned long		fw_reset_timestamp;
1259 
1260 	struct bnxt_fw_health	*fw_health;
1261 };
1262 
1263 struct bnxt_filter_info {
1264 	STAILQ_ENTRY(bnxt_filter_info) next;
1265 	uint64_t	fw_l2_filter_id;
1266 #define INVALID_MAC_INDEX ((uint16_t)-1)
1267 	uint16_t	mac_index;
1268 
1269 	/* Filter Characteristics */
1270 	uint32_t	flags;
1271 	uint32_t	enables;
1272 	uint8_t		l2_addr[ETHER_ADDR_LEN];
1273 	uint8_t		l2_addr_mask[ETHER_ADDR_LEN];
1274 	uint16_t	l2_ovlan;
1275 	uint16_t	l2_ovlan_mask;
1276 	uint16_t	l2_ivlan;
1277 	uint16_t	l2_ivlan_mask;
1278 	uint8_t		t_l2_addr[ETHER_ADDR_LEN];
1279 	uint8_t		t_l2_addr_mask[ETHER_ADDR_LEN];
1280 	uint16_t	t_l2_ovlan;
1281 	uint16_t	t_l2_ovlan_mask;
1282 	uint16_t	t_l2_ivlan;
1283 	uint16_t	t_l2_ivlan_mask;
1284 	uint8_t		tunnel_type;
1285 	uint16_t	mirror_vnic_id;
1286 	uint32_t	vni;
1287 	uint8_t		pri_hint;
1288 	uint64_t	l2_filter_id_hint;
1289 };
1290 
1291 #define I2C_DEV_ADDR_A0                 0xa0
1292 #define BNXT_MAX_PHY_I2C_RESP_SIZE      64
1293 
1294 /* Function declarations */
1295 void bnxt_report_link(struct bnxt_softc *softc);
1296 bool bnxt_check_hwrm_version(struct bnxt_softc *softc);
1297 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name);
1298 int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *bp, uint16_t i2c_addr,
1299     uint16_t page_number, uint8_t bank, bool bank_sel_en, uint16_t start_addr,
1300     uint16_t data_length, uint8_t *buf);
1301 void bnxt_dcb_init(struct bnxt_softc *softc);
1302 void bnxt_dcb_free(struct bnxt_softc *softc);
1303 uint8_t bnxt_dcb_setdcbx(struct bnxt_softc *softc, uint8_t mode);
1304 uint8_t bnxt_dcb_getdcbx(struct bnxt_softc *softc);
1305 int bnxt_dcb_ieee_getets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets);
1306 int bnxt_dcb_ieee_setets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets);
1307 uint8_t get_phy_type(struct bnxt_softc *softc);
1308 int bnxt_dcb_ieee_getpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc);
1309 int bnxt_dcb_ieee_setpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc);
1310 int bnxt_dcb_ieee_setapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app);
1311 int bnxt_dcb_ieee_delapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app);
1312 int bnxt_dcb_ieee_listapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app, int *num_inputs);
1313 
1314 #endif /* _BNXT_H */
1315