Searched refs:DefInstr (Results 1 – 9 of 9) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineCombiner.cpp | 154 MachineInstr *DefInstr = nullptr; in getOperandDef() local 157 DefInstr = MRI->getUniqueVRegDef(MO.getReg()); in getOperandDef() 159 if (DefInstr && DefInstr->isPHI()) in getOperandDef() 160 DefInstr = nullptr; in getOperandDef() 161 return DefInstr; in getOperandDef() 231 MachineInstr *DefInstr = InsInstrs[II->second]; in getDepth() local 232 assert(DefInstr && in getDepth() 240 MachineInstr *DefInstr = getOperandDef(MO); in getDepth() local 243 DefInstr->getParent() == &MBB)) { in getDepth() 245 if (!isTransientMI(DefInstr)) in getDepth() [all …]
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H A D | LiveRangeShrink.cpp | 201 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg); in runOnMachineFunction() local 202 if (!TII.isCopyInstr(DefInstr)) in runOnMachineFunction() 204 Insert = FindDominatedInstruction(DefInstr, Insert, IOM); in runOnMachineFunction()
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H A D | MachineUniformityAnalysis.cpp | 145 auto *DefInstr = Def->getParent(); in isDivergentUse() local 147 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr); in isDivergentUse()
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H A D | ScheduleDAGInstrs.cpp | 317 MachineInstr *DefInstr = DefSU->getInstr(); in addPhysRegDeps() local 318 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); in addPhysRegDeps() 324 SchedModel.computeOutputLatency(MI, OperIdx, DefInstr)); in addPhysRegDeps()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILowerControlFlow.cpp | 741 MachineInstr *DefInstr = MRI->getVRegDef(InputReg); in lowerInitExec() local 742 assert(DefInstr && DefInstr->isCopy()); in lowerInitExec() 743 if (DefInstr->getParent() == MBB) { in lowerInitExec() 744 if (DefInstr != FirstMI) { in lowerInitExec() 747 DefInstr->removeFromParent(); in lowerInitExec() 748 MBB->insert(FirstMI, DefInstr); in lowerInitExec() 750 LIS->handleMove(*DefInstr); in lowerInitExec()
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H A D | AMDGPUMachineCFGStructurizer.cpp | 327 MachineInstr *DefInstr, const MachineRegisterInfo *MRI, 331 MachineInstr *DefInstr, 675 MachineInstr *DefInstr, in storeLiveOutReg() argument 702 if ((&(*MII)) == DefInstr) { in storeLiveOutReg() 715 MachineInstr *DefInstr, in storeLiveOutRegRegion() argument 1930 MachineInstr *DefInstr = getDefInstr(SourceReg); in insertChainedPHI() local 1931 if (DefInstr->isPHI() && DefInstr->getParent() == CodeBB && IsSingleBB) { in insertChainedPHI() 1940 storePHILinearizationInfoDest(DestReg, *DefInstr); in insertChainedPHI() 1944 DefInstr->eraseFromParent(); in insertChainedPHI() 1947 if (IsSingleBB && DefInstr->getParent() == InnerRegion->getEntry()) { in insertChainedPHI()
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H A D | SIPeepholeSDWA.cpp | 292 MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg()); in findSingleRegDef() local 293 if (!DefInstr) in findSingleRegDef() 296 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | UniformityAnalysis.cpp | 99 if (const auto *DefInstr = dyn_cast<Instruction>(V)) { in isDivergentUse() local 101 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr); in isDivergentUse()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
H A D | SPIRVBuiltins.cpp | 1498 MachineInstr *DefInstr = MRI->getUniqueVRegDef(GlobalWorkSize); in buildNDRange() local 1499 assert(DefInstr && isSpvIntrinsic(*DefInstr, Intrinsic::spv_gep) && in buildNDRange() 1500 DefInstr->getOperand(3).isReg()); in buildNDRange() 1501 Register GWSPtr = DefInstr->getOperand(3).getReg(); in buildNDRange()
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