/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRExpandPseudoInsts.cpp | 1162 .addReg(DstReg, in expand() 1313 .addReg(DstReg) in expand() 1324 .addReg(DstReg) in expand() 1506 .addReg(DstReg, RegState::Kill) in expandROLBRd() 1551 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg); in expand() 1554 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7); in expand() 2232 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd() 2238 .addReg(DstReg, RegState::Kill) in expandLSLB7Rd() 2282 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd() 2283 .addReg(DstReg, RegState::Kill) in expandLSRB7Rd() [all …]
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H A D | AVRRegisterInfo.cpp | 113 Register DstReg) { in foldFrameOffset() argument 124 if (DstReg != MI.getOperand(0).getReg()) { in foldFrameOffset() 169 Register DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 170 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); in eliminateFrameIndex() 174 BuildMI(MBB, MI, dl, TII.get(AVR::MOVWRdRr), DstReg) in eliminateFrameIndex() 178 splitReg(DstReg, DstLoReg, DstHiReg); in eliminateFrameIndex() 201 foldFrameOffset(II, Offset, DstReg); in eliminateFrameIndex() 204 switch (DstReg) { in eliminateFrameIndex() 222 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg) in eliminateFrameIndex() 223 .addReg(DstReg, RegState::Kill) in eliminateFrameIndex()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYInstrInfo.cpp | 233 Register DstReg; in movImm() local 250 .addReg(DstReg) in movImm() 266 .addReg(DstReg) in movImm() 271 .addReg(DstReg) in movImm() 279 .addReg(DstReg) in movImm() 284 .addReg(DstReg) in movImm() 288 .addReg(DstReg) in movImm() 301 .addReg(DstReg) in movImm() 310 .addReg(DstReg) in movImm() 319 .addReg(DstReg) in movImm() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCDuplexInfo.cpp | 201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup() 279 if (Hexagon::R31 == DstReg) in getDuplexCandidateGroup() 419 if (DstReg == SrcReg) { in getDuplexCandidateGroup() 435 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) && in getDuplexCandidateGroup() 483 if (Hexagon::P0 == DstReg && in getDuplexCandidateGroup() 536 unsigned DstReg, SrcReg; in subInstWouldBeExtended() local [all …]
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H A D | HexagonMCCompound.cpp | 81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local 97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup() 100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup() 111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup() 113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup() 123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup() 125 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getCompoundCandidateGroup() 133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup() 136 HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) in getCompoundCandidateGroup() 142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup() [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 78 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt() 91 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt() 104 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt() 129 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt() 166 UpdatedDefs.push_back(DstReg); in tryCombineZExt() 179 UpdatedDefs.push_back(DstReg); in tryCombineZExt() 200 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt() 222 UpdatedDefs.push_back(DstReg); in tryCombineSExt() 337 UpdatedDefs.push_back(DstReg); in tryCombineTrunc() 554 UpdatedDefs.push_back(DstReg); in replaceRegOrBuildCopy() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILowerI1Copies.cpp | 479 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1() 560 markAsLaneMask(DstReg); in lowerPhis() 575 PhiRegisters.insert(DstReg); in lowerPhis() 593 SSAUpdater.Initialize(DstReg); in lowerPhis() 642 if (NewReg != DstReg) { in lowerPhis() 643 replaceDstReg(NewReg, DstReg, &MBB); in lowerPhis() 667 if (!isVreg1(DstReg)) in lowerCopiesToI1() 672 if (MRI->use_empty(DstReg)) { in lowerCopiesToI1() 679 markAsLaneMask(DstReg); in lowerCopiesToI1() 712 SSAUpdater.Initialize(DstReg); in lowerCopiesToI1() [all …]
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H A D | R600ExpandSpecialInstrs.cpp | 126 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local 127 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction() 130 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction() 196 Register DstReg = in runOnMachineFunction() local 226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction() 230 Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction() 231 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction() 232 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction() 252 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
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H A D | SIFixSGPRCopies.cpp | 192 Register DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses() local 228 Register DstReg = MI.getOperand(0).getReg(); in tryChangeVGPRtoSGPRinCopy() local 247 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy() 270 Register DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence() local 274 if (!MRI.hasOneUse(DstReg)) in foldVGPRCopyIntoRegSequence() 299 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence() 861 TII->get(MoveOp), DstReg) in tryMoveVGPRConstToSGPR() 865 MaybeVGPRConstMO.setReg(DstReg); in tryMoveVGPRConstToSGPR() 873 if (!DstReg.isVirtual()) { in lowerSpecialCase() 878 if (DstReg == AMDGPU::M0 && in lowerSpecialCase() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchInstrInfo.cpp | 43 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg() 44 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) in copyPhysReg() 67 if (LoongArch::CFRRegClass.contains(DstReg) && in copyPhysReg() 74 if (LoongArch::GPRRegClass.contains(DstReg) && in copyPhysReg() 93 } else if (LoongArch::GPRRegClass.contains(DstReg) && in copyPhysReg() 97 } else if (LoongArch::GPRRegClass.contains(DstReg) && in copyPhysReg() 106 BuildMI(MBB, MBBI, DL, get(Opc), DstReg) in copyPhysReg() 177 BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg) in loadRegFromStackSlot() 198 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) in movImm() 206 BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg) in movImm() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 135 Register DstReg = Dst.getReg(); in runOnMachineFunction() local 138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction() 142 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction() 155 Register DstReg = Dst.getReg(); in runOnMachineFunction() local 157 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction() 172 Register DstReg = Dst.getReg(); in runOnMachineFunction() local 174 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction() 183 Register DstReg = Dst.getReg(); in runOnMachineFunction() local 186 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction() 190 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
H A D | X86InstructionSelector.cpp | 280 if (DstReg.isPhysical()) { in selectCopy() 765 const LLT DstTy = MRI.getType(DstReg); in selectTruncOrPtrToInt() 829 const LLT DstTy = MRI.getType(DstReg); in selectZext() 894 const LLT DstTy = MRI.getType(DstReg); in selectAnyext() 932 .addDef(DstReg) in selectAnyext() 1101 const LLT DstTy = MRI.getType(DstReg); in selectUAddSub() 1550 if (!MRI.getRegClassOrNull(DstReg)) { in selectImplicitDefOrPHI() 1783 .addDef(DstReg) in selectMulDivRem() 1789 DstReg) in selectMulDivRem() 1801 unsigned DstReg = Sel.getReg(0); in selectSelect() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMISimplifyPatchable.cpp | 67 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg, 191 Register &DstReg, const GlobalValue *GVal, bool IsAma) { in processCandidate() argument 192 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate() 200 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate() 210 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate() 215 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg) in processCandidate() 221 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate() 225 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument 227 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg() 329 Register DstReg = MI.getOperand(0).getReg(); in removeLD() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVInstructionSelector.cpp | 271 MIB.addReg(DstReg); in selectSHXADDOp() 283 MIB.addReg(DstReg); in selectSHXADDOp() 322 MIB.addReg(DstReg); in selectSHXADDOp() 361 MIB.addReg(DstReg); in selectSHXADD_UWOp() 766 MRI.setType(DstReg, sXLen); in preISelLower() 774 MRI.setType(DstReg, sXLen); in preISelLower() 865 if (DstReg.isPhysical()) in selectCopy() 869 MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); in selectCopy() 892 MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI)); in selectImplicitDef() 922 : DstReg; in materializeImm() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TwoAddressInstructionPass.cpp | 176 void scanUses(Register DstReg); 293 DstReg = 0; in isCopyToReg() 387 Register SrcReg, DstReg; in isKilled() local 760 Register Reg = DstReg; in scanUses() 813 Register SrcReg, DstReg; in processCopy() local 825 scanUses(DstReg); in processCopy() 873 Register DstReg; in rescheduleMIBelowKill() local 1056 Register DstReg; in rescheduleKillAboveMI() local 1453 if (SrcReg == DstReg) in collectTiedOperands() 1461 if (DstReg.isVirtual()) { in collectTiedOperands() [all …]
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H A D | ExpandPostRAPseudos.cpp | 66 Register DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg() local 72 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg() 74 assert(DstReg.isPhysical() && in LowerSubregToReg() 94 if (DstReg != InsReg) { in LowerSubregToReg() 109 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
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H A D | OptimizePHIs.cpp | 100 Register DstReg = MI->getOperand(0).getReg(); in IsSingleValuePHICycle() local 113 if (SrcReg == DstReg) in IsSingleValuePHICycle() 144 Register DstReg = MI->getOperand(0).getReg(); in IsDeadPHICycle() local 145 assert(DstReg.isVirtual() && "PHI destination is not a virtual register"); in IsDeadPHICycle() 155 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) { in IsDeadPHICycle()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCInstructionSelector.cpp | 133 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local 135 if (DstReg.isPhysical()) in selectCopy() 140 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy() 145 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy() 191 const Register DstReg = I.getOperand(0).getReg(); in selectIntToFP() local 199 bool IsSingle = MRI.getType(DstReg).getSizeInBits() == 32; in selectIntToFP() 218 const Register DstReg = I.getOperand(0).getReg(); in selectFPToInt() local 243 const Register DstReg = I.getOperand(0).getReg(); in selectZExt() local 244 const LLT DstTy = MRI.getType(DstReg); in selectZExt() 604 Register DstReg = I.getOperand(0).getReg(); in selectI64Imm() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64RedundantCopyElimination.cpp | 185 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local 194 SrcReg != DstReg) { in knownRegValInBlock() 208 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock() 213 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock() 217 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock() 251 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local 252 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock() 257 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock() 262 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
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H A D | AArch64ExpandPseudoInsts.cpp | 134 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm() 167 .addReg(DstReg) in expandMOVImm() 186 .addReg(DstReg) in expandMOVImm() 207 .addReg(DstReg, in expandMOVImm() 211 .addReg(DstReg) in expandMOVImm() 621 .addReg(DstReg) in expand_DestructiveOp() 1157 .addReg(DstReg, in expandMI() 1166 .addReg(DstReg, in expandMI() 1349 assert(DstReg != AArch64::XZR); in expandMI() 1366 .addReg(DstReg) in expandMI() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | InstructionSelect.cpp | 178 auto [DstReg, SrcReg] = MI.getFirst2Regs(); in runOnMachineFunction() 184 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() 187 assert(canReplaceReg(DstReg, SrcReg, MRI) && in runOnMachineFunction() 190 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction() 244 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local 245 if (SrcReg.isVirtual() && DstReg.isVirtual()) { in runOnMachineFunction() 247 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() 249 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 163 return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs; in forwardCopyWillClobberTuple() 354 MIB.addReg(DstReg, RegState::Undef); in copyPhysRegVector() 434 RISCV::GPRRegClass.contains(DstReg)) { in copyPhysReg() 450 DstReg = TRI->getMatchingSuperReg(DstReg, RISCV::sub_16, in copyPhysReg() 456 BuildMI(MBB, MBBI, DL, get(Opc), DstReg) in copyPhysReg() 476 if (RISCV::FPR32RegClass.contains(DstReg) && in copyPhysReg() 483 if (RISCV::GPRRegClass.contains(DstReg) && in copyPhysReg() 498 if (RISCV::GPRRegClass.contains(DstReg) && in copyPhysReg() 811 DstReg) in foldMemoryOperandImpl() 870 SrcReg = DstReg; in movImm() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 3211 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress() 3233 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress() 3236 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress() 3239 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress() 4531 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh() 4534 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh() 4629 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge() 4766 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle() 4814 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm() 5265 DstReg, DstReg, 0x1F, IDLoc, STI); in expandMulO() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kInstrInfo.cpp | 636 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg() 644 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg() 657 if (M68k::XR16RegClass.contains(DstReg)) in copyPhysReg() 659 else if (M68k::XR32RegClass.contains(DstReg)) in copyPhysReg() 662 M68k::XR32RegClass.contains(DstReg)) in copyPhysReg() 666 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg() 673 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg() 674 bool ToSR = DstReg == M68k::SR; in copyPhysReg() 677 assert(M68k::DR8RegClass.contains(DstReg) && in copyPhysReg() 688 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZCopyPhysRegs.cpp | 79 Register DstReg = MI->getOperand(0).getReg(); in visitMBB() local 80 if (DstReg.isVirtual() && in visitMBB() 91 SystemZ::AR32BitRegClass.contains(DstReg)) { in visitMBB() 94 BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp); in visitMBB()
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