| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 145 #define FEXP 3 macro
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| H A D | lex.c | 61 { "exp", FEXP, BLTIN },
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| H A D | run.c | 2091 case FEXP: in bltin()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | ZOSLibcallNames.def | 82 HANDLE_LIBCALL(EXP_F32, "@@FEXP@B")
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 74 DAG_FUNCTION(exp, 1, 1, experimental_constrained_exp, FEXP)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 947 FEXP, enumerator
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| H A D | BasicTTIImpl.h | 1887 ISD = ISD::FEXP; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 223 case ISD::FEXP: return "fexp"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 87 case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break; in SoftenFloatResult()
1316 case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break; in ExpandFloatResult()
2405 case ISD::FEXP: in PromoteFloatResult()
2813 case ISD::FEXP: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 401 case ISD::FEXP: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 89 case ISD::FEXP: in ScalarizeVectorResult()
1081 case ISD::FEXP: in SplitVectorResult()
4272 case ISD::FEXP: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4455 case ISD::FEXP: in ConvertNodeToLibcall()
5369 case ISD::FEXP: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5263 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags); in expandExp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 351 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
367 setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, in AMDGPUTargetLowering()
481 ISD::FDIV, ISD::FEXP2, ISD::FEXP, in AMDGPUTargetLowering()
1354 case ISD::FEXP: in LowerOperation()
1400 case ISD::FEXP: in ReplaceNodeResults()
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| H A D | AMDGPUISelDAGToDAG.cpp | 161 case ISD::FEXP: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 213 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in SITargetLowering()
475 setOperationAction({ISD::FLOG, ISD::FEXP, ISD::FLOG10}, MVT::f16, Custom); in SITargetLowering()
807 setOperationAction(ISD::FEXP, MVT::v2f16, Custom); in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 935 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 251 ISD::FEXP, ISD::FEXP2}) in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 372 setOperationAction(ISD::FEXP, VT, Expand); in addMVEVectorTypes()
882 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); in ARMTargetLowering()
904 setOperationAction(ISD::FEXP, MVT::v4f32, Expand); in ARMTargetLowering()
921 setOperationAction(ISD::FEXP, MVT::v2f32, Expand); in ARMTargetLowering()
1063 setOperationAction(ISD::FEXP, MVT::f64, Expand); in ARMTargetLowering()
1546 setOperationAction(ISD::FEXP, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 148 setOperationAction(ISD::FEXP, MVT::f16, Promote); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 438 setOperationAction(ISD::FEXP, MVT::f32, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1636 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 408 setOperationAction(ISD::FEXP, MVT::f64, Custom); in PPCTargetLowering()
414 setOperationAction(ISD::FEXP, MVT::f32, Custom); in PPCTargetLowering()
849 setOperationAction(ISD::FEXP, VT, Expand); in PPCTargetLowering()
11608 case ISD::FEXP: return lowerExp(Op, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 684 ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in AArch64TargetLowering()
1498 setOperationAction(ISD::FEXP, VT, Expand); in AArch64TargetLowering()
1689 setOperationAction(ISD::FEXP, VT, Expand); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 497 ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP, in RISCVTargetLowering()
964 setOperationAction(ISD::FEXP, VT, Expand); in RISCVTargetLowering()
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