| /freebsd/sys/dts/ |
| H A D | bindings-gpio.txt | 2 GPIO configuration.
5 1. Properties for GPIO Controllers
24 GPIO controller node.
38 GPIO: gpio@10100 {
67 gpios = <&GPIO 0 1 /* GPIO[0]: FLAGS */
68 &GPIO 1 2>; /* GPIO[1]: FLAGS */
100 gpios = <&GPIO 0 0x00000001 /* GPIO[0]: IN */
101 &GPIO 1 0x00000002 /* GPIO[1]: OUT */
102 &GPIO 2 0x00000801 /* GPIO[2]: IN, IRQ (edge) */
103 &GPIO 3 0x00004001 /* GPIO[3]: IN, IRQ (level) */
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | renesas,rzg2l-irqc.yaml | 58 - description: GPIO interrupt, TINT0
59 - description: GPIO interrupt, TINT1
60 - description: GPIO interrupt, TINT2
61 - description: GPIO interrupt, TINT3
62 - description: GPIO interrupt, TINT4
63 - description: GPIO interrupt, TINT5
64 - description: GPIO interrupt, TINT6
65 - description: GPIO interrupt, TINT7
66 - description: GPIO interrupt, TINT8
67 - description: GPIO interrupt, TINT9
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | intel,ixp4xx-gpio.yaml | 7 title: Intel IXP4xx XScale Networking Processors GPIO Controller
10 This GPIO controller is found in the Intel IXP4xx
11 processors. It supports 16 GPIO lines.
12 The interrupt portions of the GPIO controller is hierarchical.
16 the first 12 GPIO lines to 12 system interrupts.
17 The remaining 4 GPIO lines can not be used for receiving
19 The interrupt parent of this GPIO controller must be the
21 GPIO 14 and 15 can be used as clock outputs rather than GPIO,
45 description: If defined, enables clock output on GPIO 14
46 instead of GPIO.
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| H A D | gpio.txt | 1 Specifying GPIO information for devices
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
57 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
124 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
157 GPIO controller.
202 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
206 Each GPIO hog definition is represented as a child node of the GPIO controller.
209 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
267 The GPIO controller offset pertains to the GPIO controller node containing the
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| H A D | nxp,lpc1850-gpio.txt | 1 NXP LPC18xx/43xx GPIO controller Device Tree Bindings
6 - reg : List of addresses and lengths of the GPIO controller
10 - clocks : Phandle and clock specifier pair for GPIO controller
11 - resets : Phandle and reset specifier pair for GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller
14 - The first cell is the GPIO line number
19 0..9 range, for GPIO pin interrupts it is equal
21 GPIO pin configuration, 8 is for GPIO GROUP0
22 interrupt, 9 is for GPIO GROUP1 interrupt
26 - gpio-ranges : Mapping between GPIO and pinctrl
|
| H A D | intel,ixp4xx-gpio.txt | 1 Intel IXP4xx XScale Networking Processors GPIO
3 This GPIO controller is found in the Intel IXP4xx processors.
4 It supports 16 GPIO lines.
6 The interrupt portions of the GPIO controller is hierarchical:
7 the synchronous edge detector is part of the GPIO block, but the
10 the first 12 GPIO lines to 12 system interrupts.
12 The remaining 4 GPIO lines can not be used for receiving
15 The interrupt parent of this GPIO controller must be the
23 - gpio-controller : marks this as a GPIO controller
|
| H A D | nvidia,tegra186-gpio.txt | 1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
77 - "gpio": Mandatory. GPIO control registers. This may cover either:
100 Marks the device node as a GPIO controller/provider.
104 Indicates how many cells are used in a consumer's GPIO specifier.
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| H A D | 8xxx_gpio.txt | 1 GPIO controllers on MPC8xxx SoCs
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
8 See bindings/gpio/gpio.txt for details of how to specify GPIO
11 The GPIO module usually is connected to the SoC's internal interrupt
13 interrupt client nodes section) for details how to specify this GPIO
16 The GPIO module may serve as another interrupt controller (cascaded to
28 - interrupts: Interrupt mapping for GPIO IRQ.
29 - gpio-controller: Marks the port as GPIO controller.
32 - interrupt-controller: Empty boolean property which marks the GPIO
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| H A D | nvidia,tegra186-gpio.yaml | 7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
20 The Tegra186 GPIO controller allows software to set the IO direction of,
21 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
28 features available, varies between the different GPIO controllers.
33 GPIO data does not need access to these registers.
35 b) GPIO registers, which allow manipulation of the GPIO signals. In some
43 control a number of GPIOs. Thus, each GPIO is named according to an
44 alphabetical port name and an integer GPIO name within the port. For
99 GPIO control registers. This may cover either:
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| H A D | gpio-twl4030.txt | 1 twl4030 GPIO controller bindings
5 - "ti,twl4030-gpio" for twl4030 GPIO controller
9 - gpio-controller : Marks the device node as a GPIO controller.
12 The first cell is the GPIO number.
15 - ti,debounce : if n-th bit is set, debounces GPIO-n
16 - ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
17 - ti,pullups : if n-th bit is set, set a pullup on GPIO-n
18 - ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
|
| H A D | gpio-mmio.yaml | 7 title: Generic MMIO GPIO
14 Some simple GPIO controllers may consist of a single data register or a pair
24 - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
40 of GPIOs is set by the width, with bit 0 corresponding to GPIO 0.
43 Register to READ the value of the GPIO lines. If GPIO line is high,
44 the bit will be set. If the GPIO line is low, the bit will be cleared.
48 Register to SET the value of the GPIO lines. Setting a bit in this
49 register will drive the GPIO line high.
51 Register to CLEAR the value of the GPIO lines. Setting a bit in this
52 register will drive the GPIO line low. If this register is omitted,
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| H A D | gpio_lpc32xx.txt | 1 NXP LPC32xx SoC GPIO controller
6 - gpio-controller: Marks the device node as a GPIO controller.
9 0: GPIO P0
10 1: GPIO P1
11 2: GPIO P2
12 3: GPIO P3
18 - reg: Index of the GPIO group
|
| H A D | gpio-altera.txt | 1 Altera GPIO controller bindings
10 - gpio-controller : Marks the device node as a GPIO controller.
13 - The first cell is the GPIO offset number within the GPIO controller.
16 - altr,interrupt-type: Specifies the interrupt trigger type the GPIO
17 hardware is synthesized. This field is required if the Altera GPIO controller
19 but hardware synthesized. Required if GPIO is used as an interrupt
28 - altr,ngpio: Width of the GPIO bank. This defines how many pins the
29 GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
|
| H A D | cavium-octeon-gpio.txt | 1 * General Purpose Input Output (GPIO) bus.
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
36 * 1) GPIO pin number (0..15)
44 /* The GPIO pin connect to 16 consecutive CUI bits */
|
| H A D | gpio-vf610.yaml | 7 title: Freescale VF610 PORT/GPIO module
13 The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
17 Note: Each GPIO port should have an alias correctly numbered in "aliases"
40 - description: GPIO Trustzone non-secure interrupt number
41 - description: GPIO Trustzone secure interrupt number
56 - description: SoC GPIO clock
99 - description: GPIO register base address
106 - description: GPIO register base address
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| /freebsd/sys/contrib/device-tree/src/arm64/bitmain/ |
| H A D | bm1880-sophon-edge.dts | 12 * GPIO name legend: proper name = the GPIO line is used as GPIO
29 * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
30 * are the only ones actually used for GPIO.
56 "GPIO-A", /* GPIO0, LSEC pin 23 */
57 "GPIO-C", /* GPIO1, LSEC pin 25 */
59 "GPIO-E", /* GPIO3, LSEC pin 27 */
63 "GPIO-G", /* GPIO7, LSEC pin 29 */
112 "GPIO-I", /* GPIO50, LSEC pin 31 */
113 "GPIO-K", /* GPIO51, LSEC pin 33 */
124 "GPIO-B", /* GPIO62, LSEC pin 24 */
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| /freebsd/sys/contrib/device-tree/src/arm/hisilicon/ |
| H A D | hi3620-hi4511.dts | 95 0x0f8 0x1 /* GPIO (IOMG61) */
96 0x0fc 0x1 /* GPIO (IOMG62) */
107 0x104 0x1 /* GPIO (IOMG96) */
108 0x108 0x1 /* GPIO (IOMG64) */
119 0x160 0x1 /* GPIO (IOMG85) */
120 0x164 0x1 /* GPIO (IOMG86) */
132 0x168 0x1 /* GPIO (IOMG87) */
133 0x16c 0x1 /* GPIO (IOMG88) */
134 0x170 0x1 /* GPIO (IOMG93) */
144 0x0b4 0x1 /* GPIO (IOMG45) */
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| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | gpio-mouse.txt | 1 Device-Tree bindings for GPIO attached mice
3 This simply uses standard GPIO handles to define a simple mouse connected
4 to 5-7 GPIO lines.
9 - up-gpios: GPIO line phandle to the line indicating "up"
10 - down-gpios: GPIO line phandle to the line indicating "down"
11 - left-gpios: GPIO line phandle to the line indicating "left"
12 - right-gpios: GPIO line phandle to the line indicating "right"
15 - button-left-gpios: GPIO line handle to the left mouse button
16 - button-middle-gpios: GPIO line handle to the middle mouse button
17 - button-right-gpios: GPIO line handle to the right mouse button
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | ingenic,pinctrl.txt | 7 For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
9 GPIO port configuration registers and it is typical to refer to pins using the
10 naming scheme "PxN" where x is a character identifying the GPIO port with
12 pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
13 PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
14 contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
15 jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
35 Required properties for sub-nodes (GPIO chips):
45 - reg: The GPIO bank number.
50 - gpio-controller: Marks the device node as a GPIO controller.
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6ull-dhcom-pdk2.dts | 39 gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* GPIO A */
40 label = "TA1-GPIO-A";
46 gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; /* GPIO B */
47 label = "TA2-GPIO-B";
53 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
54 label = "TA3-GPIO-C";
60 gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; /* GPIO D */
61 label = "TA4-GPIO-D";
71 * Disable PDK2 LED5, because GPIO E is
92 * Disable PDK2 LED7, because GPIO H is
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| H A D | imx6qdl-dhcom-pdk2.dtsi | 63 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
64 label = "TA1-GPIO-A";
72 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
73 label = "TA2-GPIO-B";
81 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
82 label = "TA3-GPIO-C";
90 gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
91 label = "TA4-GPIO-D";
103 * Disable led-5, because GPIO E is
110 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | qrb5165-rb5.dts | 1090 "GPIO-A",
1091 "GPIO-C",
1092 "GPIO-E",
1093 "GPIO-D",
1100 "GPIO-X",
1111 "GPIO-Z",
1132 "GPIO-F",
1152 "GPIO-G",
1178 "GPIO-K",
1179 "GPIO-I",
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| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | hi3798cv200-poplar.dts | 108 gpio-line-names = "GPIO-E", "",
110 "", "GPIO-F",
111 "", "GPIO-J";
116 gpio-line-names = "GPIO-H", "GPIO-I",
117 "GPIO-L", "GPIO-G",
118 "GPIO-K", "",
126 "GPIO-C", "",
127 "", "GPIO-B";
134 "", "GPIO-D",
142 "", "GPIO-A",
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| /freebsd/sys/contrib/device-tree/Bindings/fsi/ |
| H A D | fsi-master-gpio.txt | 6 - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock
7 - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal
10 - enable-gpios = <gpio-descriptor>; : GPIO for enable signal
11 - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable
12 - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other
14 - no-gpio-delays; : Don't add extra delays between GPIO
16 GPIO block is running at a low enough
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| /freebsd/sys/contrib/device-tree/src/arm64/actions/ |
| H A D | s900-bubblegum-96.dts | 68 * GPIO name legend: proper name = the GPIO line is used as GPIO
88 * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
94 "GPIO-A", /* GPIO_0, LSEC pin 23 */
95 "GPIO-B", /* GPIO_1, LSEC pin 24 */
96 "GPIO-C", /* GPIO_2, LSEC pin 25 */
97 "GPIO-D", /* GPIO_3, LSEC pin 26 */
98 "GPIO-E", /* GPIO_4, LSEC pin 27 */
99 "GPIO-F", /* GPIO_5, LSEC pin 28 */
100 "GPIO-G", /* GPIO_6, LSEC pin 29 */
101 "GPIO-H", /* GPIO_7, LSEC pin 30 */
[all …]
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