1 /*- 2 * Copyright 1992-2015 Michal Meloun 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 #ifndef _TEGRA_DC_REG_H_ 27 #define _TEGRA_DC_REG_H_ 28 29 /* 30 * !!! WARNING !!! 31 * Tegra manual uses registers index (and not register addreses). 32 * We follow the TRM notation and index is converted to offset in 33 * WR4 / RD4 macros 34 */ 35 36 /* --------------------------- DC CMD -------------------------------------- */ 37 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 38 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 39 #define SYNCPT_CNTRL_NO_STALL (1 << 8) 40 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 41 42 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 43 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 44 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 45 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 46 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 47 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 48 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 49 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 50 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 51 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 52 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 53 #define SYNCPT_VSYNC_ENABLE (1 << 8) 54 55 #define DC_CMD_CTXSW 0x030 56 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 57 #define DC_CMD_DISPLAY_COMMAND 0x032 58 #define DISPLAY_CTRL_MODE(x) ((x) << 5) 59 #define CTRL_MODE_STOP 0 60 #define CTRL_MODE_C_DISPLAY 1 61 #define CTRL_MODE_NC_DISPLAY 2 62 63 #define DC_CMD_SIGNAL_RAISE 0x033 64 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 65 #define PM1_ENABLE (1 << 18) 66 #define PM0_ENABLE (1 << 16) 67 #define PW4_ENABLE (1 << 8) 68 #define PW3_ENABLE (1 << 6) 69 #define PW2_ENABLE (1 << 4) 70 #define PW1_ENABLE (1 << 2) 71 #define PW0_ENABLE (1 << 0) 72 73 #define DC_CMD_INT_STATUS 0x037 74 #define DC_CMD_INT_MASK 0x038 75 #define DC_CMD_INT_ENABLE 0x039 76 #define DC_CMD_INT_TYPE 0x03a 77 #define DC_CMD_INT_POLARITY 0x03b 78 #define WIN_T_UF_INT (1 << 25) 79 #define WIN_D_UF_INT (1 << 24) 80 #define HC_UF_INT (1 << 23) 81 #define CMU_LUT_CONFLICT_INT (1 << 22) 82 #define WIN_C_OF_INT (1 << 16) 83 #define WIN_B_OF_INT (1 << 15) 84 #define WIN_A_OF_INT (1 << 14) 85 #define SSF_INT (1 << 13) 86 #define MSF_INT (1 << 12) 87 #define WIN_C_UF_INT (1 << 10) 88 #define WIN_B_UF_INT (1 << 9) 89 #define WIN_A_UF_INT (1 << 8) 90 #define SPI_BUSY_INT (1 << 6) 91 #define V_PULSE2_INT (1 << 5) 92 #define V_PULSE3_INT (1 << 4) 93 #define HBLANK_INT (1 << 3) 94 #define VBLANK_INT (1 << 2) 95 #define FRAME_END_INT (1 << 1) 96 97 #define DC_CMD_STATE_ACCESS 0x040 98 #define WRITE_MUX (1 << 2) 99 #define READ_MUX (1 << 0) 100 101 #define DC_CMD_STATE_CONTROL 0x041 102 #define NC_HOST_TRIG (1 << 24) 103 #define CURSOR_UPDATE (1 << 15) 104 #define WIN_C_UPDATE (1 << 11) 105 #define WIN_B_UPDATE (1 << 10) 106 #define WIN_A_UPDATE (1 << 9) 107 #define WIN_UPDATE(x) (1 << (9 + (x))) 108 #define GENERAL_UPDATE (1 << 8) 109 #define CURSOR_ACT_REQ (1 << 7) 110 #define WIN_D_ACT_REQ (1 << 4) 111 #define WIN_C_ACT_REQ (1 << 3) 112 #define WIN_B_ACT_REQ (1 << 2) 113 #define WIN_A_ACT_REQ (1 << 1) 114 #define WIN_ACT_REQ(x) (1 << (1 + (x))) 115 #define GENERAL_ACT_REQ (1 << 0) 116 117 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 118 #define WINDOW_D_SELECT (1 << 7) 119 #define WINDOW_C_SELECT (1 << 6) 120 #define WINDOW_B_SELECT (1 << 5) 121 #define WINDOW_A_SELECT (1 << 4) 122 #define WINDOW_SELECT(x) (1 << (4 + (x))) 123 124 #define DC_CMD_REG_ACT_CONTROL 0x043 125 #define DC_CMD_WIN_D_INCR_SYNCPT 0x04c 126 #define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL 0x04d 127 #define DC_CMD_WIN_D_INCR_SYNCPT_ERROR 0x04e 128 129 /* ---------------------------- DC COM ------------------------------------- */ 130 131 /* --------------------------- DC DISP ------------------------------------- */ 132 133 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 134 #define M1_ENABLE (1 << 26) 135 #define M0_ENABLE (1 << 24) 136 #define V_PULSE2_ENABLE (1 << 18) 137 #define V_PULSE1_ENABLE (1 << 16) 138 #define V_PULSE0_ENABLE (1 << 14) 139 #define H_PULSE2_ENABLE (1 << 12) 140 #define H_PULSE1_ENABLE (1 << 10) 141 #define H_PULSE0_ENABLE (1 << 8) 142 143 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 144 145 #define DC_DISP_DISP_WIN_OPTIONS 0x402 146 #define HDMI_ENABLE (1 << 30) 147 #define DSI_ENABLE (1 << 29) 148 #define SOR1_TIMING_CYA (1 << 27) 149 #define SOR1_ENABLE (1 << 26) 150 #define SOR_ENABLE (1 << 25) 151 #define CURSOR_ENABLE (1 << 16) 152 153 #define DC_DISP_DISP_TIMING_OPTIONS 0x405 154 #define VSYNC_H_POSITION(x) (((x) & 0xfff) << 0) 155 156 #define DC_DISP_REF_TO_SYNC 0x406 157 #define DC_DISP_SYNC_WIDTH 0x407 158 #define DC_DISP_BACK_PORCH 0x408 159 #define DC_DISP_DISP_ACTIVE 0x409 160 #define DC_DISP_FRONT_PORCH 0x40a 161 #define DC_DISP_H_PULSE0_CONTROL 0x40b 162 #define DC_DISP_H_PULSE0_POSITION_A 0x40c 163 #define DC_DISP_H_PULSE0_POSITION_B 0x40d 164 #define DC_DISP_H_PULSE0_POSITION_C 0x40e 165 #define DC_DISP_H_PULSE0_POSITION_D 0x40f 166 #define DC_DISP_H_PULSE1_CONTROL 0x410 167 #define DC_DISP_H_PULSE1_POSITION_A 0x411 168 #define DC_DISP_H_PULSE1_POSITION_B 0x412 169 #define DC_DISP_H_PULSE1_POSITION_C 0x413 170 #define DC_DISP_H_PULSE1_POSITION_D 0x414 171 #define DC_DISP_H_PULSE2_CONTROL 0x415 172 #define DC_DISP_H_PULSE2_POSITION_A 0x416 173 #define DC_DISP_H_PULSE2_POSITION_B 0x417 174 #define DC_DISP_H_PULSE2_POSITION_C 0x418 175 #define DC_DISP_H_PULSE2_POSITION_D 0x419 176 #define DC_DISP_V_PULSE0_CONTROL 0x41a 177 #define DC_DISP_V_PULSE0_POSITION_A 0x41b 178 #define DC_DISP_V_PULSE0_POSITION_B 0x41c 179 #define DC_DISP_V_PULSE0_POSITION_C 0x41d 180 #define DC_DISP_V_PULSE1_CONTROL 0x41e 181 #define DC_DISP_V_PULSE1_POSITION_A 0x41f 182 #define DC_DISP_V_PULSE1_POSITION_B 0x420 183 #define DC_DISP_V_PULSE1_POSITION_C 0x421 184 #define DC_DISP_V_PULSE2_CONTROL 0x422 185 #define DC_DISP_V_PULSE2_POSITION_A 0x423 186 #define DC_DISP_V_PULSE3_CONTROL 0x424 187 #define PULSE_CONTROL_LAST(x) (((x) & 0x7f) << 8) 188 #define LAST_START_A 0 189 #define LAST_END_A 1 190 #define LAST_START_B 2 191 #define LAST_END_B 3 192 #define LAST_START_C 4 193 #define LAST_END_C 5 194 #define LAST_START_D 6 195 #define LAST_END_D 7 196 #define PULSE_CONTROL_QUAL(x) (((x) & 0x3) << 8) 197 #define QUAL_ALWAYS 0 198 #define QUAL_VACTIVE 2 199 #define QUAL_VACTIVE1 3 200 #define PULSE_POLARITY (1 << 4) 201 #define PULSE_MODE (1 << 3) 202 203 #define DC_DISP_V_PULSE3_POSITION_A 0x425 204 #define PULSE_END(x) (((x) & 0xfff) << 16) 205 #define PULSE_START(x) (((x) & 0xfff) << 0) 206 207 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e 208 #define PIXEL_CLK_DIVIDER(x) (((x) & 0xf) << 8) 209 #define PCD1 0 210 #define PCD1H 1 211 #define PCD2 2 212 #define PCD3 3 213 #define PCD4 4 214 #define PCD6 5 215 #define PCD8 6 216 #define PCD9 7 217 #define PCD12 8 218 #define PCD16 9 219 #define PCD18 10 220 #define PCD24 11 221 #define PCD13 12 222 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 223 224 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 225 #define DISP_ORDER_BLUE_RED ( 1 << 9) 226 #define DISP_ALIGNMENT_LSB ( 1 << 8) 227 #define DISP_DATA_FORMAT(x) (((x) & 0xf) << 8) 228 #define DF1P1C 0 229 #define DF1P2C24B 1 230 #define DF1P2C18B 2 231 #define DF1P2C16B 3 232 #define DF1S 4 233 #define DF2S 5 234 #define DF3S 6 235 #define DFSPI 7 236 #define DF1P3C24B 8 237 #define DF2P1C18B 9 238 #define DFDUAL1P1C18B 10 239 240 #define DC_DISP_DISP_COLOR_CONTROL 0x430 241 #define NON_BASE_COLOR (1 << 18) 242 #define BLANK_COLOR (1 << 17) 243 #define DISP_COLOR_SWAP (1 << 16) 244 #define ORD_DITHER_ROTATION(x) (((x) & 0x3) << 12) 245 #define DITHER_CONTROL(x) (((x) & 0x3) << 8) 246 #define DITHER_DISABLE 0 247 #define DITHER_ORDERED 2 248 #define DITHER_TEMPORAL 3 249 #define BASE_COLOR_SIZE(x) (((x) & 0xF) << 0) 250 #define SIZE_BASE666 0 251 #define SIZE_BASE111 1 252 #define SIZE_BASE222 2 253 #define SIZE_BASE333 3 254 #define SIZE_BASE444 4 255 #define SIZE_BASE555 5 256 #define SIZE_BASE565 6 257 #define SIZE_BASE332 7 258 #define SIZE_BASE888 8 259 260 #define DC_DISP_CURSOR_START_ADDR 0x43e 261 #define CURSOR_CLIP(x) (((x) & 0x3) << 28) 262 #define CC_DISPLAY 0 263 #define CC_WA 1 264 #define CC_WB 2 265 #define CC_WC 3 266 #define CURSOR_SIZE(x) (((x) & 0x3) << 24) 267 #define C32x32 0 268 #define C64x64 1 269 #define C128x128 2 270 #define C256x256 3 271 #define CURSOR_START_ADDR(x) (((x) >> 10) & 0x3FFFFF) 272 273 #define DC_DISP_CURSOR_POSITION 0x440 274 #define CURSOR_POSITION(h, v) ((((h) & 0x3fff) << 0) | \ 275 (((v) & 0x3fff) << 16)) 276 #define DC_DISP_CURSOR_UNDERFLOW_CTRL 0x4eb 277 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 278 #define CURSOR_MODE_SELECT (1 << 24) 279 #define CURSOR_DST_BLEND_FACTOR_SELECT(x) (((x) & 0x3) << 16) 280 #define DST_BLEND_ZERO 0 281 #define DST_BLEND_K1 1 282 #define DST_NEG_K1_TIMES_SRC 2 283 #define CURSOR_SRC_BLEND_FACTOR_SELECT(x) (((x) & 0x3) << 8) 284 #define SRC_BLEND_K1 0 285 #define SRC_BLEND_K1_TIMES_SRC 1 286 #define CURSOR_ALPHA(x) (((x) & 0xFF) << 0) 287 288 #define DC_DISP_CURSOR_UFLOW_DBG_PIXEL 0x4f3 289 #define CURSOR_UFLOW_CYA (1 << 7) 290 #define CURSOR_UFLOW_CTRL_DBG_MODE (1 << 0) 291 /* --------------------------- DC WIN ------------------------------------- */ 292 293 #define DC_WINC_COLOR_PALETTE 0x500 294 #define DC_WINC_CSC_YOF 0x611 295 #define DC_WINC_CSC_KYRGB 0x612 296 #define DC_WINC_CSC_KUR 0x613 297 #define DC_WINC_CSC_KVR 0x614 298 #define DC_WINC_CSC_KUG 0x615 299 #define DC_WINC_CSC_KVG 0x616 300 #define DC_WINC_CSC_KUB 0x617 301 #define DC_WINC_CSC_KVB 0x618 302 303 #define DC_WINC_WIN_OPTIONS 0x700 304 #define H_FILTER_MODE (1U << 31) 305 #define WIN_ENABLE (1 << 30) 306 #define INTERLACE_ENABLE (1 << 23) 307 #define YUV_RANGE_EXPAND (1 << 22) 308 #define DV_ENABLE (1 << 20) 309 #define CSC_ENABLE (1 << 18) 310 #define CP_ENABLE (1 << 16) 311 #define V_FILTER_UV_ALIGN (1 << 14) 312 #define V_FILTER_OPTIMIZE (1 << 12) 313 #define V_FILTER_ENABLE (1 << 10) 314 #define H_FILTER_ENABLE (1 << 8) 315 #define COLOR_EXPAND (1 << 6) 316 #define SCAN_COLUMN (1 << 4) 317 #define V_DIRECTION (1 << 2) 318 #define H_DIRECTION (1 << 0) 319 320 #define DC_WIN_BYTE_SWAP 0x701 321 #define BYTE_SWAP(x) (((x) & 0x7) << 0) 322 #define NOSWAP 0 323 #define SWAP2 1 324 #define SWAP4 2 325 #define SWAP4HW 3 326 #define SWAP02 4 327 #define SWAPLEFT 5 328 329 #define DC_WIN_COLOR_DEPTH 0x703 330 #define WIN_COLOR_DEPTH_P8 3 331 #define WIN_COLOR_DEPTH_B4G4R4A4 4 332 #define WIN_COLOR_DEPTH_B5G5R5A 5 333 #define WIN_COLOR_DEPTH_B5G6R5 6 334 #define WIN_COLOR_DEPTH_AB5G5R5 7 335 #define WIN_COLOR_DEPTH_B8G8R8A8 12 336 #define WIN_COLOR_DEPTH_R8G8B8A8 13 337 #define WIN_COLOR_DEPTH_YCbCr422 16 338 #define WIN_COLOR_DEPTH_YUV422 17 339 #define WIN_COLOR_DEPTH_YCbCr420P 18 340 #define WIN_COLOR_DEPTH_YUV420P 19 341 #define WIN_COLOR_DEPTH_YCbCr422P 20 342 #define WIN_COLOR_DEPTH_YUV422P 21 343 #define WIN_COLOR_DEPTH_YCbCr422R 22 344 #define WIN_COLOR_DEPTH_YUV422R 23 345 #define WIN_COLOR_DEPTH_YCbCr422RA 24 346 #define WIN_COLOR_DEPTH_YUV422RA 25 347 348 #define DC_WIN_POSITION 0x704 349 #define WIN_POSITION(h, v) ((((h) & 0x1fff) << 0) | \ 350 (((v) & 0x1fff) << 16)) 351 352 #define DC_WIN_SIZE 0x705 353 #define WIN_SIZE(h, v) ((((h) & 0x1fff) << 0) | \ 354 (((v) & 0x1fff) << 16)) 355 356 #define DC_WIN_PRESCALED_SIZE 0x706 357 #define WIN_PRESCALED_SIZE(h, v) ((((h) & 0x7fff) << 0) | \ 358 (((v) & 0x1fff) << 16)) 359 360 #define DC_WIN_H_INITIAL_DDA 0x707 361 #define DC_WIN_V_INITIAL_DDA 0x708 362 #define DC_WIN_DDA_INCREMENT 0x709 363 #define WIN_DDA_INCREMENT(h, v) ((((h) & 0xffff) << 0) | \ 364 (((v) & 0xffff) << 16)) 365 #define DC_WIN_LINE_STRIDE 0x70a 366 367 /* -------------------------- DC WINBUF ------------------------------------ */ 368 369 #define DC_WINBUF_START_ADDR 0x800 370 #define DC_WINBUF_START_ADDR_NS 0x801 371 #define DC_WINBUF_START_ADDR_U 0x802 372 #define DC_WINBUF_START_ADDR_U_NS 0x803 373 #define DC_WINBUF_START_ADDR_V 0x804 374 #define DC_WINBUF_START_ADDR_V_NS 0x805 375 #define DC_WINBUF_ADDR_H_OFFSET 0x806 376 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 377 #define DC_WINBUF_ADDR_V_OFFSET 0x808 378 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 379 #define DC_WINBUF_UFLOW_STATUS 0x80a 380 #define DC_WINBUF_SURFACE_KIND 0x80b 381 #define SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 382 #define SURFACE_KIND_PITCH 0 383 #define SURFACE_KIND_TILED 1 384 #define SURFACE_KIND_BL_16B2 2 385 #define DC_WINBUF_SURFACE_WEIGHT 0x80c 386 #define DC_WINBUF_START_ADDR_HI 0x80d 387 #define DC_WINBUF_START_ADDR_HI_NS 0x80e 388 #define DC_WINBUF_START_ADDR_U_HI 0x80f 389 #define DC_WINBUF_START_ADDR_U_HI_NS 0x810 390 #define DC_WINBUF_START_ADDR_V_HI 0x811 391 #define DC_WINBUF_START_ADDR_V_HI_NS 0x812 392 #define DC_WINBUF_UFLOW_CTRL 0x824 393 #define UFLOW_CTR_ENABLE (1 << 0) 394 #define DC_WINBUF_UFLOW_DBG_PIXEL 0x825 395 396 #endif /* _TEGRA_DC_REG_H_ */ 397