| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 56 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() function in HexagonRegisterInfo
61 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(Register R) const { in isEHReturnCalleeSaveReg()
67 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF, in getCallerSavedRegs()
141 const uint32_t *HexagonRegisterInfo::getCallPreservedMask( in getCallPreservedMask()
147 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) in getReservedRegs()
353 bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI, in shouldCoalesce()
402 Register HexagonRegisterInfo::getFrameRegister(const MachineFunction in getFrameRegister()
411 Register HexagonRegisterInfo::getFrameRegister() const { in getFrameRegister()
416 Register HexagonRegisterInfo::getStackRegister() const { in getStackRegister()
421 unsigned HexagonRegisterInfo::getHexagonSubRegIndex( in getHexagonSubRegIndex()
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| H A D | HexagonRegisterInfo.h | 29 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
31 HexagonRegisterInfo(unsigned HwMode);
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| H A D | HexagonBitTracker.h | 19 class HexagonRegisterInfo; variable
31 HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
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| H A D | HexagonFrameLowering.h | 25 class HexagonRegisterInfo; variable
123 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
125 const HexagonRegisterInfo &HRI) const;
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| H A D | HexagonVLIWPacketizer.h | 20 class HexagonRegisterInfo; variable
77 const HexagonRegisterInfo *HRI;
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| H A D | HexagonISelDAGToDAG.h | 26 class HexagonRegisterInfo; variable
31 const HexagonRegisterInfo *HRI;
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| H A D | HexagonSubtarget.h | 104 HexagonRegisterInfo RegInfo;
125 const HexagonRegisterInfo *getRegisterInfo() const override { in getRegisterInfo()
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| H A D | HexagonConstExtenders.cpp | 384 const HexagonRegisterInfo *HRI = nullptr;
445 PrintRegister(HCE::Register R, const HexagonRegisterInfo &I) in PrintRegister()
448 const HexagonRegisterInfo &HRI;
461 PrintExpr(const HCE::ExtExpr &E, const HexagonRegisterInfo &I) in PrintExpr()
464 const HexagonRegisterInfo &HRI;
479 PrintInit(const HCE::ExtenderInit &EI, const HexagonRegisterInfo &I) in PrintInit()
482 const HexagonRegisterInfo &HRI;
550 PrintIMap(const HCE::AssignmentMap &M, const HexagonRegisterInfo &I) in PrintIMap()
553 const HexagonRegisterInfo &HRI;
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| H A D | HexagonBranchRelaxation.cpp | 70 const HexagonRegisterInfo *HRI;
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| H A D | HexagonNewValueJump.cpp | 96 const HexagonRegisterInfo *QRI;
460 QRI = static_cast<const HexagonRegisterInfo *>( in runOnMachineFunction()
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| H A D | HexagonVectorPrint.cpp | 55 const HexagonRegisterInfo *QRI = nullptr;
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| H A D | HexagonBitSimplify.cpp | 468 auto &HRI = static_cast<const HexagonRegisterInfo&>( in parseRegSequence()
932 auto &HRI = static_cast<const HexagonRegisterInfo&>( in getFinalVRegClass()
1082 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in RedundantInstrElimination()
1098 const HexagonRegisterInfo &HRI;
1535 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in CopyGeneration()
1545 const HexagonRegisterInfo &HRI;
1555 CopyPropagation(const HexagonRegisterInfo &hri, MachineRegisterInfo &mri) in CopyPropagation()
1565 const HexagonRegisterInfo &HRI;
1776 const HexagonInstrInfo &hii, const HexagonRegisterInfo &hri, in BitSimplification()
1820 const HexagonRegisterInfo &HRI;
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| H A D | HexagonPeephole.cpp | 83 const HexagonRegisterInfo *QRI;
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| H A D | HexagonGenMux.cpp | 89 const HexagonRegisterInfo *HRI = nullptr;
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| H A D | HexagonBitTracker.cpp | 40 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri, in HexagonEvaluator()
95 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in mask()
136 const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); in composeWithSubRegIndex()
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| H A D | HexagonStoreWidening.cpp | 66 const HexagonRegisterInfo *TRI;
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| H A D | HexagonGenPredicate.cpp | 109 const HexagonRegisterInfo *TRI = nullptr;
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| H A D | HexagonInstrInfo.cpp | 136 static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst()
860 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in copyPhysReg()
1055 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in expandPostRAPseudo()
1732 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in ClobbersPredicate()
2213 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in isDependent()
3897 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getDuplexCandidateGroup()
4301 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getOperandLatency()
4472 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getMemAccessSize()
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| H A D | HexagonFrameLowering.cpp | 287 const HexagonRegisterInfo &HRI) { in needsStackFrame()
1362 const CSIVect &CSI, const HexagonRegisterInfo &HRI, in insertCSRSpillsInBlock()
1430 const CSIVect &CSI, const HexagonRegisterInfo &HRI) const { in insertCSRRestoresInBlock()
1528 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) { in needToReserveScavengingSpillSlots()
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| H A D | HexagonRegisterInfo.td | 1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
180 // as reserved in HexagonRegisterInfo.cpp.
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| H A D | Hexagon.td | 377 include "HexagonRegisterInfo.td"
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| H A D | HexagonOptAddrMode.cpp | 84 const HexagonRegisterInfo *HRI = nullptr;
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| H A D | HexagonISelLowering.cpp | 460 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerCall()
660 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerINLINEASM()
1168 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerRETURNADDR()
1194 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in LowerFRAMEADDR()
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| H A D | HexagonSplitDouble.cpp | 84 const HexagonRegisterInfo *TRI = nullptr;
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| H A D | HexagonVLIWPacketizer.cpp | 117 const HexagonRegisterInfo *HRI = nullptr;
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