Searched refs:InsMI (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 334 auto *InsMI = getOpcodeDef(TargetOpcode::G_INSERT_VECTOR_ELT, in matchDupFromInsertVectorElt() local
336 if (!InsMI) in matchDupFromInsertVectorElt()
339 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), in matchDupFromInsertVectorElt()
344 if (!mi_match(InsMI->getOperand(3).getReg(), MRI, m_ZeroInt())) in matchDupFromInsertVectorElt()
348 {InsMI->getOperand(2).getReg()}); in matchDupFromInsertVectorElt()
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| H A D | AArch64InstructionSelector.cpp | 3956 MachineInstr *InsMI = emitLaneInsert(std::nullopt, Tmp.getReg(0), Src1Reg, in selectMergeValues() local
3958 if (!InsMI) in selectMergeValues()
3960 MachineInstr *Ins2MI = emitLaneInsert(DstReg, InsMI->getOperand(0).getReg(), in selectMergeValues()
3964 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI); in selectMergeValues()
4231 MachineInstr &InsMI = in selectUnmergeValues() local
4239 constrainSelectedInstRegOperands(InsMI, TII, TRI, RBI); in selectUnmergeValues()
5424 MachineInstr *InsMI = in selectInsertElt() local
5430 if (!emitNarrowVector(DstReg, InsMI->getOperand(0).getReg(), MIB, MRI)) in selectInsertElt()
5434 InsMI->getOperand(0).setReg(DstReg); in selectInsertElt()
5435 constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI); in selectInsertElt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1246 MachineInstr *InsMI = in convertToThreeAddressWithLEA() local
1326 LV->replaceKillInstruction(Src, MI, *InsMI); in convertToThreeAddressWithLEA()
1333 SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI); in convertToThreeAddressWithLEA()
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