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Searched refs:IsLE (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Object/
H A DDecompressor.cpp22 bool IsLE, bool Is64Bit) { in create() argument
24 if (Error Err = D.consumeCompressedHeader(Is64Bit, IsLE)) in create()
/freebsd/contrib/llvm-project/llvm/include/llvm/Object/
H A DDecompressor.h29 bool IsLE, bool Is64Bit);
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3620 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3621 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3622 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3623 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3624 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3625 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3627 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3628 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3629 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3630 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
[all …]
H A DMipsInstrInfo.td237 def IsLE : Predicate<"Subtarget->isLittle()">;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h633 bool &Swap, bool IsLE);
654 bool &Swap, bool IsLE);
674 unsigned &InsertAtByte, bool &Swap, bool IsLE);
H A DPPCISelLowering.cpp1885 if (IsLE) in isVPKUHUMShuffleMask()
1891 if (!IsLE) in isVPKUHUMShuffleMask()
1897 unsigned j = IsLE ? 0 : 1; in isVPKUHUMShuffleMask()
1916 if (IsLE) in isVPKUWUMShuffleMask()
1923 if (!IsLE) in isVPKUWUMShuffleMask()
1930 unsigned j = IsLE ? 0 : 2; in isVPKUWUMShuffleMask()
1957 if (IsLE) in isVPKUDUMShuffleMask()
1966 if (!IsLE) in isVPKUDUMShuffleMask()
1975 unsigned j = IsLE ? 0 : 4; in isVPKUDUMShuffleMask()
2380 if (IsLE) { in isXXSLDWIShuffleMask()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DMachOEmitter.cpp378 makeRelocationInfo(const MachOYAML::Relocation &R, bool IsLE) { in makeRelocationInfo() argument
382 if (IsLE) in makeRelocationInfo()
H A DELFEmitter.cpp2041 bool IsLE = Doc.Header.Data == ELFYAML::ELF_ELFDATA(ELF::ELFDATA2LSB); in yaml2elf() local
2044 if (IsLE) in yaml2elf()
2048 if (IsLE) in yaml2elf()
/freebsd/contrib/llvm-project/llvm/lib/DWP/
H A DDWP.cpp341 bool IsLE = isa<object::ELF32LEObjectFile>(Obj) || in handleCompressedSection() local
345 Expected<Decompressor> Dec = Decompressor::create(Name, Contents, IsLE, Is64); in handleCompressedSection()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td222 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
H A DARMInstrThumb.td1651 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1653 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1655 Requires<[IsThumb, IsThumb1Only, IsLE]>;
H A DARMInstrNEON.td2462 let Predicates = [IsLE,HasNEON] in {
2487 let Predicates = [IsLE,HasNEON] in {
7538 let Predicates = [IsLE,HasNEON] in {
8029 let Predicates = [HasNEON,IsLE] in {
8054 let Predicates = [HasNEON,IsLE] in {
H A DARMInstrMVE.td7295 let Predicates = [HasMVEInt, IsLE] in {
7454 let Predicates = [IsLE,HasMVEInt] in {
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td3081 let Predicates = [IsLE] in {
3095 let Predicates = [IsLE] in {
3229 let Predicates = [IsLE] in {
3250 let Predicates = [IsLE] in {
3426 let Predicates = [IsLE] in {
3444 let Predicates = [IsLE] in {
3832 let Predicates = [IsLE] in {
3934 let Predicates = [IsLE] in {
3961 let Predicates = [IsLE] in {
4085 let Predicates = [IsLE] in {
[all …]
H A DAArch64SVEInstrInfo.td2567 let Predicates = [IsLE] in {
2871 let Predicates = [IsLE] in {
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp681 bool IsLE = DAG.getDataLayout().isLittleEndian(); in SimplifyMultipleUseDemandedBits() local
709 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyMultipleUseDemandedBits()
726 if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
844 if (IsLE && DemandedElts == 1 && in SimplifyMultipleUseDemandedBits()
1091 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedBits() local
2405 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2458 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2513 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2685 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyDemandedBits()
3048 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedVectorElts() local
[all …]
H A DSelectionDAG.cpp3267 bool IsLE = getDataLayout().isLittleEndian(); in computeKnownBits() local
3286 unsigned Shifts = IsLE ? i : SubScale - 1 - i; in computeKnownBits()
3306 unsigned Shifts = IsLE ? i : NumElts - 1 - i; in computeKnownBits()
4378 bool IsLE = getDataLayout().isLittleEndian(); in ComputeNumSignBits() local
4398 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset); in ComputeNumSignBits()
6281 bool IsLE = getDataLayout().isLittleEndian(); in FoldConstantArithmetic() local
6285 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) && in FoldConstantArithmetic()
6286 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) { in FoldConstantArithmetic()
6300 BuildVectorSDNode::recastRawBits(IsLE, BVVT.getScalarSizeInBits(), in FoldConstantArithmetic()
H A DDAGCombiner.cpp15528 bool IsLE = DAG.getDataLayout().isLittleEndian(); in ConstantFoldBITCASTofBUILD_VECTOR() local
15529 if (!BVN->getConstantRawBits(IsLE, DstBitSize, RawBits, UndefElements)) in ConstantFoldBITCASTofBUILD_VECTOR()
19969 bool IsLE = DAG.getDataLayout().isLittleEndian(); in mergeStoresOfConstantsOrVecElts() local
19971 unsigned Idx = IsLE ? (NumStores - 1 - i) : i; in mergeStoresOfConstantsOrVecElts()
22290 bool IsLE = DAG.getDataLayout().isLittleEndian(); in visitEXTRACT_VECTOR_ELT() local
22293 unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; in visitEXTRACT_VECTOR_ELT()
22307 BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; in visitEXTRACT_VECTOR_ELT()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp16696 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
16702 if (!IsLE) in EmitPPCBuiltinExpr()
16722 Op0 = IsLE ? HiLd : LoLd; in EmitPPCBuiltinExpr()
16723 Op1 = IsLE ? LoLd : HiLd; in EmitPPCBuiltinExpr()
16727 if (IsLE) { in EmitPPCBuiltinExpr()
16749 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
16755 if (IsLE) { in EmitPPCBuiltinExpr()
16791 if (IsLE && Width > 1) { in EmitPPCBuiltinExpr()
16804 Result = StoreSubVec(8, NumBytes - 8, IsLE ? 0 : 1); in EmitPPCBuiltinExpr()
16810 IsLE ? (Stored >> 2) : 3 - (Stored >> 2)); in EmitPPCBuiltinExpr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp7921 bool IsLE = SI.getModule()->getDataLayout().isLittleEndian(); in splitMergedValStore() local
7926 const bool IsOffsetStore = (IsLE && Upper) || (!IsLE && !Upper); in splitMergedValStore()