| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZk.td | 82 let Predicates = [HasStdExtZknd, IsRV32] in {
85 } // Predicates = [HasStdExtZknd, IsRV32]
100 let Predicates = [HasStdExtZkne, IsRV32] in {
103 } // Predicates = [HasStdExtZkne, IsRV32]
117 let Predicates = [HasStdExtZknh, IsRV32] in {
124 } // [HasStdExtZknh, IsRV32]
152 let Predicates = [HasStdExtZknd, IsRV32] in {
155 } // Predicates = [HasStdExtZknd, IsRV32]
170 let Predicates = [HasStdExtZkne, IsRV32] in {
173 } // Predicates = [HasStdExtZkne, IsRV32]
[all …]
|
| H A D | RISCVInstrInfoXCV.td | 41 let Predicates = [HasVendorXCVbitmanip, IsRV32],
98 let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0,
149 let Predicates = [HasVendorXCVmac, IsRV32] in {
162 } // Predicates = [HasVendorXCVmac, IsRV32]
392 let Predicates = [HasVendorXCVsimd, IsRV32],
550 let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
567 let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
617 let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
637 let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
656 let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0,
[all …]
|
| H A D | RISCVInstrInfoD.td | 221 let Predicates = [HasStdExtZdinx, IsRV32] in {
233 } // Predicates = [HasStdExtZdinx, IsRV32]
256 let Predicates = [HasStdExtZdinx, IsRV32] in {
262 } // Predicates = [HasStdExtZdinx, IsRV32]
349 let Predicates = [HasStdExtZdinx, IsRV32] in {
384 } // Predicates = [HasStdExtZdinx, IsRV32]
450 let Predicates = [HasStdExtZdinx, IsRV32] in {
468 } // Predicates = [HasStdExtZdinx, IsRV32]
511 let Predicates = [HasStdExtZdinx, IsRV32] in {
541 } // Predicates = [HasStdExtZdinx, IsRV32]
[all …]
|
| H A D | RISCVInstrInfoC.td | 335 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
369 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
413 Predicates = [HasStdExtCOrZca, IsRV32] in
521 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
579 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
865 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
885 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
899 let Predicates = [HasStdExtCOrZca, IsRV32] in {
902 } // Predicates = [HasStdExtCOrZca, IsRV32]
988 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
[all …]
|
| H A D | RISCVInstrInfoZa.td | 61 let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32Zacas" in {
63 } // Predicates = [HasStdExtZacas, IsRV32]
|
| H A D | RISCVInstrInfoZb.td | 448 let Predicates = [HasStdExtZbb, IsRV32] in {
451 } // Predicates = [HasStdExtZbb, IsRV32]
458 let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in {
461 } // Predicates = [HasStdExtZbbOrZbkb, IsRV32]
477 let Predicates = [HasStdExtZbkb, IsRV32] in {
482 } // Predicates = [HasStdExtZbkb, IsRV32]
599 let Predicates = [HasStdExtZbkb, IsRV32] in {
603 } // Predicates = [HasStdExtZbkb, IsRV32]
632 let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in
654 let Predicates = [HasStdExtZbkb, IsRV32] in
[all …]
|
| H A D | RISCVInstrInfoZfa.td | 126 let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
138 } // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
236 let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
|
| H A D | RISCVInstrInfoZfh.td | 63 [HasStdExtZhinx, HasStdExtZdinx, IsRV32],
66 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32],
254 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
304 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
576 let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] in {
586 } // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32]
|
| H A D | RISCVGISel.td | 151 let Predicates = [IsRV32] in {
|
| H A D | RISCVInstrInfoXTHead.td | 692 let Predicates = [HasVendorXTHeadMac, IsRV32] in {
699 } // Predicates = [HasVendorXTHeadMac, IsRV32]
824 let Predicates = [HasVendorXTHeadMemIdx, IsRV32] in {
|
| H A D | RISCVFeatures.td | 987 : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
993 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
|
| H A D | RISCVInstrInfo.td | 952 let Predicates = [IsRV32] in {
956 } // Predicates = [IsRV32]
2016 let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
|
| H A D | RISCVInstrInfoF.td | 513 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
|
| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | ELF_riscv.cpp | 499 bool IsRV32; member
526 Aux.Config.IsRV32 = G.getTargetTriple().isRISCV32(); in initRelaxAux()
604 } else if (Config.HasRVC && Config.IsRV32 && isInt<12>(Displace) && RD == 1) { in relaxCall()
|