/freebsd/sys/contrib/device-tree/Bindings/mfd/ |
H A D | aspeed-lpc.txt | 16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the 18 APB-to-LPC bridging amonst other functions. 21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 46 LPC memory region. 72 LPC Host Interface Controller 76 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 98 be exposed over the LPC to AHB mapping 110 LPC Host Controller 113 The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour 116 the LPC host controller node. [all …]
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H A D | aspeed-lpc.yaml | 8 title: Aspeed Low Pin Count (LPC) Bus Controller 15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth 17 primary use case of the Aspeed LPC controller is as a slave on the bus 21 The LPC controller is represented as a multi-function device to account for the 26 * An LPC Host Interface Controller manages functions exposed to the host such 27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 34 Additionally the state of the LPC controller influences the pinmux 66 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management 127 bytes written by the Host to the targeted LPC I/O pots. 145 description: The LPC I/O ports to snoop [all …]
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H A D | cros-ec.txt | 6 The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the 36 Required properties (LPC): 76 Example for LPC is not supplied as it is not yet implemented.
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/freebsd/sys/contrib/device-tree/Bindings/timer/ |
H A D | st,stih407-lpc | 1 STMicroelectronics Low Power Controller (LPC) - Clocksource 4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource 13 - reg : LPC registers base address + size 14 - interrupts : LPC interrupt line number and associated flags 15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) 16 - st,lpc-mode : The LPC can run either one of three modes:
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/freebsd/sys/contrib/device-tree/Bindings/rtc/ |
H A D | rtc-st-lpc.txt | 1 STMicroelectronics Low Power Controller (LPC) - RTC 4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource 13 - reg : LPC registers base address + size 14 - interrupts : LPC interrupt line number and associated flags 15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) 16 - st,lpc-mode : The LPC can run either one of three modes:
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
H A D | st_lpc_wdt.txt | 1 STMicroelectronics Low Power Controller (LPC) - Watchdog 4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource 13 - reg : LPC registers base address + size 14 - interrupts : LPC interrupt line number and associated flags 15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt) 16 - st,lpc-mode : The LPC can run either one of three modes:
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/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/ |
H A D | hisilicon-low-pin-count.txt | 2 Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which 6 LPC device node. 14 - reg: base memory range where the LPC register set is mapped.
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H A D | low-pin-count.yaml | 13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which 17 LPC device node.
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/freebsd/sys/contrib/device-tree/Bindings/ipmi/ |
H A D | aspeed,ast2400-kcs-bmc.yaml | 14 interfaces on the LPC bus for in-band IPMI communication with their host. 48 The host CPU LPC IO data and status addresses for the device. For most 57 A 2-cell property expressing the LPC SerIRQ number and the interrupt 67 description: The LPC channel number in the controller
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H A D | aspeed-kcs-bmc.txt | 13 - kcs_chan : The LPC channel number in the controller 23 - aspeed,lpc-io-reg : The host CPU LPC IO address for the device
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/freebsd/share/doc/smm/07.lpd/ |
H A D | spell.ok | 8 LPC
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/freebsd/sys/contrib/device-tree/Bindings/security/tpm/ |
H A D | tpm_tis_mmio.txt | 5 this interface will be implemented over Intel's LPC bus.
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/freebsd/sys/contrib/device-tree/Bindings/tpm/ |
H A D | tcg,tpm-tis-mmio.yaml | 15 one of them being LPC (via MMIO). The standard is named:
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | aspeed,ast2600-pinctrl.yaml | 38 I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, 63 LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
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/freebsd/sys/contrib/device-tree/Bindings/serial/ |
H A D | 8250.yaml | 202 configured. One possible data source is the LPC/eSPI mode bit. Only 210 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
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/freebsd/share/misc/ |
H A D | pci_vendors | 43 7a0c LPC Controller 4986 13e8 Ariel LPC Bridge 5527 7468 AMD-8111 LPC 5582 780e FCH LPC Bridge 5617 790e FCH LPC Bridge 10448 0260 MCP51 LPC Bridge 10454 0261 MCP51 LPC Bridge 10456 0262 MCP51 LPC Bridge 15550 0225 CSB5 LPC bridge 15553 0230 CSB5 LPC bridge [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | lpc1850-ccu.txt | 36 specific LPC part. Check the user manual for your specific part.
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H A D | lpc1850-cgu.txt | 42 specific LPC part. Base clocks are numbered from 0 to 27.
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/ |
H A D | aspeed-g6-pinctrl.dtsi | 346 function = "LPC"; 347 groups = "LPC";
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H A D | aspeed-bmc-ibm-bonnell.dts | 52 /* LPC FW cycle bridge region requires natural alignment */
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H A D | aspeed-bmc-opp-tacoma.dts | 867 /* Hog these as no driver is probed for the entire LPC block */
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H A D | aspeed-bmc-ibm-rainier.dts | 58 /* LPC FW cycle bridge region requires natural alignment */
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H A D | aspeed-bmc-ibm-everest.dts | 198 /* LPC FW cycle bridge region requires natural alignment */
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/freebsd/sys/contrib/device-tree/src/arm/gemini/ |
H A D | gemini-dlink-dns-313.dts | 212 * Used by fan & G751, conflicts LPC,
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H A D | gemini-dlink-dir-685.dts | 43 /* Collides with LPC LFRAME, UART RTS, SSP TXD */
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