| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 701 auto LaneIdx = getSplatIndex(MI); in matchDupLane() local
702 if (!LaneIdx) in matchDupLane()
706 if (*LaneIdx >= SrcTy.getNumElements()) in matchDupLane()
746 MatchInfo.second = *LaneIdx; in matchDupLane()
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| H A D | AArch64InstructionSelector.cpp | 2763 unsigned LaneIdx = Offset / 64; in select() local
4068 if (LaneIdx == 0) { in emitExtractVectorElt()
4121 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4256 unsigned LaneIdx = 1; in selectUnmergeValues() local
4258 Register CopyTo = I.getOperand(LaneIdx).getReg(); in selectUnmergeValues()
4262 .addImm(LaneIdx); in selectUnmergeValues()
4264 ++LaneIdx; in selectUnmergeValues()
5289 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert() argument
5305 .addImm(LaneIdx) in emitLaneInsert()
5310 .addImm(LaneIdx) in emitLaneInsert()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 3056 unsigned LaneIdx = Lane * VWidthPerLane; in simplifyDemandedVectorEltsIntrinsic() local
3058 unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum; in simplifyDemandedVectorEltsIntrinsic()
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| H A D | X86ISelLowering.cpp | 5088 int LaneIdx = (Idx / NumEltsPerLane) * NumEltsPerLane; in getHorizDemandedElts() local
5091 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 0); in getHorizDemandedElts()
5092 DemandedLHS.setBit(LaneIdx + 2 * LocalIdx + 1); in getHorizDemandedElts()
5095 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 0); in getHorizDemandedElts()
5096 DemandedRHS.setBit(LaneIdx + 2 * LocalIdx + 1); in getHorizDemandedElts()
21607 unsigned LaneIdx = LExtIndex / NumEltsPerLane; in lowerAddSubToHorizontalOp() local
21608 X = extract128BitVector(X, LaneIdx * NumEltsPerLane, DAG, DL); in lowerAddSubToHorizontalOp()
43749 unsigned LaneIdx = LaneOffset / Vec.getScalarValueSizeInBits(); in combineExtractWithShuffle() local
43751 Vec = extract128BitVector(Vec, LaneIdx, DAG, dl); in combineExtractWithShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 7715 int64_t LaneIdx; in parseSwizzleBroadcast() local
7727 if (parseSwizzleOperand(LaneIdx, in parseSwizzleBroadcast()
7731 Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0); in parseSwizzleBroadcast()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrSIMD.td | 55 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8159 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR() local
8160 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
15371 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine() local
15372 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx); in PerformARMBUILD_VECTORCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13235 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
13239 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
13393 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64); in LowerBUILD_VECTOR() local
13394 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
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