1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9 #include "reg.h"
10
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
14 #define BSSID_CAM_ENT_SIZE 0x08
15 #define HFC_PAGE_UNIT 64
16 #define RPWM_TRY_CNT 3
17
18 enum rtw89_mac_hwmod_sel {
19 RTW89_DMAC_SEL = 0,
20 RTW89_CMAC_SEL = 1,
21
22 RTW89_MAC_INVALID,
23 };
24
25 enum rtw89_mac_fwd_target {
26 RTW89_FWD_DONT_CARE = 0,
27 RTW89_FWD_TO_HOST = 1,
28 RTW89_FWD_TO_WLAN_CPU = 2
29 };
30
31 enum rtw89_mac_wd_dma_intvl {
32 RTW89_MAC_WD_DMA_INTVL_0S,
33 RTW89_MAC_WD_DMA_INTVL_256NS,
34 RTW89_MAC_WD_DMA_INTVL_512NS,
35 RTW89_MAC_WD_DMA_INTVL_768NS,
36 RTW89_MAC_WD_DMA_INTVL_1US,
37 RTW89_MAC_WD_DMA_INTVL_1_5US,
38 RTW89_MAC_WD_DMA_INTVL_2US,
39 RTW89_MAC_WD_DMA_INTVL_4US,
40 RTW89_MAC_WD_DMA_INTVL_8US,
41 RTW89_MAC_WD_DMA_INTVL_16US,
42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
43 };
44
45 enum rtw89_mac_multi_tag_num {
46 RTW89_MAC_TAG_NUM_1,
47 RTW89_MAC_TAG_NUM_2,
48 RTW89_MAC_TAG_NUM_3,
49 RTW89_MAC_TAG_NUM_4,
50 RTW89_MAC_TAG_NUM_5,
51 RTW89_MAC_TAG_NUM_6,
52 RTW89_MAC_TAG_NUM_7,
53 RTW89_MAC_TAG_NUM_8,
54 RTW89_MAC_TAG_NUM_DEF = 0xFE
55 };
56
57 enum rtw89_mac_lbc_tmr {
58 RTW89_MAC_LBC_TMR_8US = 0,
59 RTW89_MAC_LBC_TMR_16US,
60 RTW89_MAC_LBC_TMR_32US,
61 RTW89_MAC_LBC_TMR_64US,
62 RTW89_MAC_LBC_TMR_128US,
63 RTW89_MAC_LBC_TMR_256US,
64 RTW89_MAC_LBC_TMR_512US,
65 RTW89_MAC_LBC_TMR_1MS,
66 RTW89_MAC_LBC_TMR_2MS,
67 RTW89_MAC_LBC_TMR_4MS,
68 RTW89_MAC_LBC_TMR_8MS,
69 RTW89_MAC_LBC_TMR_DEF = 0xFE
70 };
71
72 enum rtw89_mac_cpuio_op_cmd_type {
73 CPUIO_OP_CMD_GET_1ST_PID = 0,
74 CPUIO_OP_CMD_GET_NEXT_PID = 1,
75 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
76 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
77 CPUIO_OP_CMD_DEQ = 8,
78 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
79 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
80 };
81
82 enum rtw89_mac_wde_dle_port_id {
83 WDE_DLE_PORT_ID_DISPATCH = 0,
84 WDE_DLE_PORT_ID_PKTIN = 1,
85 WDE_DLE_PORT_ID_CMAC0 = 3,
86 WDE_DLE_PORT_ID_CMAC1 = 4,
87 WDE_DLE_PORT_ID_CPU_IO = 6,
88 WDE_DLE_PORT_ID_WDRLS = 7,
89 WDE_DLE_PORT_ID_END = 8
90 };
91
92 enum rtw89_mac_wde_dle_queid_wdrls {
93 WDE_DLE_QUEID_TXOK = 0,
94 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
95 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
96 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
97 WDE_DLE_QUEID_NO_REPORT = 4
98 };
99
100 enum rtw89_mac_ple_dle_port_id {
101 PLE_DLE_PORT_ID_DISPATCH = 0,
102 PLE_DLE_PORT_ID_MPDU = 1,
103 PLE_DLE_PORT_ID_SEC = 2,
104 PLE_DLE_PORT_ID_CMAC0 = 3,
105 PLE_DLE_PORT_ID_CMAC1 = 4,
106 PLE_DLE_PORT_ID_WDRLS = 5,
107 PLE_DLE_PORT_ID_CPU_IO = 6,
108 PLE_DLE_PORT_ID_PLRLS = 7,
109 PLE_DLE_PORT_ID_END = 8
110 };
111
112 enum rtw89_mac_ple_dle_queid_plrls {
113 PLE_DLE_QUEID_NO_REPORT = 0x0
114 };
115
116 enum rtw89_machdr_frame_type {
117 RTW89_MGNT = 0,
118 RTW89_CTRL = 1,
119 RTW89_DATA = 2,
120 };
121
122 enum rtw89_mac_dle_dfi_type {
123 DLE_DFI_TYPE_FREEPG = 0,
124 DLE_DFI_TYPE_QUOTA = 1,
125 DLE_DFI_TYPE_PAGELLT = 2,
126 DLE_DFI_TYPE_PKTINFO = 3,
127 DLE_DFI_TYPE_PREPKTLLT = 4,
128 DLE_DFI_TYPE_NXTPKTLLT = 5,
129 DLE_DFI_TYPE_QLNKTBL = 6,
130 DLE_DFI_TYPE_QEMPTY = 7,
131 };
132
133 enum rtw89_mac_dle_wde_quota_id {
134 WDE_QTAID_HOST_IF = 0,
135 WDE_QTAID_WLAN_CPU = 1,
136 WDE_QTAID_DATA_CPU = 2,
137 WDE_QTAID_PKTIN = 3,
138 WDE_QTAID_CPUIO = 4,
139 };
140
141 enum rtw89_mac_dle_ple_quota_id {
142 PLE_QTAID_B0_TXPL = 0,
143 PLE_QTAID_B1_TXPL = 1,
144 PLE_QTAID_C2H = 2,
145 PLE_QTAID_H2C = 3,
146 PLE_QTAID_WLAN_CPU = 4,
147 PLE_QTAID_MPDU = 5,
148 PLE_QTAID_CMAC0_RX = 6,
149 PLE_QTAID_CMAC1_RX = 7,
150 PLE_QTAID_CMAC1_BBRPT = 8,
151 PLE_QTAID_WDRLS = 9,
152 PLE_QTAID_CPUIO = 10,
153 };
154
155 enum rtw89_mac_dle_ctrl_type {
156 DLE_CTRL_TYPE_WDE = 0,
157 DLE_CTRL_TYPE_PLE = 1,
158 DLE_CTRL_TYPE_NUM = 2,
159 };
160
161 enum rtw89_mac_ax_l0_to_l1_event {
162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
163 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
164 MAC_AX_L0_TO_L1_RLS_PKID = 2,
165 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
166 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
167 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
168 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
169 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
170 };
171
172 enum rtw89_mac_wow_fw_status {
173 WOWLAN_NOT_READY = 0x00,
174 WOWLAN_SLEEP_READY = 0x01,
175 WOWLAN_RESUME_READY = 0x02,
176 };
177
178 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
179
180 enum rtw89_mac_dbg_port_sel {
181 /* CMAC 0 related */
182 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
183 RTW89_DBG_PORT_SEL_SCH_C0,
184 RTW89_DBG_PORT_SEL_TMAC_C0,
185 RTW89_DBG_PORT_SEL_RMAC_C0,
186 RTW89_DBG_PORT_SEL_RMACST_C0,
187 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
188 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
189 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
190 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
191 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
192 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
193 /* CMAC 1 related */
194 RTW89_DBG_PORT_SEL_PTCL_C1,
195 RTW89_DBG_PORT_SEL_SCH_C1,
196 RTW89_DBG_PORT_SEL_TMAC_C1,
197 RTW89_DBG_PORT_SEL_RMAC_C1,
198 RTW89_DBG_PORT_SEL_RMACST_C1,
199 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
200 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
201 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
202 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
203 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
204 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
205 /* DLE related */
206 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
207 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
208 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
209 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
210 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
211 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
212 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
213 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
214 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
215 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
216 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
217 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
218 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
219 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
220 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
221 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
222 RTW89_DBG_PORT_SEL_PKTINFO,
223 /* DISPATCHER related */
224 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
225 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
226 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
227 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
228 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
229 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
230 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
231 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
232 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
233 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
234 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
235 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
236 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
237 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
238 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
239 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
240 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
241 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
242 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
243 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
244 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
245 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
246 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
247 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
248 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
249 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
250 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
251 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
252 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
253 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
254 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
255 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
256 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
257 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
258 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
259 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
260 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
261 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
262 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
263 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
264 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
265 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
266 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
267 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
268 /* PCIE related */
269 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
270 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
271 RTW89_DBG_PORT_SEL_PCIE_CVT,
272 RTW89_DBG_PORT_SEL_PCIE_CXPL,
273 RTW89_DBG_PORT_SEL_PCIE_IO,
274 RTW89_DBG_PORT_SEL_PCIE_MISC,
275 RTW89_DBG_PORT_SEL_PCIE_MISC2,
276
277 /* keep last */
278 RTW89_DBG_PORT_SEL_LAST,
279 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
280 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
281 };
282
283 /* SRAM mem dump */
284 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
285 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
286
287 #define AXIDMA_BASE_ADDR 0x18006000
288 #define STA_SCHED_BASE_ADDR 0x18808000
289 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
290 #define SECURITY_CAM_BASE_ADDR 0x18814000
291 #define WOW_CAM_BASE_ADDR 0x18815000
292 #define CMAC_TBL_BASE_ADDR 0x18840000
293 #define ADDR_CAM_BASE_ADDR 0x18850000
294 #define BSSID_CAM_BASE_ADDR 0x18853000
295 #define BA_CAM_BASE_ADDR 0x18854000
296 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
297 #define SHARED_BUF_BASE_ADDR 0x18700000
298 #define DMAC_TBL_BASE_ADDR 0x18800000
299 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
300 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
301 #define TXD_FIFO_0_BASE_ADDR 0x18856200
302 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
303 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
304 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
305 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
306 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
307 #define CPU_LOCAL_BASE_ADDR 0x18003000
308
309 #define WD_PAGE_BASE_ADDR_BE 0x0
310 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
311 #define AXIDMA_BASE_ADDR_BE 0x18006000
312 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
313 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
314 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
315 #define STA_SCHED_BASE_ADDR_BE 0x18818000
316 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
317 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
318 #define SEC_CAM_BASE_ADDR_BE 0x18824000
319 #define WOW_CAM_BASE_ADDR_BE 0x18828000
320 #define MLD_TBL_BASE_ADDR_BE 0x18829000
321 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
322 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
323 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
324 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
325 #define BA_CAM_BASE_ADDR_BE 0x18859000
326 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
327 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
328 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
329 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
330 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
331 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
332 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
333
334 #define CCTL_INFO_SIZE 32
335
336 enum rtw89_mac_mem_sel {
337 RTW89_MAC_MEM_AXIDMA,
338 RTW89_MAC_MEM_SHARED_BUF,
339 RTW89_MAC_MEM_DMAC_TBL,
340 RTW89_MAC_MEM_SHCUT_MACHDR,
341 RTW89_MAC_MEM_STA_SCHED,
342 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
343 RTW89_MAC_MEM_SECURITY_CAM,
344 RTW89_MAC_MEM_WOW_CAM,
345 RTW89_MAC_MEM_CMAC_TBL,
346 RTW89_MAC_MEM_ADDR_CAM,
347 RTW89_MAC_MEM_BA_CAM,
348 RTW89_MAC_MEM_BCN_IE_CAM0,
349 RTW89_MAC_MEM_BCN_IE_CAM1,
350 RTW89_MAC_MEM_TXD_FIFO_0,
351 RTW89_MAC_MEM_TXD_FIFO_1,
352 RTW89_MAC_MEM_TXDATA_FIFO_0,
353 RTW89_MAC_MEM_TXDATA_FIFO_1,
354 RTW89_MAC_MEM_CPU_LOCAL,
355 RTW89_MAC_MEM_BSSID_CAM,
356 RTW89_MAC_MEM_TXD_FIFO_0_V1,
357 RTW89_MAC_MEM_TXD_FIFO_1_V1,
358 RTW89_MAC_MEM_WD_PAGE,
359
360 /* keep last */
361 RTW89_MAC_MEM_NUM,
362 };
363
364 enum rtw89_rpwm_req_pwr_state {
365 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
366 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
367 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
368 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
369 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
370 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
371 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
372 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
373 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
374 };
375
376 struct rtw89_pwr_cfg {
377 u16 addr;
378 u8 cv_msk;
379 u8 intf_msk;
380 u8 base:4;
381 u8 cmd:4;
382 u8 msk;
383 u8 val;
384 };
385
386 enum rtw89_mac_c2h_ofld_func {
387 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
388 RTW89_MAC_C2H_FUNC_READ_RSP,
389 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
390 RTW89_MAC_C2H_FUNC_BCN_RESEND,
391 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
392 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
393 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
394 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
395 RTW89_MAC_C2H_FUNC_OFLD_MAX,
396 };
397
398 enum rtw89_mac_c2h_info_func {
399 RTW89_MAC_C2H_FUNC_REC_ACK,
400 RTW89_MAC_C2H_FUNC_DONE_ACK,
401 RTW89_MAC_C2H_FUNC_C2H_LOG,
402 RTW89_MAC_C2H_FUNC_BCN_CNT,
403 RTW89_MAC_C2H_FUNC_INFO_MAX,
404 };
405
406 enum rtw89_mac_c2h_mcc_func {
407 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
408 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
409 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
410 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
411
412 NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
413 };
414
415 enum rtw89_mac_c2h_mrc_func {
416 RTW89_MAC_C2H_FUNC_MRC_TSF_RPT = 0,
417 RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT = 1,
418
419 NUM_OF_RTW89_MAC_C2H_FUNC_MRC,
420 };
421
422 enum rtw89_mac_c2h_wow_func {
423 RTW89_MAC_C2H_FUNC_AOAC_REPORT,
424 RTW89_MAC_C2H_FUNC_READ_WOW_CAM,
425
426 NUM_OF_RTW89_MAC_C2H_FUNC_WOW,
427 };
428
429 enum rtw89_mac_c2h_class {
430 RTW89_MAC_C2H_CLASS_INFO = 0x0,
431 RTW89_MAC_C2H_CLASS_OFLD = 0x1,
432 RTW89_MAC_C2H_CLASS_TWT = 0x2,
433 RTW89_MAC_C2H_CLASS_WOW = 0x3,
434 RTW89_MAC_C2H_CLASS_MCC = 0x4,
435 RTW89_MAC_C2H_CLASS_FWDBG = 0x5,
436 RTW89_MAC_C2H_CLASS_MRC = 0xe,
437 RTW89_MAC_C2H_CLASS_MAX,
438 };
439
440 enum rtw89_mac_mcc_status {
441 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
442 RTW89_MAC_MCC_START_GROUP_OK = 1,
443 RTW89_MAC_MCC_STOP_GROUP_OK = 2,
444 RTW89_MAC_MCC_DEL_GROUP_OK = 3,
445 RTW89_MAC_MCC_RESET_GROUP_OK = 4,
446 RTW89_MAC_MCC_SWITCH_CH_OK = 5,
447 RTW89_MAC_MCC_TXNULL0_OK = 6,
448 RTW89_MAC_MCC_TXNULL1_OK = 7,
449
450 RTW89_MAC_MCC_SWITCH_EARLY = 10,
451 RTW89_MAC_MCC_TBTT = 11,
452 RTW89_MAC_MCC_DURATION_START = 12,
453 RTW89_MAC_MCC_DURATION_END = 13,
454
455 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
456 RTW89_MAC_MCC_START_GROUP_FAIL = 21,
457 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
458 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
459 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
460 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
461 RTW89_MAC_MCC_TXNULL0_FAIL = 26,
462 RTW89_MAC_MCC_TXNULL1_FAIL = 27,
463 };
464
465 enum rtw89_mac_mrc_status {
466 RTW89_MAC_MRC_START_SCH_OK = 0,
467 RTW89_MAC_MRC_STOP_SCH_OK = 1,
468 RTW89_MAC_MRC_DEL_SCH_OK = 2,
469 RTW89_MAC_MRC_EMPTY_SCH_FAIL = 16,
470 RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL = 17,
471 RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL = 18,
472 RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL = 19,
473 RTW89_MAC_MRC_ALT_ROLE_FAIL = 20,
474 RTW89_MAC_MRC_ADD_PSTIMER_FAIL = 21,
475 RTW89_MAC_MRC_MALLOC_FAIL = 22,
476 RTW89_MAC_MRC_SWITCH_CH_FAIL = 23,
477 RTW89_MAC_MRC_TXNULL0_FAIL = 24,
478 RTW89_MAC_MRC_PORT_FUNC_EN_FAIL = 25,
479 };
480
481 struct rtw89_mac_ax_coex {
482 #define RTW89_MAC_AX_COEX_RTK_MODE 0
483 #define RTW89_MAC_AX_COEX_CSR_MODE 1
484 u8 pta_mode;
485 #define RTW89_MAC_AX_COEX_INNER 0
486 #define RTW89_MAC_AX_COEX_OUTPUT 1
487 #define RTW89_MAC_AX_COEX_INPUT 2
488 u8 direction;
489 };
490
491 struct rtw89_mac_ax_plt {
492 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
493 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
494 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
495 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
496 u8 band;
497 u8 tx;
498 u8 rx;
499 };
500
501 enum rtw89_mac_bf_rrsc_rate {
502 RTW89_MAC_BF_RRSC_6M = 0,
503 RTW89_MAC_BF_RRSC_9M = 1,
504 RTW89_MAC_BF_RRSC_12M,
505 RTW89_MAC_BF_RRSC_18M,
506 RTW89_MAC_BF_RRSC_24M,
507 RTW89_MAC_BF_RRSC_36M,
508 RTW89_MAC_BF_RRSC_48M,
509 RTW89_MAC_BF_RRSC_54M,
510 RTW89_MAC_BF_RRSC_HT_MSC0,
511 RTW89_MAC_BF_RRSC_HT_MSC1,
512 RTW89_MAC_BF_RRSC_HT_MSC2,
513 RTW89_MAC_BF_RRSC_HT_MSC3,
514 RTW89_MAC_BF_RRSC_HT_MSC4,
515 RTW89_MAC_BF_RRSC_HT_MSC5,
516 RTW89_MAC_BF_RRSC_HT_MSC6,
517 RTW89_MAC_BF_RRSC_HT_MSC7,
518 RTW89_MAC_BF_RRSC_VHT_MSC0,
519 RTW89_MAC_BF_RRSC_VHT_MSC1,
520 RTW89_MAC_BF_RRSC_VHT_MSC2,
521 RTW89_MAC_BF_RRSC_VHT_MSC3,
522 RTW89_MAC_BF_RRSC_VHT_MSC4,
523 RTW89_MAC_BF_RRSC_VHT_MSC5,
524 RTW89_MAC_BF_RRSC_VHT_MSC6,
525 RTW89_MAC_BF_RRSC_VHT_MSC7,
526 RTW89_MAC_BF_RRSC_HE_MSC0,
527 RTW89_MAC_BF_RRSC_HE_MSC1,
528 RTW89_MAC_BF_RRSC_HE_MSC2,
529 RTW89_MAC_BF_RRSC_HE_MSC3,
530 RTW89_MAC_BF_RRSC_HE_MSC4,
531 RTW89_MAC_BF_RRSC_HE_MSC5,
532 RTW89_MAC_BF_RRSC_HE_MSC6,
533 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
534 RTW89_MAC_BF_RRSC_MAX = 32
535 };
536
537 #define RTW89_R32_EA 0xEAEAEAEA
538 #define RTW89_R32_DEAD 0xDEADBEEF
539 #define MAC_REG_POOL_COUNT 10
540 #define ACCESS_CMAC(_addr) \
541 ({typeof(_addr) __addr = (_addr); \
542 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
543 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
544 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
545
546 #define PTCL_IDLE_POLL_CNT 10000
547 #define SW_CVR_DUR_US 8
548 #define SW_CVR_CNT 8
549
550 #define DLE_BOUND_UNIT (8 * 1024)
551 #define DLE_WAIT_CNT 2000
552 #define TRXCFG_WAIT_CNT 2000
553
554 #define RTW89_WDE_PG_64 64
555 #define RTW89_WDE_PG_128 128
556 #define RTW89_WDE_PG_256 256
557
558 #define S_AX_WDE_PAGE_SEL_64 0
559 #define S_AX_WDE_PAGE_SEL_128 1
560 #define S_AX_WDE_PAGE_SEL_256 2
561
562 #define RTW89_PLE_PG_64 64
563 #define RTW89_PLE_PG_128 128
564 #define RTW89_PLE_PG_256 256
565
566 #define S_AX_PLE_PAGE_SEL_64 0
567 #define S_AX_PLE_PAGE_SEL_128 1
568 #define S_AX_PLE_PAGE_SEL_256 2
569
570 #define B_CMAC0_MGQ_NORMAL BIT(2)
571 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
572 #define B_CMAC0_CPUMGQ BIT(4)
573 #define B_CMAC1_MGQ_NORMAL BIT(10)
574 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
575 #define B_CMAC1_CPUMGQ BIT(12)
576
577 #define B_CMAC0_MGQ_NORMAL_BE BIT(2)
578 #define B_CMAC1_MGQ_NORMAL_BE BIT(30)
579
580 #define QEMP_ACQ_GRP_MACID_NUM 8
581 #define QEMP_ACQ_GRP_QSEL_SH 4
582 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
583
584 #define SDIO_LOCAL_BASE_ADDR 0x80000000
585
586 #define PWR_CMD_WRITE 0
587 #define PWR_CMD_POLL 1
588 #define PWR_CMD_DELAY 2
589 #define PWR_CMD_END 3
590
591 #define PWR_INTF_MSK_SDIO BIT(0)
592 #define PWR_INTF_MSK_USB BIT(1)
593 #define PWR_INTF_MSK_PCIE BIT(2)
594 #define PWR_INTF_MSK_ALL 0x7
595
596 #define PWR_BASE_MAC 0
597 #define PWR_BASE_USB 1
598 #define PWR_BASE_PCIE 2
599 #define PWR_BASE_SDIO 3
600
601 #define PWR_CV_MSK_A BIT(0)
602 #define PWR_CV_MSK_B BIT(1)
603 #define PWR_CV_MSK_C BIT(2)
604 #define PWR_CV_MSK_D BIT(3)
605 #define PWR_CV_MSK_E BIT(4)
606 #define PWR_CV_MSK_F BIT(5)
607 #define PWR_CV_MSK_G BIT(6)
608 #define PWR_CV_MSK_TEST BIT(7)
609 #define PWR_CV_MSK_ALL 0xFF
610
611 #define PWR_DELAY_US 0
612 #define PWR_DELAY_MS 1
613
614 /* STA scheduler */
615 #define SS_MACID_SH 8
616 #define SS_TX_LEN_MSK 0x1FFFFF
617 #define SS_CTRL1_R_TX_LEN 5
618 #define SS_CTRL1_R_NEXT_LINK 20
619 #define SS_LINK_SIZE 256
620
621 /* MAC debug port */
622 #define TMAC_DBG_SEL_C0 0xA5
623 #define RMAC_DBG_SEL_C0 0xA6
624 #define TRXPTCL_DBG_SEL_C0 0xA7
625 #define TMAC_DBG_SEL_C1 0xB5
626 #define RMAC_DBG_SEL_C1 0xB6
627 #define TRXPTCL_DBG_SEL_C1 0xB7
628 #define FW_PROG_CNTR_DBG_SEL 0xF2
629 #define PCIE_TXDMA_DBG_SEL 0x30
630 #define PCIE_RXDMA_DBG_SEL 0x31
631 #define PCIE_CVT_DBG_SEL 0x32
632 #define PCIE_CXPL_DBG_SEL 0x33
633 #define PCIE_IO_DBG_SEL 0x37
634 #define PCIE_MISC_DBG_SEL 0x38
635 #define PCIE_MISC2_DBG_SEL 0x00
636 #define MAC_DBG_SEL 1
637 #define RMAC_CMAC_DBG_SEL 1
638
639 /* TRXPTCL dbg port sel */
640 #define TRXPTRL_DBG_SEL_TMAC 0
641 #define TRXPTRL_DBG_SEL_RMAC 1
642
643 struct rtw89_cpuio_ctrl {
644 u16 pkt_num;
645 u16 start_pktid;
646 u16 end_pktid;
647 u8 cmd_type;
648 u8 macid;
649 u8 src_pid;
650 u8 src_qid;
651 u8 dst_pid;
652 u8 dst_qid;
653 u16 pktid;
654 };
655
656 struct rtw89_mac_dbg_port_info {
657 u32 sel_addr;
658 u8 sel_byte;
659 u32 sel_msk;
660 u32 srt;
661 u32 end;
662 u32 rd_addr;
663 u8 rd_byte;
664 u32 rd_msk;
665 };
666
667 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
668 #define QLNKTBL_ADDR_INFO_SEL_0 0
669 #define QLNKTBL_ADDR_INFO_SEL_1 1
670 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
671 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
672
673 struct rtw89_mac_dle_dfi_ctrl {
674 enum rtw89_mac_dle_ctrl_type type;
675 u32 target;
676 u32 addr;
677 u32 out_data;
678 };
679
680 struct rtw89_mac_dle_dfi_quota {
681 enum rtw89_mac_dle_ctrl_type dle_type;
682 u32 qtaid;
683 u16 rsv_pgnum;
684 u16 use_pgnum;
685 };
686
687 struct rtw89_mac_dle_dfi_qempty {
688 enum rtw89_mac_dle_ctrl_type dle_type;
689 u32 grpsel;
690 u32 qempty;
691 };
692
693 enum rtw89_mac_dle_rsvd_qt_type {
694 DLE_RSVD_QT_MPDU_INFO,
695 DLE_RSVD_QT_B0_CSI,
696 DLE_RSVD_QT_B1_CSI,
697 DLE_RSVD_QT_B0_LMR,
698 DLE_RSVD_QT_B1_LMR,
699 DLE_RSVD_QT_B0_FTM,
700 DLE_RSVD_QT_B1_FTM,
701 };
702
703 struct rtw89_mac_dle_rsvd_qt_cfg {
704 u16 pktid;
705 u16 pg_num;
706 u32 size;
707 };
708
709 enum rtw89_mac_error_scenario {
710 RTW89_RXI300_ERROR = 1,
711 RTW89_WCPU_CPU_EXCEPTION = 2,
712 RTW89_WCPU_ASSERTION = 3,
713 };
714
715 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
716
717 /* Define DBG and recovery enum */
718 enum mac_ax_err_info {
719 /* Get error info */
720
721 /* L0 */
722 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
723 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
724 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
725 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
726
727 /* L1 */
728 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
729 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
730 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
731 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
732 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
733 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
734
735 /* L2 */
736 /* address hole (master) */
737 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
738 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
739 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
740 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
741 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
742 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
743 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
744 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
745
746 /* AHB bridge timeout (master) */
747 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
748 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
749 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
750 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
751 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
752 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
753 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
754 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
755
756 /* APB_SA bridge timeout (master + slave) */
757 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
758 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
759 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
760 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
761 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
762 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
763 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
764 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
765 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
766 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
767 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
768 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
769 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
770 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
771 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
772 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
773 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
774 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
775 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
776 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
777 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
778 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
779 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
780 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
781 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
782 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
783 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
784 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
785 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
786 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
787 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
788 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
789 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
790 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
791 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
792 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
793 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
794 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
795 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
796 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
797 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
798 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
799 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
800 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
801 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
802 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
803 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
807 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
808 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
809 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
810 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
811 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
812 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
813 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
814 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
815 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
816 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
817 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
818 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
819 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
820 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
821 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
822 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
823 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
824 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
825 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
826 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
827 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
828 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
829 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
830 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
831 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
832 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
833 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
834 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
835 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
836 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
837 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
838 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
839 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
840 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
841 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
842 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
843 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
844
845 /* APB_BBRF bridge timeout (master) */
846 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
847 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
848 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
849 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
850 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
851 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
852 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
853 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
854 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
855 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
856 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
857 MAC_AX_ERR_ASSERTION = 0x4000,
858 MAC_AX_ERR_RXI300 = 0x5000,
859 MAC_AX_GET_ERR_MAX,
860 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
861
862 /* set error info */
863 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
864 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
865 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
866 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
867 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
868 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
869 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
870 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
871 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
872 MAC_AX_SET_ERR_MAX,
873 };
874
875 struct rtw89_mac_size_set {
876 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
877 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
878 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
879 const struct rtw89_dle_size wde_size0;
880 const struct rtw89_dle_size wde_size0_v1;
881 const struct rtw89_dle_size wde_size4;
882 const struct rtw89_dle_size wde_size4_v1;
883 const struct rtw89_dle_size wde_size6;
884 const struct rtw89_dle_size wde_size7;
885 const struct rtw89_dle_size wde_size9;
886 const struct rtw89_dle_size wde_size18;
887 const struct rtw89_dle_size wde_size19;
888 const struct rtw89_dle_size ple_size0;
889 const struct rtw89_dle_size ple_size0_v1;
890 const struct rtw89_dle_size ple_size3_v1;
891 const struct rtw89_dle_size ple_size4;
892 const struct rtw89_dle_size ple_size6;
893 const struct rtw89_dle_size ple_size8;
894 const struct rtw89_dle_size ple_size18;
895 const struct rtw89_dle_size ple_size19;
896 const struct rtw89_wde_quota wde_qt0;
897 const struct rtw89_wde_quota wde_qt0_v1;
898 const struct rtw89_wde_quota wde_qt4;
899 const struct rtw89_wde_quota wde_qt6;
900 const struct rtw89_wde_quota wde_qt7;
901 const struct rtw89_wde_quota wde_qt17;
902 const struct rtw89_wde_quota wde_qt18;
903 const struct rtw89_ple_quota ple_qt0;
904 const struct rtw89_ple_quota ple_qt1;
905 const struct rtw89_ple_quota ple_qt4;
906 const struct rtw89_ple_quota ple_qt5;
907 const struct rtw89_ple_quota ple_qt9;
908 const struct rtw89_ple_quota ple_qt13;
909 const struct rtw89_ple_quota ple_qt18;
910 const struct rtw89_ple_quota ple_qt44;
911 const struct rtw89_ple_quota ple_qt45;
912 const struct rtw89_ple_quota ple_qt46;
913 const struct rtw89_ple_quota ple_qt47;
914 const struct rtw89_ple_quota ple_qt58;
915 const struct rtw89_ple_quota ple_qt_52a_wow;
916 const struct rtw89_ple_quota ple_qt_52b_wow;
917 const struct rtw89_ple_quota ple_qt_51b_wow;
918 const struct rtw89_rsvd_quota ple_rsvd_qt0;
919 const struct rtw89_rsvd_quota ple_rsvd_qt1;
920 const struct rtw89_dle_rsvd_size rsvd0_size0;
921 const struct rtw89_dle_rsvd_size rsvd1_size0;
922 };
923
924 extern const struct rtw89_mac_size_set rtw89_mac_size;
925
926 struct rtw89_mac_gen_def {
927 u32 band1_offset;
928 u32 filter_model_addr;
929 u32 indir_access_addr;
930 const u32 *mem_base_addrs;
931 u32 rx_fltr;
932 const struct rtw89_port_reg *port_base;
933 u32 agg_len_ht;
934 u32 ps_status;
935
936 struct rtw89_reg_def muedca_ctrl;
937 struct rtw89_reg_def bfee_ctrl;
938 struct rtw89_reg_def narrow_bw_ru_dis;
939 struct rtw89_reg_def wow_ctrl;
940
941 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
942 enum rtw89_mac_hwmod_sel sel);
943 int (*sys_init)(struct rtw89_dev *rtwdev);
944 int (*trx_init)(struct rtw89_dev *rtwdev);
945 void (*hci_func_en)(struct rtw89_dev *rtwdev);
946 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
947 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
948 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable);
949 void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
950 struct ieee80211_sta *sta);
951
952 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev,
953 enum rtw89_machdr_frame_type type,
954 enum rtw89_mac_fwd_target fwd_target,
955 u8 mac_idx);
956 int (*cfg_ppdu_status)(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable);
957
958 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
959 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
960 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id);
961 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en);
962 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev);
963 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev);
964 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev);
965 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev,
966 const struct rtw89_wde_quota *min_cfg,
967 const struct rtw89_wde_quota *max_cfg,
968 u16 ext_wde_min_qt_wcpu);
969 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev,
970 const struct rtw89_ple_quota *min_cfg,
971 const struct rtw89_ple_quota *max_cfg);
972 int (*set_cpuio)(struct rtw89_dev *rtwdev,
973 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
974 int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
975
976 void (*disable_cpu)(struct rtw89_dev *rtwdev);
977 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
978 bool dlfw, bool include_bb);
979 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
980 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);
981 int (*parse_efuse_map)(struct rtw89_dev *rtwdev);
982 int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
983 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
984
985 int (*cfg_plt)(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
986 u16 (*get_plt_cnt)(struct rtw89_dev *rtwdev, u8 band);
987
988 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,
989 enum rtw89_phy_idx phy_idx,
990 u32 reg_base, u32 *cr);
991
992 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
993 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
994
995 void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
996 void (*dump_err_status)(struct rtw89_dev *rtwdev,
997 enum mac_ax_err_info err);
998
999 bool (*is_txq_empty)(struct rtw89_dev *rtwdev);
1000
1001 int (*add_chan_list)(struct rtw89_dev *rtwdev,
1002 struct rtw89_vif *rtwvif, bool connected);
1003 int (*scan_offload)(struct rtw89_dev *rtwdev,
1004 struct rtw89_scan_option *option,
1005 struct rtw89_vif *rtwvif);
1006
1007 int (*wow_config_mac)(struct rtw89_dev *rtwdev, bool enable_wow);
1008 };
1009
1010 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
1011 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
1012
1013 static inline
rtw89_mac_reg_by_idx(struct rtw89_dev * rtwdev,u32 reg_base,u8 band)1014 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
1015 {
1016 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1017
1018 return band == 0 ? reg_base : (reg_base + mac->band1_offset);
1019 }
1020
1021 static inline
rtw89_mac_reg_by_port(struct rtw89_dev * rtwdev,u32 base,u8 port,u8 mac_idx)1022 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
1023 {
1024 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx);
1025 }
1026
1027 static inline u32
rtw89_read32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base)1028 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base)
1029 {
1030 u32 reg;
1031
1032 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1033 return rtw89_read32(rtwdev, reg);
1034 }
1035
1036 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask)1037 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1038 u32 base, u32 mask)
1039 {
1040 u32 reg;
1041
1042 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1043 return rtw89_read32_mask(rtwdev, reg, mask);
1044 }
1045
1046 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 data)1047 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
1048 u32 data)
1049 {
1050 u32 reg;
1051
1052 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1053 rtw89_write32(rtwdev, reg, data);
1054 }
1055
1056 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u32 data)1057 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1058 u32 base, u32 mask, u32 data)
1059 {
1060 u32 reg;
1061
1062 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1063 rtw89_write32_mask(rtwdev, reg, mask, data);
1064 }
1065
1066 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u16 data)1067 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1068 u32 base, u32 mask, u16 data)
1069 {
1070 u32 reg;
1071
1072 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1073 rtw89_write16_mask(rtwdev, reg, mask, data);
1074 }
1075
1076 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)1077 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1078 u32 base, u32 bit)
1079 {
1080 u32 reg;
1081
1082 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1083 rtw89_write32_clr(rtwdev, reg, bit);
1084 }
1085
1086 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u16 bit)1087 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1088 u32 base, u16 bit)
1089 {
1090 u32 reg;
1091
1092 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1093 rtw89_write16_clr(rtwdev, reg, bit);
1094 }
1095
1096 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)1097 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1098 u32 base, u32 bit)
1099 {
1100 u32 reg;
1101
1102 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1103 rtw89_write32_set(rtwdev, reg, bit);
1104 }
1105
1106 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1107 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb);
1108 int rtw89_mac_init(struct rtw89_dev *rtwdev);
1109 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1110 enum rtw89_qta_mode ext_mode);
1111 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en);
1112 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1113 enum rtw89_qta_mode mode);
1114 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1115 static inline
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 band,enum rtw89_mac_hwmod_sel sel)1116 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
1117 enum rtw89_mac_hwmod_sel sel)
1118 {
1119 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1120
1121 return mac->check_mac_en(rtwdev, band, sel);
1122 }
1123
1124 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
1125 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
1126 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl);
1127 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
1128 struct rtw89_mac_dle_dfi_quota *quota);
1129 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev);
1130 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
1131 struct rtw89_mac_dle_dfi_qempty *qempty);
1132 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
1133 enum mac_ax_err_info err);
1134 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
1135 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1136 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
1137 struct rtw89_vif *rtwvif,
1138 struct rtw89_vif *rtwvif_src,
1139 u16 offset_tu);
1140 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1141 u64 *tsf);
1142 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
1143 struct rtw89_vif *rtwvif, bool en);
1144 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
1145 struct ieee80211_vif *vif);
1146 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1147 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en);
1148 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
1149 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
1150 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
1151
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)1152 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
1153 {
1154 const struct rtw89_chip_info *chip = rtwdev->chip;
1155
1156 return chip->ops->enable_bb_rf(rtwdev);
1157 }
1158
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)1159 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
1160 {
1161 const struct rtw89_chip_info *chip = rtwdev->chip;
1162
1163 return chip->ops->disable_bb_rf(rtwdev);
1164 }
1165
rtw89_chip_reset_bb_rf(struct rtw89_dev * rtwdev)1166 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev)
1167 {
1168 int ret;
1169
1170 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1171 return 0;
1172
1173 ret = rtw89_chip_disable_bb_rf(rtwdev);
1174 if (ret)
1175 return ret;
1176 ret = rtw89_chip_enable_bb_rf(rtwdev);
1177 if (ret)
1178 return ret;
1179
1180 return 0;
1181 }
1182
1183 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
1184 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
1185 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
1186 u8 class, u8 func);
1187 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1188 u32 len, u8 class, u8 func);
1189 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
1190 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
1191 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1192 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
1193 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1194 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
1195 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1196 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1197 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1198 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1199
1200 static inline
rtw89_mac_cfg_ppdu_status(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)1201 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
1202 {
1203 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1204
1205 return mac->cfg_ppdu_status(rtwdev, mac_idx, enable);
1206 }
1207
1208 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
1209 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1210 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
1211 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
1212 const struct rtw89_mac_ax_coex *coex);
1213 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
1214 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1215 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1216 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1217 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
1218 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1219
1220 static inline
rtw89_mac_cfg_plt(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)1221 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
1222 {
1223 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1224
1225 return mac->cfg_plt(rtwdev, plt);
1226 }
1227
1228 static inline
rtw89_mac_get_plt_cnt(struct rtw89_dev * rtwdev,u8 band)1229 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
1230 {
1231 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1232
1233 return mac->get_plt_cnt(rtwdev, band);
1234 }
1235
1236 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
1237 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
1238 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
1239 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1240 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1241 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl);
1242 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
1243 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
1244
1245 static inline
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1246 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1247 struct ieee80211_sta *sta)
1248 {
1249 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1250
1251 if (mac->bf_assoc)
1252 mac->bf_assoc(rtwdev, vif, sta);
1253 }
1254
1255 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1256 struct ieee80211_sta *sta);
1257 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1258 struct ieee80211_bss_conf *conf);
1259 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
1260 struct ieee80211_sta *sta, bool disconnect);
1261 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
1262 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en);
1263 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1264 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1265 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
1266 struct rtw89_vif *rtwvif, bool en);
1267 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
1268
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)1269 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
1270 {
1271 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1272 return;
1273
1274 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1275 return;
1276
1277 _rtw89_mac_bf_monitor_track(rtwdev);
1278 }
1279
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)1280 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1281 enum rtw89_phy_idx phy_idx,
1282 u32 reg_base, u32 *val)
1283 {
1284 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1285 u32 cr;
1286
1287 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1288 return -EINVAL;
1289
1290 *val = rtw89_read32(rtwdev, cr);
1291 return 0;
1292 }
1293
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)1294 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1295 enum rtw89_phy_idx phy_idx,
1296 u32 reg_base, u32 val)
1297 {
1298 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1299 u32 cr;
1300
1301 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1302 return -EINVAL;
1303
1304 rtw89_write32(rtwdev, cr, val);
1305 return 0;
1306 }
1307
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)1308 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1309 enum rtw89_phy_idx phy_idx,
1310 u32 reg_base, u32 mask, u32 val)
1311 {
1312 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1313 u32 cr;
1314
1315 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1316 return -EINVAL;
1317
1318 rtw89_write32_mask(rtwdev, cr, mask, val);
1319 return 0;
1320 }
1321
rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev * rtwdev,bool enable)1322 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1323 bool enable)
1324 {
1325 const struct rtw89_chip_info *chip = rtwdev->chip;
1326
1327 if (enable)
1328 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1329 B_AX_HCI_TXDMA_EN);
1330 else
1331 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1332 B_AX_HCI_TXDMA_EN);
1333 }
1334
rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev * rtwdev,bool enable)1335 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1336 bool enable)
1337 {
1338 const struct rtw89_chip_info *chip = rtwdev->chip;
1339
1340 if (enable)
1341 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1342 B_AX_HCI_RXDMA_EN);
1343 else
1344 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1345 B_AX_HCI_RXDMA_EN);
1346 }
1347
rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev * rtwdev,bool enable)1348 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1349 bool enable)
1350 {
1351 const struct rtw89_chip_info *chip = rtwdev->chip;
1352
1353 if (enable)
1354 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1355 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1356 else
1357 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1358 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1359 }
1360
rtw89_mac_get_power_state(struct rtw89_dev * rtwdev)1361 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1362 {
1363 u32 val;
1364
1365 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1366 B_AX_WLMAC_PWR_STE_MASK);
1367
1368 return !!val;
1369 }
1370
1371 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1372 bool resume, u32 tx_time);
1373 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1374 u32 *tx_time);
1375 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1376 struct rtw89_sta *rtwsta,
1377 bool resume, u8 tx_retry);
1378 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1379 struct rtw89_sta *rtwsta, u8 *tx_retry);
1380
1381 enum rtw89_mac_xtal_si_offset {
1382 XTAL0 = 0x0,
1383 XTAL3 = 0x3,
1384 XTAL_SI_XTAL_SC_XI = 0x04,
1385 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1386 XTAL_SI_XTAL_SC_XO = 0x05,
1387 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1388 XTAL_SI_XREF_MODE = 0x0B,
1389 XTAL_SI_PWR_CUT = 0x10,
1390 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1391 #define XTAL_SI_BIG_PWR_CUT BIT(1)
1392 XTAL_SI_XTAL_DRV = 0x15,
1393 #define XTAL_SI_DRV_LATCH BIT(4)
1394 XTAL_SI_XTAL_PLL = 0x16,
1395 XTAL_SI_XTAL_XMD_2 = 0x24,
1396 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
1397 XTAL_SI_XTAL_XMD_4 = 0x26,
1398 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1399 XTAL_SI_XREF_RF1 = 0x2D,
1400 XTAL_SI_XREF_RF2 = 0x2E,
1401 XTAL_SI_CV = 0x41,
1402 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1403 XTAL_SI_LOW_ADDR = 0x62,
1404 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1405 XTAL_SI_CTRL = 0x63,
1406 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
1407 #define XTAL_SI_RDY BIT(5)
1408 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1409 XTAL_SI_READ_VAL = 0x7A,
1410 XTAL_SI_WL_RFC_S0 = 0x80,
1411 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1412 #define XTAL_SI_RF00 BIT(0)
1413 XTAL_SI_WL_RFC_S1 = 0x81,
1414 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1415 #define XTAL_SI_RF10 BIT(0)
1416 XTAL_SI_ANAPAR_WL = 0x90,
1417 #define XTAL_SI_SRAM2RFC BIT(7)
1418 #define XTAL_SI_GND_SHDN_WL BIT(6)
1419 #define XTAL_SI_SHDN_WL BIT(5)
1420 #define XTAL_SI_RFC2RF BIT(4)
1421 #define XTAL_SI_OFF_EI BIT(3)
1422 #define XTAL_SI_OFF_WEI BIT(2)
1423 #define XTAL_SI_PON_EI BIT(1)
1424 #define XTAL_SI_PON_WEI BIT(0)
1425 XTAL_SI_SRAM_CTRL = 0xA1,
1426 #define XTAL_SI_SRAM_DIS BIT(1)
1427 #define FULL_BIT_MASK GENMASK(7, 0)
1428 XTAL_SI_APBT = 0xD1,
1429 XTAL_SI_PLL = 0xE0,
1430 XTAL_SI_PLL_1 = 0xE1,
1431 };
1432
1433 static inline
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)1434 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
1435 {
1436 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1437
1438 return mac->write_xtal_si(rtwdev, offset, val, mask);
1439 }
1440
1441 static inline
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)1442 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
1443 {
1444 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1445
1446 return mac->read_xtal_si(rtwdev, offset, val);
1447 }
1448
1449 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1450 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1451 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1452 enum rtw89_mac_idx band);
1453 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1454 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1455 bool band1_en);
1456 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1457 enum rtw89_mac_dle_rsvd_qt_type type,
1458 struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1459 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable);
1460
1461 #endif
1462