Searched refs:MV_BASE (Results 1 – 5 of 5) sorted by relevance
100 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ macro101 #define MV_DDR_CADR_BASE_ARMV7 (MV_BASE + 0x20180)102 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500)103 #define MV_MPP_BASE (MV_BASE + 0x10000)105 #define MV_MISC_BASE (MV_BASE + 0x18200)106 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)113 #define MV_PCI_BASE (MV_BASE + 0x30000)116 #define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000)117 #define MV_PCIE_BASE (MV_BASE + 0x40000)119 #define MV_SDIO_BASE (MV_BASE + 0x90000)
411 #define MV_SCU_BASE (MV_BASE + 0xc000)422 #define MV_PMSU_BASE (MV_BASE + 0x22000)429 #define MV_CPU_RESET_BASE (MV_BASE + 0x20800)434 #define MV_MBUS_CTRL_BASE (MV_BASE + 0x20420)
273 if (fdt_immr_addr(MV_BASE) != 0) in mv_platform_probe_and_attach()
52 #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700)58 #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x)))61 #define MP (MV_BASE + 0x20800)115 pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT; in mv_axp_platform_mp_start_ap()165 bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0); in mv_axp_platform_mp_start_ap()
58 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000)