| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.h | 41 MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
64 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
73 MachineRegisterInfo &MRI) const;
80 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
98 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
147 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | AMDGPURegisterBankInfo.h | 53 MachineRegisterInfo &MRI,
60 Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI,
90 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
100 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI,
106 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
111 const MachineRegisterInfo &MRI,
116 const MachineRegisterInfo &MRI,
121 const MachineRegisterInfo &MRI,
145 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
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| H A D | GCNRegPressure.h | 26 class MachineRegisterInfo; variable
71 const MachineRegisterInfo &MRI);
105 static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI);
143 mutable const MachineRegisterInfo *MRI = nullptr;
165 const MachineRegisterInfo &MRI);
175 void reset(const MachineRegisterInfo &MRI, SlotIndex SI) { in reset()
253 const MachineRegisterInfo &MRI);
256 const MachineRegisterInfo &MRI);
259 const MachineRegisterInfo &MRI);
318 GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, in getRegPressure()
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| H A D | SIRegisterInfo.h | 207 bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
284 MCRegister findUnusedRegister(const MachineRegisterInfo &MRI,
289 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
292 getRegClassForOperandReg(const MachineRegisterInfo &MRI,
295 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
296 bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
297 bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const { in isVectorRegister()
309 bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI,
343 const MachineRegisterInfo &MRI) const override;
368 MachineRegisterInfo &MRI,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 41 class MachineRegisterInfo; variable
94 Register constrainRegToClass(MachineRegisterInfo &MRI,
109 MachineRegisterInfo &MRI,
128 MachineRegisterInfo &MRI,
198 Register VReg, const MachineRegisterInfo &MRI,
220 const MachineRegisterInfo &MRI);
274 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef()
442 const MachineRegisterInfo &MRI,
448 const MachineRegisterInfo &MRI,
472 const MachineRegisterInfo &MRI,
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| H A D | MIPatternMatch.h | 41 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
55 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
84 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
119 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
145 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
159 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
398 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
422 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
558 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
652 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
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| H A D | LoadStoreOpt.h | 35 class MachineRegisterInfo; variable
58 BaseIndexOffset getPointerInfo(Register Ptr, MachineRegisterInfo &MRI);
64 bool &IsAlias, MachineRegisterInfo &MRI);
71 MachineRegisterInfo &MRI, AliasAnalysis *AA);
85 MachineRegisterInfo *MRI = nullptr;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 41 void MachineRegisterInfo::Delegate::anchor() {} in anchor()
43 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) in MachineRegisterInfo() function in MachineRegisterInfo
62 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
68 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass()
91 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs()
121 MachineRegisterInfo::recomputeRegClass(Register Reg) { in recomputeRegClass()
179 void MachineRegisterInfo::setType(Register VReg, LLT Ty) { in setType()
198 void MachineRegisterInfo::clearVirtRegs() { in clearVirtRegs()
255 void MachineRegisterInfo::verifyUseLists() const { in verifyUseLists()
333 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, in moveOperands()
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| H A D | MIRVRegNamerUtils.h | 29 class MachineRegisterInfo; variable
48 MachineRegisterInfo &MRI;
85 VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {} in VRegRenamer()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.h | 37 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
39 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
42 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeFunnelShift(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeCTPOP(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeAtomicCmpxchg128(MachineInstr &MI, MachineRegisterInfo &MRI,
64 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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| H A D | AArch64PostLegalizerLowering.cpp | 230 bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV()
259 bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN()
280 bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP()
296 bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip()
354 MachineRegisterInfo &MRI, in matchDupFromBuildVector()
369 bool matchDup(MachineInstr &MI, MachineRegisterInfo &MRI, in matchDup()
415 bool matchEXT(MachineInstr &MI, MachineRegisterInfo &MRI, in matchEXT()
482 bool matchINS(MachineInstr &MI, MachineRegisterInfo &MRI, in matchINS()
668 MachineInstr &MI, const MachineRegisterInfo &MRI, in matchAdjustICmpImmAndPred()
685 MachineRegisterInfo &MRI = *MIB.getMRI(); in applyAdjustICmpImmAndPred()
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| H A D | AArch64GlobalISelUtils.h | 35 getAArch64VectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI);
41 const MachineRegisterInfo &MRI);
46 const MachineRegisterInfo &MRI);
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| H A D | AArch64PostLegalizerCombiner.cpp | 67 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd()
110 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyExtractVecEltPairwiseAdd()
125 bool isSignExtended(Register R, MachineRegisterInfo &MRI) { in isSignExtended()
131 bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended()
137 MachineInstr &MI, MachineRegisterInfo &MRI, in matchAArch64MulConstCombine()
250 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyAArch64MulConstCombine()
259 bool matchFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchFoldMergeToZext()
267 void applyFoldMergeToZext(MachineInstr &MI, MachineRegisterInfo &MRI, in applyFoldMergeToZext()
323 void applySplitStoreZero128(MachineInstr &MI, MachineRegisterInfo &MRI, in applySplitStoreZero128()
343 bool matchOrToBSP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchOrToBSP()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 44 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass()
56 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
108 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
161 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands()
200 MachineRegisterInfo &MRI) { in canReplaceReg()
483 MachineRegisterInfo &MRI) { in extractParts()
493 MachineRegisterInfo &MRI) { in extractParts()
587 MachineRegisterInfo &MRI) { in extractVectorParts()
886 MachineRegisterInfo &MRI = MF.getRegInfo(); in getFunctionLiveInPhysReg()
1432 const MachineRegisterInfo &MRI, Register Reg, in matchUnaryPredicate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 28 class MachineRegisterInfo; variable
133 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
136 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
139 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
142 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
145 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
148 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
151 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
154 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
157 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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| H A D | RDFDeadCode.h | 31 class MachineRegisterInfo; variable
35 DeadCodeElimination(DataFlowGraph &dfg, MachineRegisterInfo &mri) in DeadCodeElimination()
53 MachineRegisterInfo &MRI;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 52 MachineRegisterInfo &MRI) { in IsRegInClass()
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
78 bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSSReg()
86 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in processBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVRegisterBankInfo.h | 44 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
48 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
52 bool anyUseOnlyUseFP(Register Def, const MachineRegisterInfo &MRI,
56 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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| H A D | RISCVInstructionSelector.cpp | 62 MachineRegisterInfo &MRI);
65 MachineRegisterInfo &MRI);
70 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
79 MachineRegisterInfo &MRI) const;
167 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectShiftMask()
235 MachineRegisterInfo &MRI = MF.getRegInfo(); in selectSHXADDOp()
335 MachineRegisterInfo &MRI = MF.getRegInfo(); in selectSHXADD_UWOp()
373 MachineRegisterInfo &MRI = MF.getRegInfo(); in selectAddrRegImm()
500 MachineRegisterInfo &MRI = MF.getRegInfo(); in select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 64 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
67 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
70 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
72 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
74 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
127 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr()
175 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift()
189 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate()
224 void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI, in processDstReg()
285 void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI, in processInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 88 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
96 bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
104 bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
106 bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
120 bool selectSelect(MachineInstr &I, MachineRegisterInfo &MRI,
353 MachineRegisterInfo &MRI = MF.getRegInfo(); in select()
524 const MachineRegisterInfo &MRI, in X86SelectAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 66 MachineRegisterInfo *MRI;
105 const MachineRegisterInfo *MRI) { in isGPR64()
114 const MachineRegisterInfo *MRI) { in isFPR64()
128 const MachineRegisterInfo *MRI, in getSrcFromCopy()
209 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
222 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
241 for (MachineRegisterInfo::use_instr_nodbg_iterator in isProfitableToTransform()
302 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
321 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 33 class MachineRegisterInfo; variable
291 MachineRegisterInfo &MRI;
325 MachineRegisterInfo &MRI);
336 MachineRegisterInfo &getMRI() const { return MRI; } in getMRI()
556 const MachineRegisterInfo &MRI) const;
599 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
667 MachineRegisterInfo &MRI);
752 TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
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| H A D | DetectDeadLanes.h | 39 class MachineRegisterInfo; variable
51 DeadLaneDetector(const MachineRegisterInfo *MRI,
98 const MachineRegisterInfo *MRI;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.h | 81 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
86 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
90 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
|