1 /*- 2 ******************************************************************************** 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @{ 39 * @file al_hal_nb_regs.h 40 * 41 * @brief North Bridge service registers 42 * 43 */ 44 45 #ifndef __AL_HAL_NB_REGS_H__ 46 #define __AL_HAL_NB_REGS_H__ 47 48 #include "al_hal_plat_types.h" 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 /* 54 * Unit Registers 55 */ 56 57 58 59 struct al_nb_global { 60 /* [0x0] */ 61 uint32_t cpus_config; 62 /* [0x4] */ 63 uint32_t cpus_secure; 64 /* [0x8] Force init reset. */ 65 uint32_t cpus_init_control; 66 /* [0xc] Force init reset per DECEI mode. */ 67 uint32_t cpus_init_status; 68 /* [0x10] */ 69 uint32_t nb_int_cause; 70 /* [0x14] */ 71 uint32_t sev_int_cause; 72 /* [0x18] */ 73 uint32_t pmus_int_cause; 74 /* [0x1c] */ 75 uint32_t sev_mask; 76 /* [0x20] */ 77 uint32_t cpus_hold_reset; 78 /* [0x24] */ 79 uint32_t cpus_software_reset; 80 /* [0x28] */ 81 uint32_t wd_timer0_reset; 82 /* [0x2c] */ 83 uint32_t wd_timer1_reset; 84 /* [0x30] */ 85 uint32_t wd_timer2_reset; 86 /* [0x34] */ 87 uint32_t wd_timer3_reset; 88 /* [0x38] */ 89 uint32_t ddrc_hold_reset; 90 /* [0x3c] */ 91 uint32_t fabric_software_reset; 92 /* [0x40] */ 93 uint32_t cpus_power_ctrl; 94 uint32_t rsrvd_0[7]; 95 /* [0x60] */ 96 uint32_t acf_base_high; 97 /* [0x64] */ 98 uint32_t acf_base_low; 99 /* [0x68] */ 100 uint32_t acf_control_override; 101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */ 102 uint32_t lgic_base_high; 103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */ 104 uint32_t lgic_base_low; 105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */ 106 uint32_t iogic_base_high; 107 /* [0x78] Read-only that reflects IOGIC base low address */ 108 uint32_t iogic_base_low; 109 /* [0x7c] */ 110 uint32_t io_wr_split_control; 111 /* [0x80] */ 112 uint32_t io_rd_rob_control; 113 /* [0x84] */ 114 uint32_t sb_pos_error_log_1; 115 /* [0x88] */ 116 uint32_t sb_pos_error_log_0; 117 /* [0x8c] */ 118 uint32_t c2swb_config; 119 /* [0x90] */ 120 uint32_t msix_error_log; 121 /* [0x94] */ 122 uint32_t error_cause; 123 /* [0x98] */ 124 uint32_t error_mask; 125 uint32_t rsrvd_1; 126 /* [0xa0] */ 127 uint32_t qos_peak_control; 128 /* [0xa4] */ 129 uint32_t qos_set_control; 130 /* [0xa8] */ 131 uint32_t ddr_qos; 132 uint32_t rsrvd_2[9]; 133 /* [0xd0] */ 134 uint32_t acf_misc; 135 /* [0xd4] */ 136 uint32_t config_bus_control; 137 uint32_t rsrvd_3[2]; 138 /* [0xe0] */ 139 uint32_t pos_id_match; 140 uint32_t rsrvd_4[3]; 141 /* [0xf0] */ 142 uint32_t sb_sel_override_awuser; 143 /* [0xf4] */ 144 uint32_t sb_override_awuser; 145 /* [0xf8] */ 146 uint32_t sb_sel_override_aruser; 147 /* [0xfc] */ 148 uint32_t sb_override_aruser; 149 /* [0x100] */ 150 uint32_t cpu_max_pd_timer; 151 /* [0x104] */ 152 uint32_t cpu_max_pu_timer; 153 uint32_t rsrvd_5[2]; 154 /* [0x110] */ 155 uint32_t auto_ddr_self_refresh_counter; 156 uint32_t rsrvd_6[3]; 157 /* [0x120] */ 158 uint32_t coresight_pd; 159 /* [0x124] */ 160 uint32_t coresight_internal_0; 161 /* [0x128] */ 162 uint32_t coresight_dbgromaddr; 163 /* [0x12c] */ 164 uint32_t coresight_dbgselfaddr; 165 /* [0x130] */ 166 uint32_t coresght_targetid; 167 /* [0x134] */ 168 uint32_t coresght_targetid0; 169 uint32_t rsrvd_7[10]; 170 /* [0x160] */ 171 uint32_t sb_force_same_id_cfg_0; 172 /* [0x164] */ 173 uint32_t sb_mstr_force_same_id_sel_0; 174 /* [0x168] */ 175 uint32_t sb_force_same_id_cfg_1; 176 /* [0x16c] */ 177 uint32_t sb_mstr_force_same_id_sel_1; 178 uint32_t rsrvd[932]; 179 }; 180 struct al_nb_system_counter { 181 /* [0x0] */ 182 uint32_t cnt_control; 183 /* [0x4] */ 184 uint32_t cnt_base_freq; 185 /* [0x8] */ 186 uint32_t cnt_low; 187 /* [0xc] */ 188 uint32_t cnt_high; 189 /* [0x10] */ 190 uint32_t cnt_init_low; 191 /* [0x14] */ 192 uint32_t cnt_init_high; 193 uint32_t rsrvd[58]; 194 }; 195 struct al_nb_rams_control_misc { 196 /* [0x0] */ 197 uint32_t ca15_rf_misc; 198 uint32_t rsrvd_0; 199 /* [0x8] */ 200 uint32_t nb_rf_misc; 201 uint32_t rsrvd[61]; 202 }; 203 struct al_nb_ca15_rams_control { 204 /* [0x0] */ 205 uint32_t rf_0; 206 /* [0x4] */ 207 uint32_t rf_1; 208 /* [0x8] */ 209 uint32_t rf_2; 210 uint32_t rsrvd; 211 }; 212 struct al_nb_semaphores { 213 /* [0x0] This configuration is only sampled during reset of the processor */ 214 uint32_t lockn; 215 }; 216 struct al_nb_debug { 217 /* [0x0] */ 218 uint32_t ca15_outputs_1; 219 /* [0x4] */ 220 uint32_t ca15_outputs_2; 221 uint32_t rsrvd_0[2]; 222 /* [0x10] */ 223 uint32_t cpu_msg[4]; 224 /* [0x20] */ 225 uint32_t rsv0_config; 226 /* [0x24] */ 227 uint32_t rsv1_config; 228 uint32_t rsrvd_1[2]; 229 /* [0x30] */ 230 uint32_t rsv0_status; 231 /* [0x34] */ 232 uint32_t rsv1_status; 233 uint32_t rsrvd_2[2]; 234 /* [0x40] */ 235 uint32_t ddrc; 236 /* [0x44] */ 237 uint32_t ddrc_phy_smode_control; 238 /* [0x48] */ 239 uint32_t ddrc_phy_smode_status; 240 uint32_t rsrvd_3[5]; 241 /* [0x60] */ 242 uint32_t pmc; 243 uint32_t rsrvd_4[3]; 244 /* [0x70] */ 245 uint32_t cpus_general; 246 /* [0x74] */ 247 uint32_t cpus_general_1; 248 uint32_t rsrvd_5[2]; 249 /* [0x80] */ 250 uint32_t cpus_int_out; 251 uint32_t rsrvd_6[3]; 252 /* [0x90] */ 253 uint32_t latch_pc_req; 254 uint32_t rsrvd_7; 255 /* [0x98] */ 256 uint32_t latch_pc_low; 257 /* [0x9c] */ 258 uint32_t latch_pc_high; 259 uint32_t rsrvd_8[24]; 260 /* [0x100] */ 261 uint32_t track_dump_ctrl; 262 /* [0x104] */ 263 uint32_t track_dump_rdata_0; 264 /* [0x108] */ 265 uint32_t track_dump_rdata_1; 266 uint32_t rsrvd_9[5]; 267 /* [0x120] */ 268 uint32_t track_events; 269 uint32_t rsrvd_10[3]; 270 /* [0x130] */ 271 uint32_t pos_track_dump_ctrl; 272 /* [0x134] */ 273 uint32_t pos_track_dump_rdata_0; 274 /* [0x138] */ 275 uint32_t pos_track_dump_rdata_1; 276 uint32_t rsrvd_11; 277 /* [0x140] */ 278 uint32_t c2swb_track_dump_ctrl; 279 /* [0x144] */ 280 uint32_t c2swb_track_dump_rdata_0; 281 /* [0x148] */ 282 uint32_t c2swb_track_dump_rdata_1; 283 uint32_t rsrvd_12; 284 /* [0x150] */ 285 uint32_t cpus_track_dump_ctrl; 286 /* [0x154] */ 287 uint32_t cpus_track_dump_rdata_0; 288 /* [0x158] */ 289 uint32_t cpus_track_dump_rdata_1; 290 uint32_t rsrvd_13; 291 /* [0x160] */ 292 uint32_t c2swb_bar_ovrd_high; 293 /* [0x164] */ 294 uint32_t c2swb_bar_ovrd_low; 295 uint32_t rsrvd[38]; 296 }; 297 struct al_nb_cpun_config_status { 298 /* [0x0] This configuration is only sampled during reset of the processor. */ 299 uint32_t config; 300 /* [0x4] This configuration is only sampled during reset of the processor. */ 301 uint32_t config_aarch64; 302 /* [0x8] */ 303 uint32_t local_cause_mask; 304 uint32_t rsrvd_0; 305 /* [0x10] */ 306 uint32_t pmus_cause_mask; 307 /* [0x14] */ 308 uint32_t sei_cause_mask; 309 uint32_t rsrvd_1[2]; 310 /* [0x20] Specifies the state of the CPU with reference to power modes. */ 311 uint32_t power_ctrl; 312 /* [0x24] */ 313 uint32_t power_status; 314 /* [0x28] */ 315 uint32_t resume_addr_l; 316 /* [0x2c] */ 317 uint32_t resume_addr_h; 318 uint32_t rsrvd_2[4]; 319 /* [0x40] */ 320 uint32_t warm_rst_ctl; 321 uint32_t rsrvd_3; 322 /* [0x48] */ 323 uint32_t rvbar_low; 324 /* [0x4c] */ 325 uint32_t rvbar_high; 326 /* [0x50] */ 327 uint32_t pmu_snapshot; 328 uint32_t rsrvd_4[3]; 329 /* [0x60] */ 330 uint32_t cpu_msg_in; 331 uint32_t rsrvd[39]; 332 }; 333 struct al_nb_mc_pmu { 334 /* [0x0] PMU Global Control Register */ 335 uint32_t pmu_control; 336 /* [0x4] PMU Global Control Register */ 337 uint32_t overflow; 338 uint32_t rsrvd[62]; 339 }; 340 struct al_nb_mc_pmu_counters { 341 /* [0x0] Counter Configuration Register */ 342 uint32_t cfg; 343 /* [0x4] Counter Control Register */ 344 uint32_t cntl; 345 /* [0x8] Counter Control Register */ 346 uint32_t low; 347 /* [0xc] Counter Control Register */ 348 uint32_t high; 349 uint32_t rsrvd[4]; 350 }; 351 struct al_nb_nb_version { 352 /* [0x0] Northbridge Revision */ 353 uint32_t version; 354 uint32_t rsrvd; 355 }; 356 struct al_nb_sriov { 357 /* [0x0] */ 358 uint32_t cpu_tgtid[4]; 359 uint32_t rsrvd[4]; 360 }; 361 struct al_nb_dram_channels { 362 /* [0x0] */ 363 uint32_t dram_0_control; 364 uint32_t rsrvd_0; 365 /* [0x8] */ 366 uint32_t dram_0_status; 367 uint32_t rsrvd_1; 368 /* [0x10] */ 369 uint32_t ddr_int_cause; 370 uint32_t rsrvd_2; 371 /* [0x18] */ 372 uint32_t ddr_cause_mask; 373 uint32_t rsrvd_3; 374 /* [0x20] */ 375 uint32_t address_map; 376 uint32_t rsrvd_4[3]; 377 /* [0x30] */ 378 uint32_t reorder_id_mask_0; 379 /* [0x34] */ 380 uint32_t reorder_id_value_0; 381 /* [0x38] */ 382 uint32_t reorder_id_mask_1; 383 /* [0x3c] */ 384 uint32_t reorder_id_value_1; 385 /* [0x40] */ 386 uint32_t reorder_id_mask_2; 387 /* [0x44] */ 388 uint32_t reorder_id_value_2; 389 /* [0x48] */ 390 uint32_t reorder_id_mask_3; 391 /* [0x4c] */ 392 uint32_t reorder_id_value_3; 393 /* [0x50] */ 394 uint32_t mrr_control_status; 395 uint32_t rsrvd[43]; 396 }; 397 struct al_nb_ddr_0_mrr { 398 /* [0x0] Counter Configuration Register */ 399 uint32_t val; 400 }; 401 struct al_nb_push_packet { 402 /* [0x0] */ 403 uint32_t pp_config; 404 uint32_t rsrvd_0[3]; 405 /* [0x10] */ 406 uint32_t pp_ext_attr; 407 uint32_t rsrvd_1[3]; 408 /* [0x20] */ 409 uint32_t pp_base_low; 410 /* [0x24] */ 411 uint32_t pp_base_high; 412 uint32_t rsrvd_2[2]; 413 /* [0x30] */ 414 uint32_t pp_sel_attr; 415 uint32_t rsrvd[51]; 416 }; 417 418 struct al_nb_regs { 419 struct al_nb_global global; /* [0x0] */ 420 struct al_nb_system_counter system_counter; /* [0x1000] */ 421 struct al_nb_rams_control_misc rams_control_misc; /* [0x1100] */ 422 struct al_nb_ca15_rams_control ca15_rams_control[5]; /* [0x1200] */ 423 uint32_t rsrvd_0[108]; 424 struct al_nb_semaphores semaphores[64]; /* [0x1400] */ 425 uint32_t rsrvd_1[320]; 426 struct al_nb_debug debug; /* [0x1a00] */ 427 uint32_t rsrvd_2[256]; 428 struct al_nb_cpun_config_status cpun_config_status[4]; /* [0x2000] */ 429 uint32_t rsrvd_3[1792]; 430 struct al_nb_mc_pmu mc_pmu; /* [0x4000] */ 431 struct al_nb_mc_pmu_counters mc_pmu_counters[4]; /* [0x4100] */ 432 uint32_t rsrvd_4[160]; 433 struct al_nb_nb_version nb_version; /* [0x4400] */ 434 uint32_t rsrvd_5[126]; 435 struct al_nb_sriov sriov; /* [0x4600] */ 436 uint32_t rsrvd_6[120]; 437 struct al_nb_dram_channels dram_channels; /* [0x4800] */ 438 struct al_nb_ddr_0_mrr ddr_0_mrr[9]; /* [0x4900] */ 439 uint32_t rsrvd_7[439]; 440 uint32_t rsrvd_8[1024]; /* [0x5000] */ 441 struct al_nb_push_packet push_packet; /* [0x6000] */ 442 }; 443 444 445 /* 446 * Registers Fields 447 */ 448 449 450 /**** CPUs_Config register ****/ 451 /* Disable broadcast of barrier onto system bus. 452 Connect to Processor Cluster SYSBARDISABLE. */ 453 #define NB_GLOBAL_CPUS_CONFIG_SYSBARDISABLE (1 << 0) 454 /* Enable broadcast of inner shareable transactions from CPUs. 455 Connect to Processor Cluster BROADCASTINNER. */ 456 #define NB_GLOBAL_CPUS_CONFIG_BROADCASTINNER (1 << 1) 457 /* Disable broadcast of cache maintenance system bus. 458 Connect to Processor Cluster BROADCASTCACHEMAIN */ 459 #define NB_GLOBAL_CPUS_CONFIG_BROADCASTCACHEMAINT (1 << 2) 460 /* Enable broadcast of outer shareable transactions from CPUs. 461 Connect to Processor Cluster BROADCASTOUTER. */ 462 #define NB_GLOBAL_CPUS_CONFIG_BROADCASTOUTER (1 << 3) 463 /* Defines the internal CPU GIC operating frequency ratio with the main CPU clock. 464 0x0: 1:1 465 0x1: 1:2 466 0x2: 1:3 467 0x3: 1:4 468 469 Note: This is not in used with CA57 */ 470 #define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_MASK 0x00000030 471 #define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_SHIFT 4 472 /* Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ 473 signals directly to the processor: 474 0 Enable the GIC CPU interface logic. 475 1 Disable the GIC CPU interface logic. 476 The processor only samples this signal as it exits reset. */ 477 #define NB_GLOBAL_CPUS_CONFIG_GIC_DISABLE (1 << 6) 478 /* Disable L1 data cache and L2 snoop tag RAMs automatic invalidate on reset functionality */ 479 #define NB_GLOBAL_CPUS_CONFIG_DBG_L1_RESET_DISABLE (1 << 7) 480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity 481 Register (MPIDR). 482 This signal is only sampled during reset of the processor. */ 483 #define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_MASK 0x00FF0000 484 #define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_SHIFT 16 485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity 486 Register (MPIDR). 487 This signal is only sampled during reset of the processor.. */ 488 #define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_MASK 0xFF000000 489 #define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_SHIFT 24 490 491 /**** CPUs_Secure register ****/ 492 /* DBGEN 493 */ 494 #define NB_GLOBAL_CPUS_SECURE_DBGEN (1 << 0) 495 /* NIDEN 496 */ 497 #define NB_GLOBAL_CPUS_SECURE_NIDEN (1 << 1) 498 /* SPIDEN 499 */ 500 #define NB_GLOBAL_CPUS_SECURE_SPIDEN (1 << 2) 501 /* SPNIDEN 502 */ 503 #define NB_GLOBAL_CPUS_SECURE_SPNIDEN (1 << 3) 504 /* Disable write access to some secure GIC registers */ 505 #define NB_GLOBAL_CPUS_SECURE_CFGSDISABLE (1 << 4) 506 /* Disable write access to some secure IOGIC registers */ 507 #define NB_GLOBAL_CPUS_SECURE_IOGIC_CFGSDISABLE (1 << 5) 508 509 /**** CPUs_Init_Control register ****/ 510 /* CPU Init Done 511 Specifies which CPUs' inits are done and can exit poreset. 512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other CPUs. 513 If this bit is cleared for a specific CPU, setting it by primary CPU as part of the initialization process will initiate power-on-reset to this specific CPU. */ 514 #define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_MASK 0x0000000F 515 #define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_SHIFT 0 516 /* DBGPWRDNREQ Mask 517 When CPU does not exist, its DBGPWRDNREQ must be asserted. 518 If corresponding mask bit is set, the DBGPWDNREQ is deasserted. */ 519 #define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_MASK 0x000000F0 520 #define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_SHIFT 4 521 /* Force CPU init power-on-reset exit. 522 For debug purposes only. */ 523 #define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_MASK 0x00000F00 524 #define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_SHIFT 8 525 /* Force dbgpwrdup signal high 526 If dbgpwrdup is clear on the processor interface it indicates that the process debug resources are not available for APB access. */ 527 #define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_MASK 0x0000F000 528 #define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_SHIFT 12 529 530 /**** CPUs_Init_Status register ****/ 531 /* Specifies which CPUs are enabled in the device configuration. 532 sample at rst_cpus_exist[3:0] reset strap. */ 533 #define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_MASK 0x0000000F 534 #define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_SHIFT 0 535 536 /**** NB_Int_Cause register ****/ 537 /* 538 * Each bit corresponds to an IRQ. 539 * value is 1 for level irq, 0 for trigger irq 540 * Level IRQ indices: 12-13, 23, 24, 26-29 541 */ 542 #define NB_GLOBAL_NB_INT_CAUSE_LEVEL_IRQ_MASK 0x3D803000 543 /* Cross trigger interrupt */ 544 #define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_MASK 0x0000000F 545 #define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_SHIFT 0 546 /* Communications channel receive. Receive portion of Data Transfer Register full flag */ 547 #define NB_GLOBAL_NB_INT_CAUSE_COMMRX_MASK 0x000000F0 548 #define NB_GLOBAL_NB_INT_CAUSE_COMMRX_SHIFT 4 549 /* Communication channel transmit. Transmit portion of Data Transfer Register empty flag. */ 550 #define NB_GLOBAL_NB_INT_CAUSE_COMMTX_MASK 0x00000F00 551 #define NB_GLOBAL_NB_INT_CAUSE_COMMTX_SHIFT 8 552 /* Reserved, read undefined must write as zeros. */ 553 #define NB_GLOBAL_NB_INT_CAUSE_RESERVED_15_15 (1 << 15) 554 /* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator connected to CA15 nAXIERRIRQ. */ 555 #define NB_GLOBAL_NB_INT_CAUSE_CPU_AXIERRIRQ (1 << 16) 556 /* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */ 557 #define NB_GLOBAL_NB_INT_CAUSE_CPU_INTERRIRQ (1 << 17) 558 /* Coherent fabric error summary interrupt */ 559 #define NB_GLOBAL_NB_INT_CAUSE_ACF_ERRORIRQ (1 << 18) 560 /* DDR Controller ECC Correctable error summary interrupt */ 561 #define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_CORR_ERR (1 << 19) 562 /* DDR Controller ECC Uncorrectable error summary interrupt */ 563 #define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_UNCORR_ERR (1 << 20) 564 /* DRAM parity error interrupt */ 565 #define NB_GLOBAL_NB_INT_CAUSE_MCTL_PARITY_ERR (1 << 21) 566 /* Reserved, not functional */ 567 #define NB_GLOBAL_NB_INT_CAUSE_MCTL_WDATARAM_PAR (1 << 22) 568 /* Error cause summary interrupt */ 569 #define NB_GLOBAL_NB_INT_CAUSE_ERR_CAUSE_SUM_A0 (1 << 23) 570 /* SB PoS error */ 571 #define NB_GLOBAL_NB_INT_CAUSE_SB_POS_ERR (1 << 24) 572 /* Received msix is not mapped to local GIC or IO-GIC spin */ 573 #define NB_GLOBAL_NB_INT_CAUSE_MSIX_ERR_INT_M0 (1 << 25) 574 /* Coresight timestamp overflow */ 575 #define NB_GLOBAL_NB_INT_CAUSE_CORESIGHT_TS_OVERFLOW_M0 (1 << 26) 576 577 /**** SEV_Int_Cause register ****/ 578 /* SMMU 0/1 global non-secure fault interrupt */ 579 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_MASK 0x00000003 580 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_SHIFT 0 581 /* SMMU 0/1 non-secure context interrupt */ 582 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CXT_IRPT_NS_MASK 0x0000000C 583 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CXT_IRPT_NS_SHIFT 2 584 /* SMMU0/1 Non-secure configuration access fault interrupt */ 585 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CFG_FLT_IRPT_S_MASK 0x00000030 586 #define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CFG_FLT_IRPT_S_SHIFT 4 587 /* Reserved. Read undefined; must write as zeros. */ 588 #define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_11_6_MASK 0x00000FC0 589 #define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_11_6_SHIFT 6 590 /* Reserved. Read undefined; must write as zeros. */ 591 #define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_31_20_MASK 0xFFF00000 592 #define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_31_20_SHIFT 20 593 594 /**** PMUs_Int_Cause register ****/ 595 /* CPUs PMU Overflow interrupt */ 596 #define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_MASK 0x0000000F 597 #define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_SHIFT 0 598 /* Northbridge PMU overflow */ 599 #define NB_GLOBAL_PMUS_INT_CAUSE_NB_OVFL (1 << 4) 600 /* Memory Controller PMU overflow */ 601 #define NB_GLOBAL_PMUS_INT_CAUSE_MCTL_OVFL (1 << 5) 602 /* Coherency Interconnect PMU overflow */ 603 #define NB_GLOBAL_PMUS_INT_CAUSE_CCI_OVFL_MASK 0x000007C0 604 #define NB_GLOBAL_PMUS_INT_CAUSE_CCI_OVFL_SHIFT 6 605 /* Coherency Interconnect PMU overflow */ 606 #define NB_GLOBAL_PMUS_INT_CAUSE_SMMU_OVFL_MASK 0x00001800 607 #define NB_GLOBAL_PMUS_INT_CAUSE_SMMU_OVFL_SHIFT 11 608 /* Reserved. Read undefined; must write as zeros. */ 609 #define NB_GLOBAL_PMUS_INT_CAUSE_RESERVED_23_13_MASK 0x00FFE000 610 #define NB_GLOBAL_PMUS_INT_CAUSE_RESERVED_23_13_SHIFT 13 611 /* Southbridge PMUs overflow */ 612 #define NB_GLOBAL_PMUS_INT_CAUSE_SB_PMUS_OVFL_MASK 0xFF000000 613 #define NB_GLOBAL_PMUS_INT_CAUSE_SB_PMUS_OVFL_SHIFT 24 614 615 /**** CPUs_Hold_Reset register ****/ 616 /* Shared L2 memory system, interrupt controller and timer logic reset. 617 Reset is applied only when all processors are in STNDBYWFI state. */ 618 #define NB_GLOBAL_CPUS_HOLD_RESET_L2RESET (1 << 0) 619 /* Shared debug domain reset */ 620 #define NB_GLOBAL_CPUS_HOLD_RESET_PRESETDBG (1 << 1) 621 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */ 622 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_DBGRESET_MASK 0x000000F0 623 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_DBGRESET_SHIFT 4 624 /* Individual CPU core and VFP/NEON logic reset. 625 Reset is applied only when specific CPU is in STNDBYWFI state. */ 626 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_CORERESET_MASK 0x00000F00 627 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_CORERESET_SHIFT 8 628 /* Individual CPU por-on-reset. 629 Reset is applied only when specific CPU is in STNDBYWFI state. */ 630 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_PORESET_MASK 0x0000F000 631 #define NB_GLOBAL_CPUS_HOLD_RESET_CPU_PORESET_SHIFT 12 632 /* Wait for interrupt mask. 633 If set, reset is applied without waiting for the specified CPU's STNDBYWFI state. */ 634 #define NB_GLOBAL_CPUS_HOLD_RESET_WFI_MASK_MASK 0x000F0000 635 #define NB_GLOBAL_CPUS_HOLD_RESET_WFI_MASK_SHIFT 16 636 637 /**** CPUs_Software_Reset register ****/ 638 /* Write 1. Apply the software reset. */ 639 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_SWRESET_REQ (1 << 0) 640 /* Defines the level of software reset. 641 0x0 - cpu_core: Individual CPU core reset. 642 0x1 - cpu_poreset: Individual CPU power-on-reset. 643 0x2 - cpu_dbg: Individual CPU debug reset. 644 0x3 - cluster_no_dbg: A Cluster reset puts each core into core reset (no dbg) and also resets the interrupt controller and L2 logic. 645 0x4 - cluster: A Cluster reset puts each core into power-on-reset and also resets the interrupt controller and L2 logic. Debug is active. 646 0x5 - cluster_poreset: A Cluster power-on-reset puts each core into power-on-reset and also resets the interrupt controller and L2 logic. This include the cluster debug logic. */ 647 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_MASK 0x0000000E 648 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT 1 649 /* Individual CPU core reset. */ 650 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_CORE \ 651 (0x0 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT) 652 /* Individual CPU power-on-reset. */ 653 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_PORESET \ 654 (0x1 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT) 655 /* Individual CPU debug reset. */ 656 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_DBG \ 657 (0x2 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT) 658 /* A Cluster reset puts each core into core reset (no dbg) and a ... */ 659 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER_NO_DBG \ 660 (0x3 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT) 661 /* A Cluster reset puts each core into power-on-reset and also r ... */ 662 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER \ 663 (0x4 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT) 664 /* A Cluster power-on-reset puts each core into power-on-reset a ... */ 665 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER_PORESET \ 666 (0x5 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT) 667 /* Defines which cores to reset when no cluster_poreset is requested. */ 668 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_CORES_MASK 0x000000F0 669 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_CORES_SHIFT 4 670 /* CPUn wait for interrupt enable. 671 Defines which CPU WFI indication to wait for before applying the software reset. */ 672 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000 673 #define NB_GLOBAL_CPUS_SOFTWARE_RESET_WFI_MASK_SHIFT 16 674 675 /**** WD_Timer0_Reset register ****/ 676 /* Shared L2 memory system, interrupt controller and timer logic reset */ 677 #define NB_GLOBAL_WD_TIMER0_RESET_L2RESET (1 << 0) 678 /* Shared debug domain reset */ 679 #define NB_GLOBAL_WD_TIMER0_RESET_PRESETDBG (1 << 1) 680 /* Individual CPU debug PTM, watchpoint and breakpoint logic reset */ 681 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_DBGRESET_MASK 0x000000F0 682 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_DBGRESET_SHIFT 4 683 /* Individual CPU core and VFP/NEON logic reset */ 684 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_CORERESET_MASK 0x00000F00 685 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_CORERESET_SHIFT 8 686 /* Individual CPU por-on-reset */ 687 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_PORESET_MASK 0x0000F000 688 #define NB_GLOBAL_WD_TIMER0_RESET_CPU_PORESET_SHIFT 12 689 690 /**** WD_Timer1_Reset register ****/ 691 /* Shared L2 memory system, interrupt controller and timer logic reset */ 692 #define NB_GLOBAL_WD_TIMER1_RESET_L2RESET (1 << 0) 693 /* Shared debug domain reset */ 694 #define NB_GLOBAL_WD_TIMER1_RESET_PRESETDBG (1 << 1) 695 /* Individual CPU debug PTM, watchpoint and breakpoint logic reset */ 696 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_DBGRESET_MASK 0x000000F0 697 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_DBGRESET_SHIFT 4 698 /* Individual CPU core and VFP/NEON logic reset */ 699 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_CORERESET_MASK 0x00000F00 700 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_CORERESET_SHIFT 8 701 /* Individual CPU por-on-reset */ 702 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_PORESET_MASK 0x0000F000 703 #define NB_GLOBAL_WD_TIMER1_RESET_CPU_PORESET_SHIFT 12 704 705 /**** WD_Timer2_Reset register ****/ 706 /* Shared L2 memory system, interrupt controller and timer logic reset */ 707 #define NB_GLOBAL_WD_TIMER2_RESET_L2RESET (1 << 0) 708 /* Shared debug domain reset */ 709 #define NB_GLOBAL_WD_TIMER2_RESET_PRESETDBG (1 << 1) 710 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */ 711 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_DBGRESET_MASK 0x000000F0 712 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_DBGRESET_SHIFT 4 713 /* Individual CPU core and VFP/NEON logic reset */ 714 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_CORERESET_MASK 0x00000F00 715 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_CORERESET_SHIFT 8 716 /* Individual CPU por-on-reset */ 717 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_PORESET_MASK 0x0000F000 718 #define NB_GLOBAL_WD_TIMER2_RESET_CPU_PORESET_SHIFT 12 719 720 /**** WD_Timer3_Reset register ****/ 721 /* Shared L2 memory system, interrupt controller and timer logic reset */ 722 #define NB_GLOBAL_WD_TIMER3_RESET_L2RESET (1 << 0) 723 /* Shared debug domain reset */ 724 #define NB_GLOBAL_WD_TIMER3_RESET_PRESETDBG (1 << 1) 725 /* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */ 726 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_DBGRESET_MASK 0x000000F0 727 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_DBGRESET_SHIFT 4 728 /* Individual CPU core and VFP/NEON logic reset */ 729 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_CORERESET_MASK 0x00000F00 730 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_CORERESET_SHIFT 8 731 /* Individual CPU por-on-reset */ 732 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_PORESET_MASK 0x0000F000 733 #define NB_GLOBAL_WD_TIMER3_RESET_CPU_PORESET_SHIFT 12 734 735 /**** DDRC_Hold_Reset register ****/ 736 /* DDR Control and PHY memory mapped registers reset control 737 0 - Reset is deasserted. 738 1 - Reset is asserted (active). */ 739 #define NB_GLOBAL_DDRC_HOLD_RESET_APB_SYNC_RESET (1 << 0) 740 /* DDR Control Core reset control 741 0 - Reset is deasserted. 742 1 - Reset is asserted. 743 This field must be set to 0 to start the initialization process after configuring the DDR Controller registers. */ 744 #define NB_GLOBAL_DDRC_HOLD_RESET_CORE_SYNC_RESET (1 << 1) 745 /* DDR Control AXI Interface reset control 746 0 - Reset is deasserted. 747 1 - Reset is asserted. 748 This field must not be set to 0 while core_sync_reset is set to 1. */ 749 #define NB_GLOBAL_DDRC_HOLD_RESET_AXI_SYNC_RESET (1 << 2) 750 /* DDR PUB Controller reset control 751 0 - Reset is deasserted. 752 1 - Reset is asserted. 753 This field must be set to 0 to start the initialization process after configuring the PUB Controller registers. */ 754 #define NB_GLOBAL_DDRC_HOLD_RESET_PUB_CTL_SYNC_RESET (1 << 3) 755 /* DDR PUB SDR Controller reset control 756 0 - Reset is deasserted. 757 1 - Reset is asserted. 758 This field must be set to 0 to start the initialization process after configuring the PUB Controller registers. */ 759 #define NB_GLOBAL_DDRC_HOLD_RESET_PUB_SDR_SYNC_RESET (1 << 4) 760 /* DDR PHY reset control 761 0 - Reset is deasserted. 762 1 - Reset is asserted. */ 763 #define NB_GLOBAL_DDRC_HOLD_RESET_PHY_SYNC_RESET (1 << 5) 764 /* Memory initialization input to DDR SRAM for parity check support */ 765 #define NB_GLOBAL_DDRC_HOLD_RESET_DDR_UNIT_MEM_INIT (1 << 6) 766 767 /**** Fabric_Software_Reset register ****/ 768 /* Write 1 apply the software reset. */ 769 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_SWRESET_REQ (1 << 0) 770 /* Defines the level of software reset: 771 0x0 - fabric: Fabric reset 772 0x1 - gic: GIC reset 773 0x2 - smmu: SMMU reset */ 774 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_MASK 0x0000000E 775 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT 1 776 /* Fabric reset */ 777 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_FABRIC \ 778 (0x0 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT) 779 /* GIC reset */ 780 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_GIC \ 781 (0x1 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT) 782 /* SMMU reset */ 783 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SMMU \ 784 (0x2 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT) 785 /* CPUn waiting for interrupt enable. 786 Defines which CPU WFI indication to wait before applying the software reset. */ 787 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000 788 #define NB_GLOBAL_FABRIC_SOFTWARE_RESET_WFI_MASK_SHIFT 16 789 790 /**** CPUs_Power_Ctrl register ****/ 791 /* L2 WFI enable 792 When all the processors are in WFI mode or powered-down, the shared L2 memory system Power Management controller resumes clock on any interrupt. 793 Power management controller resumes clock on snoop request. 794 NOT IMPLEMENTED */ 795 #define NB_GLOBAL_CPUS_POWER_CTRL_L2WFI_EN (1 << 0) 796 /* L2 WFI status */ 797 #define NB_GLOBAL_CPUS_POWER_CTRL_L2WFI_STATUS (1 << 1) 798 /* L2 RAMs Power Down 799 Power down the L2 RAMs. L2 caches must be flushed prior to entering this state. */ 800 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_EN (1 << 2) 801 /* L2 RAMs power down status */ 802 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_STATUS (1 << 3) 803 /* CPU state condition to enable L2 RAM power down 804 0 - Power down 805 1 - WFI 806 NOT IMPLEMENTED */ 807 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_CPUS_STATE_MASK 0x000000F0 808 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_CPUS_STATE_SHIFT 4 809 /* Enable external debugger over power-down. 810 Provides support for external debug over power down. If any or all of the processors are powered down, the SoC can still use the debug facilities if the debug PCLKDBG domain is powered up. */ 811 #define NB_GLOBAL_CPUS_POWER_CTRL_EXT_DEBUGGER_OVER_PD_EN (1 << 8) 812 /* L2 hardware flush request. This signal indicates: 813 0 L2 hardware flush request is not asserted. flush is performed by SW 814 1 L2 hardware flush request is asserted by power management block as part of cluster rams power down flow. HW starts L2 flush flow when all CPUs are in WFI */ 815 #define NB_GLOBAL_CPUS_POWER_CTRL_L2FLUSH_EN (1 << 9) 816 /* Force wakeup the CPU in L2RAM power down 817 INTERNAL DEBUG PURPOSE ONLY */ 818 #define NB_GLOBAL_CPUS_POWER_CTRL_FORCE_CPUS_OK_PWRUP (1 << 27) 819 /* L2 RAMs power down SM status */ 820 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_SM_STATUS_MASK 0xF0000000 821 #define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_SM_STATUS_SHIFT 28 822 823 /**** ACF_Base_High register ****/ 824 /* Coherency Fabric registers base [39:32]. */ 825 #define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_MASK 0x000000FF 826 #define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_SHIFT 0 827 /* Coherency Fabric registers base [31:15] */ 828 #define NB_GLOBAL_ACF_BASE_LOW_BASED_31_15_MASK 0xFFFF8000 829 #define NB_GLOBAL_ACF_BASE_LOW_BASED_31_15_SHIFT 15 830 831 /**** ACF_Control_Override register ****/ 832 /* Override the AWCACHE[0] and ARCACHE[0] outputs to be 833 non-bufferable. One bit exists for each master interface. 834 Connected to BUFFERABLEOVERRIDE[2:0] */ 835 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_MASK 0x00000007 836 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_SHIFT 0 837 /* Overrides the ARQOS and AWQOS input signals. One bit exists for each slave 838 interface. 839 Connected to QOSOVERRIDE[4:0] */ 840 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_QOSOVRD_MASK 0x000000F8 841 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_QOSOVRD_SHIFT 3 842 /* If LOW, then AC requests are never issued on the corresponding slave 843 interface. One bit exists for each slave interface. 844 Connected to ACCHANNELEN[4:0]. */ 845 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_ACE_CH_EN_MASK 0x00001F00 846 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_ACE_CH_EN_SHIFT 8 847 /* Internal register: 848 Enables 4k hazard of post-barrier vs pre-barrier transactions. Otherwise, 64B hazard granularity is applied. */ 849 #define NB_GLOBAL_ACF_CONTROL_OVERRIDE_DMB_4K_HAZARD_EN (1 << 13) 850 851 /**** LGIC_Base_High register ****/ 852 /* GIC registers base [39:32]. 853 This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset. */ 854 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF 855 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_SHIFT 0 856 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_ALPINE_V2 0x00000FFF 857 #define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_ALPINE_V2 0 858 /* GIC registers base [31:15]. 859 This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset */ 860 #define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000 861 #define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_SHIFT 15 862 863 /**** IOGIC_Base_High register ****/ 864 /* IOGIC registers base [39:32] */ 865 #define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF 866 #define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_SHIFT 0 867 /* IOGIC registers base [31:15] */ 868 #define NB_GLOBAL_IOGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000 869 #define NB_GLOBAL_IOGIC_BASE_LOW_BASED_31_15_SHIFT 15 870 871 /**** IO_Wr_Split_Control register ****/ 872 /* Write splitters bypass. 873 [0] Splitter 0 bypass enable 874 [1] Splitter 1 bypass enable */ 875 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_MASK 0x00000003 876 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_SHIFT 0 877 /* Write splitters store and forward. 878 If store and forward is disabled, splitter does not check non-active BE in the middle of a transaction. */ 879 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_ST_FW_MASK 0x0000000C 880 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_ST_FW_SHIFT 2 881 /* Write splitters unmodify snoop type. 882 Disables modifying snoop type from Clean & Invalidate to Invalidate when conditions enable it. Only split operation to 64B is applied. */ 883 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNMODIFY_SNP_MASK 0x00000030 884 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNMODIFY_SNP_SHIFT 4 885 /* Write splitters unsplit non-coherent access. 886 Disables splitting of non-coherent access to cache-line chunks. */ 887 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNSPLIT_NOSNP_MASK 0x000000C0 888 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNSPLIT_NOSNP_SHIFT 6 889 /* Write splitter rate limit. */ 890 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR0_SPLT_RATE_LIMIT_MASK 0x00001F00 891 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR0_SPLT_RATE_LIMIT_SHIFT 8 892 /* Write splitter rate limit */ 893 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR1_SPLT_RATE_LIMIT_MASK 0x0003E000 894 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR1_SPLT_RATE_LIMIT_SHIFT 13 895 /* Write splitters 64bit remap enable 896 Enables remapping of 64bit transactions */ 897 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_REMAP_64BIT_EN_MASK 0x000C0000 898 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_REMAP_64BIT_EN_SHIFT 18 899 /* Clear is not supported. This bit was changed to wr_pack_disable. 900 In default mode, AWADDR waits for WDATA. */ 901 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_CLEAR_MASK 0xC0000000 902 #define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_CLEAR_SHIFT 30 903 904 /**** IO_Rd_ROB_Control register ****/ 905 /* Read ROB Bypass 906 [0] Rd ROB 0 bypass enable. 907 [1] Rd ROB 1 bypass enable. */ 908 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_MASK 0x00000003 909 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_SHIFT 0 910 /* Read ROB in order. 911 Return data in the order of request acceptance. */ 912 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_INORDER_MASK 0x0000000C 913 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_INORDER_SHIFT 2 914 /* Read ROB response rate 915 When enabled drops one cycle from back to back read responses */ 916 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_RSP_RATE_MASK 0x00000030 917 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_RSP_RATE_SHIFT 4 918 /* Read splitter rate limit */ 919 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD0_ROB_RATE_LIMIT_MASK 0x00001F00 920 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD0_ROB_RATE_LIMIT_SHIFT 8 921 /* Read splitter rate limit */ 922 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD1_ROB_RATE_LIMIT_MASK 0x0003E000 923 #define NB_GLOBAL_IO_RD_ROB_CONTROL_RD1_ROB_RATE_LIMIT_SHIFT 13 924 925 /**** SB_PoS_Error_Log_1 register ****/ 926 /* Error Log 1 927 [7:0] address_high 928 [16:8] request id 929 [18:17] bresp */ 930 #define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_MASK 0x7FFFFFFF 931 #define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_SHIFT 0 932 /* Valid logged error 933 Set on SB PoS error occurrence on capturing the error information. Subsequent errors will not be captured until the valid bit is cleared. 934 The SB PoS reports on write errors. 935 When valid, an interrupt is set in the NB Cause Register. */ 936 #define NB_GLOBAL_SB_POS_ERROR_LOG_1_VALID (1 << 31) 937 938 /**** MSIx_Error_Log register ****/ 939 /* Error Log 940 Corresponds to MSIx address message [30:0]. */ 941 #define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_MASK 0x7FFFFFFF 942 #define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_SHIFT 0 943 /* Valid logged error */ 944 #define NB_GLOBAL_MSIX_ERROR_LOG_VALID (1 << 31) 945 946 /**** Error_Cause register ****/ 947 /* Received msix is not mapped to local GIC or IO-GIC spin */ 948 #define NB_GLOBAL_ERROR_CAUSE_MSIX_ERR_INT (1 << 2) 949 /* Coresight timestamp overflow */ 950 #define NB_GLOBAL_ERROR_CAUSE_CORESIGHT_TS_OVERFLOW (1 << 3) 951 /* Write data parity error from SB channel 0. */ 952 #define NB_GLOBAL_ERROR_CAUSE_SB0_WRDATA_PERR (1 << 4) 953 /* Write data parity error from SB channel 1. */ 954 #define NB_GLOBAL_ERROR_CAUSE_SB1_WRDATA_PERR (1 << 5) 955 /* Read data parity error from SB slaves. */ 956 #define NB_GLOBAL_ERROR_CAUSE_SB_SLV_RDATA_PERR (1 << 6) 957 /* Local GIC uncorrectable ECC error */ 958 #define NB_GLOBAL_ERROR_CAUSE_LOCAL_GIC_ECC_FATAL (1 << 7) 959 /* SB PoS error */ 960 #define NB_GLOBAL_ERROR_CAUSE_SB_POS_ERR (1 << 8) 961 /* Coherent fabric error summary interrupt */ 962 #define NB_GLOBAL_ERROR_CAUSE_ACF_ERRORIRQ (1 << 9) 963 /* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator connected to CA15 nAXIERRIRQ. */ 964 #define NB_GLOBAL_ERROR_CAUSE_CPU_AXIERRIRQ (1 << 10) 965 /* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */ 966 #define NB_GLOBAL_ERROR_CAUSE_CPU_INTERRIRQ (1 << 12) 967 /* DDR cause summery interrupt */ 968 #define NB_GLOBAL_ERROR_CAUSE_DDR_CAUSE_SUM (1 << 14) 969 970 /**** QoS_Peak_Control register ****/ 971 /* Peak Read Low Threshold 972 When the number of outstanding read transactions from SB masters is below this value, the CPU is assigned high-priority QoS. */ 973 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_MASK 0x0000007F 974 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_SHIFT 0 975 /* Peak Read High Threshold 976 When the number of outstanding read transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS. */ 977 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_H_THRESHOLD_MASK 0x00007F00 978 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_H_THRESHOLD_SHIFT 8 979 /* Peak Write Low Threshold 980 When the number of outstanding write transactions from SB masters is below this value, the CPU is assigned high-priority QoS */ 981 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_L_THRESHOLD_MASK 0x007F0000 982 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_L_THRESHOLD_SHIFT 16 983 /* Peak Write High Threshold 984 When the number of outstanding write transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS. */ 985 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_H_THRESHOLD_MASK 0x7F000000 986 #define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_H_THRESHOLD_SHIFT 24 987 988 /**** QoS_Set_Control register ****/ 989 /* CPU Low priority Read QoS */ 990 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_MASK 0x0000000F 991 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_SHIFT 0 992 /* CPU High priority Read QoS */ 993 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_ARQOS_MASK 0x000000F0 994 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_ARQOS_SHIFT 4 995 /* CPU Low priority Write QoS */ 996 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_AWQOS_MASK 0x00000F00 997 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_AWQOS_SHIFT 8 998 /* CPU High priority Write QoS */ 999 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_AWQOS_MASK 0x0000F000 1000 #define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_AWQOS_SHIFT 12 1001 /* SB Low priority Read QoS */ 1002 #define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_ARQOS_MASK 0x000F0000 1003 #define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_ARQOS_SHIFT 16 1004 /* SB Low-priority Write QoS */ 1005 #define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_AWQOS_MASK 0x00F00000 1006 #define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_AWQOS_SHIFT 20 1007 1008 /**** DDR_QoS register ****/ 1009 /* High Priority Read Threshold 1010 Limits the number of outstanding high priority reads in the system through the memory controller. 1011 This parameter is programmed in conjunction with number of outstanding high priority reads supported by the DDR controller. */ 1012 #define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_MASK 0x0000007F 1013 #define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_SHIFT 0 1014 /* DDR Low Priority QoS 1015 Fabric priority below this value is mapped to DDR low priority queue. */ 1016 #define NB_GLOBAL_DDR_QOS_LP_QOS_MASK 0x00000F00 1017 #define NB_GLOBAL_DDR_QOS_LP_QOS_SHIFT 8 1018 1019 /**** ACF_Misc register ****/ 1020 /* Disable DDR Write Chop 1021 Performance optimization feature to chop non-active data beats to the DDR. */ 1022 #define NB_GLOBAL_ACF_MISC_DDR_WR_CHOP_DIS (1 << 0) 1023 /* Disable SB-2-SB path through NB fabric. */ 1024 #define NB_GLOBAL_ACF_MISC_SB2SB_PATH_DIS (1 << 1) 1025 /* Disable ETR tracing to non-DDR. */ 1026 #define NB_GLOBAL_ACF_MISC_ETR2SB_PATH_DIS (1 << 2) 1027 /* Disable ETR tracing to non-DDR. */ 1028 #define NB_GLOBAL_ACF_MISC_CPU2MSIX_DIS (1 << 3) 1029 /* Disable CPU generation of MSIx 1030 By default, the CPU can set any MSIx message results by setting any SPIn bit in the local and IO-GIC. */ 1031 #define NB_GLOBAL_ACF_MISC_MSIX_TERMINATE_DIS (1 << 4) 1032 /* Disable snoop override for MSIx 1033 By default, an MSIx transaction is downgraded to non-coherent. */ 1034 #define NB_GLOBAL_ACF_MISC_MSIX_SNOOPOVRD_DIS (1 << 5) 1035 /* POS bypass */ 1036 #define NB_GLOBAL_ACF_MISC_POS_BYPASS (1 << 6) 1037 /* PoS ReadStronglyOrdered enable 1038 SO read forces flushing of all prior writes */ 1039 #define NB_GLOBAL_ACF_MISC_POS_RSO_EN (1 << 7) 1040 /* WRAP to INC transfer enable */ 1041 #define NB_GLOBAL_ACF_MISC_POS_WRAP2INC (1 << 8) 1042 /* PoS DSB flush Disable 1043 On DSB from CPU, PoS blocks the progress of post-barrier reads and writes until all pre-barrier writes have been completed. */ 1044 #define NB_GLOBAL_ACF_MISC_POS_DSB_FLUSH_DIS (1 << 9) 1045 /* PoS DMB Flush Disable 1046 On DMB from CPU, the PoS blocks the progress of post-barrier non-buffereable reads or writes when there are outstanding non-bufferable writes that have not yet been completed. 1047 Other access types are hazard check against the pre-barrier requests. */ 1048 #define NB_GLOBAL_ACF_MISC_POS_DMB_FLUSH_DIS (1 << 10) 1049 /* change DMB functionality to DSB (block and drain) */ 1050 #define NB_GLOBAL_ACF_MISC_POS_DMB_TO_DSB_EN (1 << 11) 1051 /* Disable write after read stall when accessing IO fabric slaves. */ 1052 #define NB_GLOBAL_ACF_MISC_M0_WAR_STALL_DIS (1 << 12) 1053 /* Disable write after read stall when accessing DDR */ 1054 #define NB_GLOBAL_ACF_MISC_M1_WAR_STALL_DIS (1 << 13) 1055 /* Disable counter (wait 1000 NB cycles) before applying PoS enable/disable configuration */ 1056 #define NB_GLOBAL_ACF_MISC_POS_CONFIG_CNT_DIS (1 << 14) 1057 /* Disable wr spliter A0 bug fixes */ 1058 #define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_V1_M0_MODE (1 << 16) 1059 /* Disable wr spliter ALPINE_V2 bug fixes */ 1060 #define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_V1_A0_MODE (1 << 17) 1061 /* Override the address parity calucation for write transactions going to IO-fabric */ 1062 #define NB_GLOBAL_ACF_MISC_NB_NIC_AWADDR_PAR_OVRD (1 << 18) 1063 /* Override the data parity calucation for write transactions going to IO-fabric */ 1064 #define NB_GLOBAL_ACF_MISC_NB_NIC_WDATA_PAR_OVRD (1 << 19) 1065 /* Override the address parity calucation for read transactions going to IO-fabric */ 1066 #define NB_GLOBAL_ACF_MISC_NB_NIC_ARADDR_PAR_OVRD (1 << 20) 1067 /* Halts CPU AXI interface (Ar/Aw channels), not allowing the CPU to send additional transactions */ 1068 #define NB_GLOBAL_ACF_MISC_CPU_AXI_HALT (1 << 23) 1069 /* Disable early arbar termination when fabric write buffer is enabled. */ 1070 #define NB_GLOBAL_ACF_MISC_CCIWB_EARLY_ARBAR_TERM_DIS (1 << 24) 1071 /* Enable wire interrupts connectivity to IO-GIC IRQs */ 1072 #define NB_GLOBAL_ACF_MISC_IOGIC_CHIP_SPI_EN (1 << 25) 1073 /* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */ 1074 #define NB_GLOBAL_ACF_MISC_CPU_DSB_FLUSH_DIS (1 << 26) 1075 /* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */ 1076 #define NB_GLOBAL_ACF_MISC_CPU_DMB_FLUSH_DIS (1 << 27) 1077 /* Alpine V2 only: remap CPU address above 40 bits to Slave Error 1078 INTERNAL */ 1079 #define NB_GLOBAL_ACF_MISC_ADDR43_40_REMAP_DIS (1 << 28) 1080 /* Enable CPU WriteUnique to WriteNoSnoop trasform */ 1081 #define NB_GLOBAL_ACF_MISC_CPU_WU2WNS_EN (1 << 29) 1082 /* Disable device after device check */ 1083 #define NB_GLOBAL_ACF_MISC_WR_POS_DEV_AFTER_DEV_DIS (1 << 30) 1084 /* Disable wrap to inc on write */ 1085 #define NB_GLOBAL_ACF_MISC_WR_INC2WRAP_EN (1 << 31) 1086 1087 /**** Config_Bus_Control register ****/ 1088 /* Write slave error enable */ 1089 #define NB_GLOBAL_CONFIG_BUS_CONTROL_WR_SLV_ERR_EN (1 << 0) 1090 /* Write decode error enable */ 1091 #define NB_GLOBAL_CONFIG_BUS_CONTROL_WR_DEC_ERR_EN (1 << 1) 1092 /* Read slave error enable */ 1093 #define NB_GLOBAL_CONFIG_BUS_CONTROL_RD_SLV_ERR_EN (1 << 2) 1094 /* Read decode error enable */ 1095 #define NB_GLOBAL_CONFIG_BUS_CONTROL_RD_DEC_ERR_EN (1 << 3) 1096 /* Ignore Write ID */ 1097 #define NB_GLOBAL_CONFIG_BUS_CONTROL_IGNORE_WR_ID (1 << 4) 1098 /* Timeout limit before terminating configuration bus access with slave error */ 1099 #define NB_GLOBAL_CONFIG_BUS_CONTROL_TIMEOUT_LIMIT_MASK 0xFFFFFF00 1100 #define NB_GLOBAL_CONFIG_BUS_CONTROL_TIMEOUT_LIMIT_SHIFT 8 1101 1102 /**** Pos_ID_Match register ****/ 1103 /* Enable Device (GRE and nGRE) after Device ID hazard */ 1104 #define NB_GLOBAL_POS_ID_MATCH_ENABLE (1 << 0) 1105 /* ID Field Mask 1106 If set, corresonpding ID bits are not used for ID match */ 1107 #define NB_GLOBAL_POS_ID_MATCH_MASK_MASK 0xFFFF0000 1108 #define NB_GLOBAL_POS_ID_MATCH_MASK_SHIFT 16 1109 1110 /**** sb_sel_override_awuser register ****/ 1111 /* Select whether to use transaction awuser or sb_override_awuser value for awuser field on outgoing write transactions to SB. 1112 Each bit if set to 1 selects the corresponding sb_override_awuser bit. Otherwise, selects the corersponding transaction awuser bit. */ 1113 #define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_MASK 0x03FFFFFF 1114 #define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_SHIFT 0 1115 1116 /**** sb_override_awuser register ****/ 1117 /* Awuser to use on overriden transactions 1118 Only applicable if sel_override_awuser.sel is set to 1'b1 for the coressponding bit */ 1119 #define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_MASK 0x03FFFFFF 1120 #define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_SHIFT 0 1121 1122 /**** sb_sel_override_aruser register ****/ 1123 /* Select whether to use transaction aruser or sb_override_aruser value for aruser field on outgoing read transactions to SB. 1124 Each bit if set to 1 selects the corresponding sb_override_aruser bit. Otherwise, selects the corersponding transaction aruser bit. */ 1125 #define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_MASK 0x03FFFFFF 1126 #define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_SHIFT 0 1127 1128 /**** sb_override_aruser register ****/ 1129 /* Aruser to use on overriden transactions 1130 Only applicable if sb_sel_override_aruser.sel is set to 1'b1 for the coressponding bit */ 1131 #define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_MASK 0x03FFFFFF 1132 #define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_SHIFT 0 1133 1134 /**** Coresight_PD register ****/ 1135 /* ETF0 RAM force power down */ 1136 #define NB_GLOBAL_CORESIGHT_PD_ETF0_RAM_FORCE_PD (1 << 0) 1137 /* ETF1 RAM force power down */ 1138 #define NB_GLOBAL_CORESIGHT_PD_ETF1_RAM_FORCE_PD (1 << 1) 1139 /* ETF0 RAM force clock gate */ 1140 #define NB_GLOBAL_CORESIGHT_PD_ETF0_RAM_FORCE_CG (1 << 2) 1141 /* ETF1 RAM force clock gate */ 1142 #define NB_GLOBAL_CORESIGHT_PD_ETF1_RAM_FORCE_CG (1 << 3) 1143 /* APBIC clock enable */ 1144 #define NB_GLOBAL_CORESIGHT_PD_APBICLKEN (1 << 4) 1145 /* DAP system clock enable */ 1146 #define NB_GLOBAL_CORESIGHT_PD_DAP_SYS_CLKEN (1 << 5) 1147 1148 /**** Coresight_INTERNAL_0 register ****/ 1149 1150 #define NB_GLOBAL_CORESIGHT_INTERNAL_0_CTIAPBSBYPASS (1 << 0) 1151 /* CA15 CTM and Coresight CTI operate at same clock, bypass modes can be enabled but it's being set to bypass disable to break timing path. */ 1152 #define NB_GLOBAL_CORESIGHT_INTERNAL_0_CISBYPASS (1 << 1) 1153 /* CA15 CTM and Coresight CTI operate according to the same clock. 1154 Bypass modes can be enabled, but it is set to bypass disable, to break the timing path. */ 1155 #define NB_GLOBAL_CORESIGHT_INTERNAL_0_CIHSBYPASS_MASK 0x0000003C 1156 #define NB_GLOBAL_CORESIGHT_INTERNAL_0_CIHSBYPASS_SHIFT 2 1157 1158 /**** Coresight_DBGROMADDR register ****/ 1159 /* Valid signal for DBGROMADDR. 1160 Connected to DBGROMADDRV */ 1161 #define NB_GLOBAL_CORESIGHT_DBGROMADDR_VALID (1 << 0) 1162 /* Specifies bits [39:12] of the ROM table physical address. */ 1163 #define NB_GLOBAL_CORESIGHT_DBGROMADDR_ADDR_39_12_MASK 0x3FFFFFFC 1164 #define NB_GLOBAL_CORESIGHT_DBGROMADDR_ADDR_39_12_SHIFT 2 1165 1166 /**** Coresight_DBGSELFADDR register ****/ 1167 /* Valid signal for DBGROMADDR. 1168 Connected to DBGROMADDRV */ 1169 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_VALID (1 << 0) 1170 /* Specifies bits [18:17] of the two's complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped. 1171 Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster. */ 1172 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_18_17_MASK 0x00000180 1173 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_18_17_SHIFT 7 1174 /* Specifies bits [39:19] of the two's complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped. 1175 Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster, so this offset if fixed to zero. */ 1176 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_39_19_MASK 0x3FFFFE00 1177 #define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_39_19_SHIFT 9 1178 1179 /**** SB_force_same_id_cfg_0 register ****/ 1180 /* Enables force same id mechanism for SB port 0 */ 1181 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_FORCE_SAME_ID_EN (1 << 0) 1182 /* Enables MSIx stall when write transactions from same ID mechanism are in progress for SB port 0 */ 1183 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_FORCE_SAME_ID_MSIX_STALL_EN (1 << 1) 1184 /* Mask for choosing which ID bits to match for indicating the originating master */ 1185 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_SB_MSTR_ID_MASK_MASK 0x000000F8 1186 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_SB_MSTR_ID_MASK_SHIFT 3 1187 1188 /**** SB_force_same_id_cfg_1 register ****/ 1189 /* Enables force same id mechanism for SB port 1 */ 1190 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_FORCE_SAME_ID_EN (1 << 0) 1191 /* Enables MSIx stall when write transactions from same ID mechanism are in progress for SB port 1 */ 1192 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_FORCE_SAME_ID_MSIX_STALL_EN (1 << 1) 1193 /* Mask for choosing which ID bits to match for indicating the originating master */ 1194 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_SB_MSTR_ID_MASK_MASK 0x000000F8 1195 #define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_SB_MSTR_ID_MASK_SHIFT 3 1196 1197 /**** Cnt_Control register ****/ 1198 /* System counter enable 1199 Counter is enabled after reset. */ 1200 #define NB_SYSTEM_COUNTER_CNT_CONTROL_EN (1 << 0) 1201 /* System counter restart 1202 Initial value is reloaded from Counter_Init_L and Counter_Init_H registers. 1203 Transition from 0 to 1 reloads the register. */ 1204 #define NB_SYSTEM_COUNTER_CNT_CONTROL_RESTART (1 << 1) 1205 /* Disable CTI trigger out that halt the counter progress */ 1206 #define NB_SYSTEM_COUNTER_CNT_CONTROL_CTI_TRIGOUT_HALT_DIS (1 << 2) 1207 /* System counter tick 1208 Specifies the counter tick rate relative to the Northbridge clock, e.g., the counter is incremented every 16 NB cycles if programmed to 0x0f. */ 1209 #define NB_SYSTEM_COUNTER_CNT_CONTROL_SCALE_MASK 0x0000FF00 1210 #define NB_SYSTEM_COUNTER_CNT_CONTROL_SCALE_SHIFT 8 1211 1212 /**** CA15_RF_Misc register ****/ 1213 1214 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_MASK 0x0000000F 1215 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_SHIFT 0 1216 1217 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_CPU_RF_MISC_MASK 0x00FFFF00 1218 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_CPU_RF_MISC_SHIFT 8 1219 /* Pause for CPUs from the time all power is up to the time the SRAMs start opening. */ 1220 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_PWR_UP_PAUSE_MASK 0xF8000000 1221 #define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_PWR_UP_PAUSE_SHIFT 27 1222 1223 /**** NB_RF_Misc register ****/ 1224 /* SMMU TLB RAMs force power down */ 1225 #define NB_RAMS_CONTROL_MISC_NB_RF_MISC_SMMU_RAM_FORCE_PD (1 << 0) 1226 1227 /**** Lockn register ****/ 1228 /* Semaphore Lock 1229 CPU reads it: 1230 If current value ==0, return 0 to CPU but set bit to 1. (CPU knows it captured the semaphore.) 1231 If current value ==1, return 1 to CPU. (CPU knows it is already used and waits.) 1232 CPU writes 0 to it to release the semaphore. */ 1233 #define NB_SEMAPHORES_LOCKN_LOCK (1 << 0) 1234 1235 /**** CA15_outputs_1 register ****/ 1236 /* 1237 */ 1238 #define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_MASK 0x0000000F 1239 #define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_SHIFT 0 1240 /* 1241 */ 1242 #define NB_DEBUG_CA15_OUTPUTS_1_CPU_PWR_DN_ACK_MASK 0x000000F0 1243 #define NB_DEBUG_CA15_OUTPUTS_1_CPU_PWR_DN_ACK_SHIFT 4 1244 /* 1245 */ 1246 #define NB_DEBUG_CA15_OUTPUTS_1_IRQOUT_N_MASK 0x00000F00 1247 #define NB_DEBUG_CA15_OUTPUTS_1_IRQOUT_N_SHIFT 8 1248 /* 1249 */ 1250 #define NB_DEBUG_CA15_OUTPUTS_1_FIQOUT_N_MASK 0x0000F000 1251 #define NB_DEBUG_CA15_OUTPUTS_1_FIQOUT_N_SHIFT 12 1252 /* 1253 */ 1254 #define NB_DEBUG_CA15_OUTPUTS_1_CNTHPIRQ_N_MASK 0x000F0000 1255 #define NB_DEBUG_CA15_OUTPUTS_1_CNTHPIRQ_N_SHIFT 16 1256 /* 1257 */ 1258 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTPNSIRQ_N_MASK 0x00F00000 1259 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTPNSIRQ_N_SHIFT 20 1260 /* 1261 */ 1262 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTPSIRQ_N_MASK 0x0F000000 1263 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTPSIRQ_N_SHIFT 24 1264 /* 1265 */ 1266 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTVIRQ_N_MASK 0xF0000000 1267 #define NB_DEBUG_CA15_OUTPUTS_1_NCNTVIRQ_N_SHIFT 28 1268 1269 /**** CA15_outputs_2 register ****/ 1270 /* 1271 */ 1272 #define NB_DEBUG_CA15_OUTPUTS_2_STANDBYWFIL2 (1 << 0) 1273 /* 1274 */ 1275 #define NB_DEBUG_CA15_OUTPUTS_2_L2RAM_PWR_DN_ACK (1 << 1) 1276 /* Indicates for each CPU if coherency is enabled 1277 */ 1278 #define NB_DEBUG_CA15_OUTPUTS_2_SMPEN_MASK 0x0000003C 1279 #define NB_DEBUG_CA15_OUTPUTS_2_SMPEN_SHIFT 2 1280 1281 /**** cpu_msg register ****/ 1282 /* Status/ASCII code */ 1283 #define NB_DEBUG_CPU_MSG_STATUS_MASK 0x000000FF 1284 #define NB_DEBUG_CPU_MSG_STATUS_SHIFT 0 1285 /* Toggle with each ASCII write */ 1286 #define NB_DEBUG_CPU_MSG_ASCII_TOGGLE (1 << 8) 1287 /* Signals ASCII */ 1288 #define NB_DEBUG_CPU_MSG_ASCII (1 << 9) 1289 1290 #define NB_DEBUG_CPU_MSG_RESERVED_11_10_MASK 0x00000C00 1291 #define NB_DEBUG_CPU_MSG_RESERVED_11_10_SHIFT 10 1292 /* Signals new section started in S/W */ 1293 #define NB_DEBUG_CPU_MSG_SECTION_START (1 << 12) 1294 1295 #define NB_DEBUG_CPU_MSG_RESERVED_13 (1 << 13) 1296 /* Signals a single CPU is done. */ 1297 #define NB_DEBUG_CPU_MSG_CPU_DONE (1 << 14) 1298 /* Signals test is done */ 1299 #define NB_DEBUG_CPU_MSG_TEST_DONE (1 << 15) 1300 1301 /**** ddrc register ****/ 1302 /* External DLL calibration request. Also compensates for VT variations, such as an external request for the controller (can be performed automatically by the controller at the normal settings). */ 1303 #define NB_DEBUG_DDRC_DLL_CALIB_EXT_REQ (1 << 0) 1304 /* External request to perform short (long is performed during initialization) and/or ODT calibration. */ 1305 #define NB_DEBUG_DDRC_ZQ_SHORT_CALIB_EXT_REQ (1 << 1) 1306 /* External request to perform a refresh command to a specific bank. Usually performed automatically by the controller, however, the controller supports disabling of the automatic mechanism, and use of an external pulse instead. */ 1307 #define NB_DEBUG_DDRC_RANK_REFRESH_EXT_REQ_MASK 0x0000003C 1308 #define NB_DEBUG_DDRC_RANK_REFRESH_EXT_REQ_SHIFT 2 1309 1310 /**** ddrc_phy_smode_control register ****/ 1311 /* DDR PHY special mode */ 1312 #define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_MASK 0x0000FFFF 1313 #define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_SHIFT 0 1314 1315 /**** ddrc_phy_smode_status register ****/ 1316 /* DDR PHY special mode */ 1317 #define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_MASK 0x0000FFFF 1318 #define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_SHIFT 0 1319 1320 /**** pmc register ****/ 1321 /* Enable system control on NB DRO */ 1322 #define NB_DEBUG_PMC_SYS_EN (1 << 0) 1323 /* NB PMC HVT35 counter value */ 1324 #define NB_DEBUG_PMC_HVT35_VAL_14_0_MASK 0x0000FFFE 1325 #define NB_DEBUG_PMC_HVT35_VAL_14_0_SHIFT 1 1326 /* NB PMC SVT31 counter value */ 1327 #define NB_DEBUG_PMC_SVT31_VAL_14_0_MASK 0x7FFF0000 1328 #define NB_DEBUG_PMC_SVT31_VAL_14_0_SHIFT 16 1329 1330 /**** cpus_general register ****/ 1331 /* Swaps sysaddr[16:14] with sysaddr[19:17] for DDR access*/ 1332 #define NB_DEBUG_CPUS_GENERAL_ADDR_MAP_ECO (1 << 23) 1333 1334 /**** cpus_int_out register ****/ 1335 /* Defines which CPUs' FIQ will be triggered out through the cpus_int_out[1] pinout. */ 1336 #define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_MASK 0x0000000F 1337 #define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_SHIFT 0 1338 /* Defines which CPUs' IRQ will be triggered out through the cpus_int_out[0] pinout. */ 1339 #define NB_DEBUG_CPUS_INT_OUT_IRQ_EN_MASK 0x000000F0 1340 #define NB_DEBUG_CPUS_INT_OUT_IRQ_EN_SHIFT 4 1341 /* Defines which CPUs' SEI will be triggered out through the cpus_int_out[0] pinout. */ 1342 #define NB_DEBUG_CPUS_INT_OUT_IRQ_SEI_EN_MASK 0x00000F00 1343 #define NB_DEBUG_CPUS_INT_OUT_IRQ_SEI_EN_SHIFT 8 1344 1345 /**** latch_pc_req register ****/ 1346 /* If set, request to latch execution PC from processor cluster */ 1347 #define NB_DEBUG_LATCH_PC_REQ_EN (1 << 0) 1348 /* target CPU id to latch its execution PC */ 1349 #define NB_DEBUG_LATCH_PC_REQ_CPU_ID_MASK 0x000000F0 1350 #define NB_DEBUG_LATCH_PC_REQ_CPU_ID_SHIFT 4 1351 1352 /**** latch_pc_low register ****/ 1353 /* Set by hardware when the processor cluster ack the PC latch request. 1354 Clear on read latch_pc_high */ 1355 #define NB_DEBUG_LATCH_PC_LOW_VALID (1 << 0) 1356 /* Latched PC value [31:1] */ 1357 #define NB_DEBUG_LATCH_PC_LOW_VAL_MASK 0xFFFFFFFE 1358 #define NB_DEBUG_LATCH_PC_LOW_VAL_SHIFT 1 1359 1360 /**** track_dump_ctrl register ****/ 1361 /* [24:16]: Queue entry pointer 1362 [2] Target queue: 1'b0: HazardTrack or 1'b1: AmiRMI queues 1363 [1:0]: CCI target master: 2'b00: M0, 2'b01: M1, 2'b10: M2 */ 1364 #define NB_DEBUG_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF 1365 #define NB_DEBUG_TRACK_DUMP_CTRL_PTR_SHIFT 0 1366 /* Track Dump Request 1367 If set, queue entry info is latched on track_dump_rdata register. 1368 Program the pointer and target queue. 1369 This is a full handshake register. 1370 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */ 1371 #define NB_DEBUG_TRACK_DUMP_CTRL_REQ (1 << 31) 1372 1373 /**** track_dump_rdata_0 register ****/ 1374 /* Valid */ 1375 #define NB_DEBUG_TRACK_DUMP_RDATA_0_VALID (1 << 0) 1376 /* Low data */ 1377 #define NB_DEBUG_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE 1378 #define NB_DEBUG_TRACK_DUMP_RDATA_0_DATA_SHIFT 1 1379 1380 /**** pos_track_dump_ctrl register ****/ 1381 /* [24:16]: queue entry pointer */ 1382 #define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF 1383 #define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_SHIFT 0 1384 /* Track Dump Request 1385 If set, queue entry info is latched on track_dump_rdata register. 1386 Program the pointer and target queue. 1387 This is a full handshake register 1388 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */ 1389 #define NB_DEBUG_POS_TRACK_DUMP_CTRL_REQ (1 << 31) 1390 1391 /**** pos_track_dump_rdata_0 register ****/ 1392 /* Valid */ 1393 #define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_VALID (1 << 0) 1394 /* Low data */ 1395 #define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE 1396 #define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_DATA_SHIFT 1 1397 1398 /**** c2swb_track_dump_ctrl register ****/ 1399 /* [24:16]: Queue entry pointer */ 1400 #define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF 1401 #define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_SHIFT 0 1402 /* Track Dump Request 1403 If set, queue entry info is latched on track_dump_rdata register. 1404 Program the pointer and target queue. 1405 This is a full handshake register 1406 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */ 1407 #define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_REQ (1 << 31) 1408 1409 /**** c2swb_track_dump_rdata_0 register ****/ 1410 /* Valid */ 1411 #define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_VALID (1 << 0) 1412 /* Low data */ 1413 #define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE 1414 #define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_DATA_SHIFT 1 1415 1416 /**** cpus_track_dump_ctrl register ****/ 1417 /* [24:16]: Queue entry pointer 1418 [3:2] Target queue - 0:ASI, 1: AMI 1419 [1:0]: Target Processor Cluster - 0: Cluster0, 1: Cluster1 */ 1420 #define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF 1421 #define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_SHIFT 0 1422 /* Track Dump Request 1423 If set, queue entry info is latched on track_dump_rdata register. 1424 Program the pointer and target queue. 1425 This is a full handshake register 1426 Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */ 1427 #define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_REQ (1 << 31) 1428 1429 /**** cpus_track_dump_rdata_0 register ****/ 1430 /* Valid */ 1431 #define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_VALID (1 << 0) 1432 /* Low data */ 1433 #define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE 1434 #define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_DATA_SHIFT 1 1435 1436 /**** c2swb_bar_ovrd_high register ****/ 1437 /* Read barrier is progressed downstream when not terminated in the CCI. 1438 By specification, barrier address is 0x0. 1439 This register enables barrier address OVRD to a programmable value. */ 1440 #define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_RD_ADDR_OVRD_EN (1 << 0) 1441 /* Address bits 39:32 */ 1442 #define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_ADDR_39_32_MASK 0x00FF0000 1443 #define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_ADDR_39_32_SHIFT 16 1444 1445 /**** Config register ****/ 1446 /* Individual processor control of the endianness configuration at reset. It sets the initial value of the EE bit in the CP15 System Control Register (SCTLR) related to CFGEND<n> input: 1447 little - 0x0: Little endian 1448 bit - 0x1: Bit endian */ 1449 #define NB_CPUN_CONFIG_STATUS_CONFIG_ENDIAN (1 << 0) 1450 /* Individual processor control of the default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register (SCTLR) related to CFGTE<n> input: 1451 arm: 0x0: Exception operates ARM code. 1452 Thumb: 0x1: Exception operates Thumb code. */ 1453 #define NB_CPUN_CONFIG_STATUS_CONFIG_TE (1 << 1) 1454 /* Individual processor control of the location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 System Control Register (SCTLR). 1455 Connected to VINITHIGH<n> input. 1456 low - 0x0: Exception vectors start at address 0x00000000. 1457 high - 0x1: Exception vectors start at address 0xFFFF0000. */ 1458 #define NB_CPUN_CONFIG_STATUS_CONFIG_VINITHI (1 << 2) 1459 /* Individual processor control to disable write access to some secure CP15 registers 1460 connected to CP15SDISABLE<n> input. */ 1461 #define NB_CPUN_CONFIG_STATUS_CONFIG_CP15DISABLE (1 << 3) 1462 /* Force Write init implementation to ConfigAARch64 register */ 1463 #define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_REG_FORCE_WINIT (1 << 4) 1464 /* Force Write Once implementation to ConfigAARch64 register. */ 1465 #define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_REG_FORCE_WONCE (1 << 5) 1466 1467 /**** Config_AARch64 register ****/ 1468 /* Individual processor register width state. The register width states are: 1469 0 AArch32. 1470 1 AArch64. 1471 This signal is only sampled during reset of the processor. 1472 This is Write Init register */ 1473 #define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_AA64_NAA32 (1 << 0) 1474 /* Individual processor Cryptography engine disable: 1475 0 Enable the Cryptography engine. 1476 1 Disable the Cryptography engine. 1477 This signal is only sampled during reset of the processor */ 1478 #define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_CRYPTO_DIS (1 << 1) 1479 1480 /**** Power_Ctrl register ****/ 1481 /* Individual CPU power mode transition request 1482 If requested to enter power mode other than normal mode, low power state is resumed whenever CPU reenters STNDBYWFI state: 1483 normal: 0x0: normal power state 1484 deep_idle: 0x2: Dormant power mode state 1485 poweredoff: 0x3: Powered-off power mode */ 1486 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_MASK 0x00000003 1487 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT 0 1488 /* Normal power mode state */ 1489 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_NORMAL \ 1490 (0x0 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT) 1491 /* Dormant power mode state */ 1492 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_DEEP_IDLE \ 1493 (0x2 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT) 1494 /* Powered-off power mode */ 1495 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_POWEREDOFF \ 1496 (0x3 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT) 1497 /* Power down regret disable 1498 When power down regret is enabled, the powerdown enter flow can be halted whenever a valid wakeup event occurs. */ 1499 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PWRDN_RGRT_DIS (1 << 16) 1500 /* Power down emulation enable 1501 If set, the entire power down sequence is applied, but the CPU is placed in soft reset instead of hardware power down. */ 1502 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PWRDN_EMULATE (1 << 17) 1503 /* Disable wakeup from Local--GIC FIQ. */ 1504 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_LGIC_FIQ_DIS (1 << 18) 1505 /* Disable wakeup from Local-GIC IRQ. */ 1506 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_LGIC_IRQ_DIS (1 << 19) 1507 /* Disable wakeup from IO-GIC FIQ. */ 1508 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_IOGIC_FIQ_DIS (1 << 20) 1509 /* Disable wakeup from IO-GIC IRQ. */ 1510 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_IOGIC_IRQ_DIS (1 << 21) 1511 /* Disable scheduling of interrrupts in GIC(500) to non-active CPU */ 1512 #define NB_CPUN_CONFIG_STATUS_POWER_CTRL_IOGIC_DIS_CPU (1 << 22) 1513 1514 /**** Power_Status register ****/ 1515 /* Read-only bits that reflect the individual CPU power mode status. 1516 Default value for non-exist CPU is 2b11: 1517 normal - 0x0: Normal mode 1518 por - 0x1: por on reset mode 1519 deep_idle - 0x2: Dormant power mode state 1520 poweredoff - 0x3: Powered-off power mode */ 1521 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_MASK 0x00000003 1522 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT 0 1523 /* Normal power mode state */ 1524 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_NORMAL \ 1525 (0x0 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT) 1526 /* Idle power mode state (WFI) */ 1527 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_IDLE \ 1528 (0x1 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT) 1529 /* Dormant power mode state */ 1530 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_DEEP_IDLE \ 1531 (0x2 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT) 1532 /* Powered-off power mode */ 1533 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_POWEREDOFF \ 1534 (0x3 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT) 1535 /* WFI status */ 1536 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_WFI (1 << 2) 1537 /* WFE status */ 1538 #define NB_CPUN_CONFIG_STATUS_POWER_STATUS_WFE (1 << 3) 1539 1540 /**** Warm_Rst_Ctl register ****/ 1541 /* Disable CPU Warm Reset when warmrstreq is asserted 1542 1543 When the Reset Request bit in the RMR or RMR_EL3 register is set to 1 in the CPU Core , the processor asserts the WARMRSTREQ signal and the SoC reset controller use this request to trigger a Warm reset of the processor and change the register width state. */ 1544 #define NB_CPUN_CONFIG_STATUS_WARM_RST_CTL_REQ_DIS (1 << 0) 1545 /* Disable waiting WFI on Warm Reset */ 1546 #define NB_CPUN_CONFIG_STATUS_WARM_RST_CTL_WFI_DIS (1 << 1) 1547 /* CPU Core AARach64 reset vector bar 1548 This is Write Once register (controlled by aarch64_reg_force_* fields) */ 1549 #define NB_CPUN_CONFIG_STATUS_RVBAR_LOW_ADDR_31_2_MASK 0xFFFFFFFC 1550 #define NB_CPUN_CONFIG_STATUS_RVBAR_LOW_ADDR_31_2_SHIFT 2 1551 1552 /**** Rvbar_High register ****/ 1553 /* CPU Core AARach64 reset vector bar high bits 1554 This is Write Once register (controlled by aarch64_reg_force_* fields) */ 1555 #define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_MASK 0x00000FFF 1556 #define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_SHIFT 0 1557 1558 /**** pmu_snapshot register ****/ 1559 /* PMU Snapshot Request */ 1560 #define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_REQ (1 << 0) 1561 /* 0: HW deassert requests when received ack 1562 1: SW deasserts request when received done */ 1563 #define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_MODE (1 << 1) 1564 /* Snapshot process completed */ 1565 #define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_DONE (1 << 31) 1566 1567 /**** cpu_msg_in register ****/ 1568 /* CPU read this register to receive input (char) from simulation. */ 1569 #define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_MASK 0x000000FF 1570 #define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_SHIFT 0 1571 /* Indicates the data is valid. 1572 Cleared on read */ 1573 #define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_VALID (1 << 8) 1574 1575 /**** PMU_Control register ****/ 1576 /* Disable all counters 1577 When this bit is clear, counter state is determined through the specific counter control register */ 1578 #define NB_MC_PMU_PMU_CONTROL_DISABLE_ALL (1 << 0) 1579 /* Pause all counters. 1580 When this bit is clear, counter state is determined through the specific counter control register. */ 1581 #define NB_MC_PMU_PMU_CONTROL_PAUSE_ALL (1 << 1) 1582 /* Overflow interrupt enable: 1583 disable - 0x0: Disable interrupt on overflow. 1584 enable - 0x1: Enable interrupt on overflow. */ 1585 #define NB_MC_PMU_PMU_CONTROL_OVRF_INTR_EN (1 << 2) 1586 /* Number of monitored events supported by the PMU. */ 1587 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_MASK 0x00FC0000 1588 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT 18 1589 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT_ALPINE_V1 19 1590 /* Number of counters implemented by PMU. */ 1591 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_MASK 0x0F000000 1592 #define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_SHIFT 24 1593 1594 /**** Cfg register ****/ 1595 /* Event select */ 1596 #define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_MASK 0x0000003F 1597 #define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_SHIFT 0 1598 /* Enable setting of counter low overflow status bit: 1599 disable - 0x0: Disable setting. 1600 enable - 0x1: Enable setting. */ 1601 #define NB_MC_PMU_COUNTERS_CFG_OVRF_LOW_STT_EN (1 << 6) 1602 /* Enable setting of counter high overflow status bit: 1603 disable - 0x0: Disable setting. 1604 enable - 0x1: Enable setting. */ 1605 #define NB_MC_PMU_COUNTERS_CFG_OVRF_HIGH_STT_EN (1 << 7) 1606 /* Enable pause on trigger in assertion: 1607 disable - 0x0: Disable pause. 1608 enable - 0x1: Enable pause. */ 1609 #define NB_MC_PMU_COUNTERS_CFG_TRIGIN_PAUSE_EN (1 << 8) 1610 /* Enable increment trigger out for trace. 1611 Trigger is generated whenever counter reaches <granule> value: 1612 disable - 0x0: Disable trigger out. 1613 enable - 0x1: Enable trigger out. */ 1614 #define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_EN (1 << 9) 1615 /* Trigger out granule value 1616 Specifies the number of events counted between two consecutive trigger out events 1617 0x0: 1 - Trigger out on every event occurrence. 1618 0x1: 2 - Trigger out on every two events. 1619 ... 1620 0xn: 2^(n-1) - Trigger out on event 2^(n-1) events. 1621 ... 1622 0x1F: 2^31 */ 1623 #define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_GRANULA_MASK 0x00007C00 1624 #define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_GRANULA_SHIFT 10 1625 /* Pause on overflow bitmask 1626 If set for counter <i>, current counter pauses counting when counter<i> is overflowed, including self-pause. 1627 Bit [16]: counter 0 1628 Bit [17]: counter 1 1629 Note: This field must be changed for larger counters. */ 1630 #define NB_MC_PMU_COUNTERS_CFG_PAUSE_ON_OVRF_BITMASK_MASK 0x000F0000 1631 #define NB_MC_PMU_COUNTERS_CFG_PAUSE_ON_OVRF_BITMASK_SHIFT 16 1632 1633 /**** Cntl register ****/ 1634 /* Set the counter state to disable, enable, or pause: 1635 0x0 - disable: Disable counter. 1636 0x1 - enable: Enable counter. 1637 0x3 - pause: Pause counter. */ 1638 #define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_MASK 0x00000003 1639 #define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT 0 1640 /* Disable counter. */ 1641 #define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_DISABLE \ 1642 (0x0 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT) 1643 /* Enable counter. */ 1644 #define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_ENABLE \ 1645 (0x1 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT) 1646 /* Pause counter. */ 1647 #define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_PAUSE \ 1648 (0x3 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT) 1649 1650 /**** High register ****/ 1651 /* Counter high value */ 1652 #define NB_MC_PMU_COUNTERS_HIGH_COUNTER_MASK 0x0000FFFF 1653 #define NB_MC_PMU_COUNTERS_HIGH_COUNTER_SHIFT 0 1654 1655 /**** version register ****/ 1656 /* Revision number (Minor) */ 1657 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 1658 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_SHIFT 0 1659 /* Revision number (Major) */ 1660 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 1661 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 1662 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V1 2 1663 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V2 3 1664 #define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_VAL_ALPINE_V3 4 1665 /* Date of release */ 1666 #define NB_NB_VERSION_VERSION_DATE_DAY_MASK 0x001F0000 1667 #define NB_NB_VERSION_VERSION_DATE_DAY_SHIFT 16 1668 /* Month of release */ 1669 #define NB_NB_VERSION_VERSION_DATA_MONTH_MASK 0x01E00000 1670 #define NB_NB_VERSION_VERSION_DATA_MONTH_SHIFT 21 1671 /* Year of release (starting from 2000) */ 1672 #define NB_NB_VERSION_VERSION_DATE_YEAR_MASK 0x3E000000 1673 #define NB_NB_VERSION_VERSION_DATE_YEAR_SHIFT 25 1674 /* Reserved */ 1675 #define NB_NB_VERSION_VERSION_RESERVED_MASK 0xC0000000 1676 #define NB_NB_VERSION_VERSION_RESERVED_SHIFT 30 1677 1678 /**** cpu_tgtid register ****/ 1679 /* Target-ID */ 1680 #define NB_SRIOV_CPU_TGTID_VAL_MASK 0x000000FF 1681 #define NB_SRIOV_CPU_TGTID_VAL_SHIFT 0 1682 1683 /**** DRAM_0_Control register ****/ 1684 /* Controller Idle 1685 Indicates to the DDR PHY, if set, that the memory controller is idle */ 1686 #define NB_DRAM_CHANNELS_DRAM_0_CONTROL_DDR_PHY_CTL_IDLE (1 << 0) 1687 /* Disable clear exclusive monitor request from DDR controller to CPU 1688 Clear request is triggered whenever an exlusive monitor inside the DDR controller is being invalidated. */ 1689 #define NB_DRAM_CHANNELS_DRAM_0_CONTROL_DDR_EXMON_REQ_DIS (1 << 1) 1690 1691 /**** DRAM_0_Status register ****/ 1692 /* Bypass Mode: Indicates if set that the PHY is in PLL bypass mod */ 1693 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_DDR_PHY_BYP_MODE (1 << 0) 1694 /* Number of available AXI transactions (used positions) in the DDR controller read address FIFO. */ 1695 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_RAQ_WCOUNT_MASK 0x00000030 1696 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_RAQ_WCOUNT_SHIFT 4 1697 /* Number of available AXI transactions (used positions) in the DDR controller write address FIFO */ 1698 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_WAQ_WCOUNT_0_MASK 0x000000C0 1699 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_WAQ_WCOUNT_0_SHIFT 6 1700 /* Number of available Low priority read CAM slots (free positions) in the DDR controller. 1701 Each slots holds a DRAM burst */ 1702 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_LPR_CREDIT_CNT_MASK 0x00007F00 1703 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_LPR_CREDIT_CNT_SHIFT 8 1704 /* Number of available High priority read CAM slots (free positions) in the DDR controller. 1705 Each slots holds a DRAM burst */ 1706 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_HPR_CREDIT_CNT_MASK 0x003F8000 1707 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_HPR_CREDIT_CNT_SHIFT 15 1708 /* Number of available write CAM slots (free positions) in the DDR controller. 1709 Each slots holds a DRAM burst */ 1710 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_WR_CREDIT_CNT_MASK 0x1FC00000 1711 #define NB_DRAM_CHANNELS_DRAM_0_STATUS_WR_CREDIT_CNT_SHIFT 22 1712 1713 /**** DDR_Int_Cause register ****/ 1714 /* This interrupt is asserted when a correctable ECC error is detected */ 1715 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_ECC_CORRECTED_ERR (1 << 0) 1716 /* This interrupt is asserted when a uncorrectable ECC error is detected */ 1717 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_ECC_UNCORRECTED_ERR (1 << 1) 1718 /* This interrupt is asserted when a parity or CRC error is detected on the DFI interface */ 1719 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR (1 << 2) 1720 /* On-Chip Write data parity error interrupt on output */ 1721 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WDATA_OUT_ERR (1 << 3) 1722 /* This interrupt is asserted when a parity error due to MRS is detected on the DFI interface */ 1723 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR_FATL (1 << 4) 1724 /* This interrupt is asserted when the CRC/parity retry counter reaches it maximum value */ 1725 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR_MAX_REACHED (1 << 5) 1726 /* AXI Read address parity error interrupt. 1727 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read address. */ 1728 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_RADDR_ERR (1 << 6) 1729 /* AXI Read data parity error interrupt. 1730 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read data */ 1731 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_RDATA_ERR (1 << 7) 1732 /* AXI Write address parity error interrupt. 1733 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write address. */ 1734 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WADDR_ERR (1 << 8) 1735 /* AXI Write data parity error interrupt on input. 1736 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write data */ 1737 #define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WDATA_IN_ERR (1 << 9) 1738 1739 /**** Address_Map register ****/ 1740 /* Controls which system address bit will be mapped to DDR row bit 2. 1741 This field is only used when addrmap_part_en == 1 */ 1742 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_MASK 0x0000000F 1743 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_SHIFT 0 1744 /* Controls which system address bit will be mapped to DDR row bit 3. 1745 This field is only used when addrmap_part_en == 1 */ 1746 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B3_MASK 0x000003C0 1747 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B3_SHIFT 6 1748 /* Controls which system address bit will be mapped to DDR row bit 4. 1749 This field is only used when addrmap_part_en == 1 */ 1750 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B4_MASK 0x0000F000 1751 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B4_SHIFT 12 1752 /* Controls which system address bit will be mapped to DDR row bit 5. 1753 This field is only used when addrmap_part_en == 1 */ 1754 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B5_MASK 0x003C0000 1755 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B5_SHIFT 18 1756 /* Enables partitioning of the address mapping control. 1757 When set, addrmap_row_b2-5 are used inside DDR controler instead of the built in address mapping registers */ 1758 #define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_PART_EN (1 << 31) 1759 1760 /**** Reorder_ID_Mask register ****/ 1761 /* DDR Read Reorder buffer ID mask. 1762 If incoming read transaction ID ANDed with mask is equal Reorder_ID_Value, then the transaction is mapped to the DDR controller bypass channel. 1763 Setting this register to 0 will disable the check */ 1764 #define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_MASK 0x003FFFFF 1765 #define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_SHIFT 0 1766 1767 /**** Reorder_ID_Value register ****/ 1768 /* DDR Read Reorder buffer ID value 1769 If incoming read transaction ID ANDed with Reorder_ID_Mask is equal to this register, then the transaction is mapped to the DDR controller bypass channel */ 1770 #define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_MASK 0x003FFFFF 1771 #define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_SHIFT 0 1772 1773 /**** MRR_Control_Status register ****/ 1774 /* DDR4 Mode Register Read Data Valid */ 1775 #define NB_DRAM_CHANNELS_MRR_CONTROL_STATUS_MRR_VLD (1 << 0) 1776 /* MRR Ack, when asserted it clears the mrr_val indication and ready to load new MRR data. Write 1 to clear and then 0 */ 1777 #define NB_DRAM_CHANNELS_MRR_CONTROL_STATUS_MRR_ACK (1 << 16) 1778 1779 /**** pp_config register ****/ 1780 /* Bypass PP module (formality equivalent) */ 1781 #define NB_PUSH_PACKET_PP_CONFIG_FM_BYPASS (1 << 0) 1782 /* Bypass PP module */ 1783 #define NB_PUSH_PACKET_PP_CONFIG_BYPASS (1 << 1) 1784 /* Force Cleanup of entries */ 1785 #define NB_PUSH_PACKET_PP_CONFIG_CLEAR (1 << 2) 1786 /* Enable forwarding DECERR response */ 1787 #define NB_PUSH_PACKET_PP_CONFIG_DECERR_EN (1 << 3) 1788 /* Enable forwarding SLVERR response */ 1789 #define NB_PUSH_PACKET_PP_CONFIG_SLVERR_EN (1 << 4) 1790 /* Enable forwarding of data parity generation */ 1791 #define NB_PUSH_PACKET_PP_CONFIG_PAR_GEN_EN (1 << 5) 1792 /* Select channel on 8K boundaries ([15:13]) instead of 64k boundaries ([18:16]). */ 1793 #define NB_PUSH_PACKET_PP_CONFIG_SEL_8K (1 << 6) 1794 /* Forces awuser to be as configured in ext_awuser register. 1795 Not functional */ 1796 #define NB_PUSH_PACKET_PP_CONFIG_SEL_EXT_AWUSER (1 << 7) 1797 /* Enables PP channel. 1798 1 bit per channel */ 1799 #define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_MASK 0x00030000 1800 #define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_SHIFT 16 1801 1802 #define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE(i) \ 1803 (1 << (NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_SHIFT + i)) 1804 1805 /**** pp_ext_awuser register ****/ 1806 /* Awuser to use on PP transactions 1807 Only applicable if config.sel_ext_awuser is set to 1'b1 1808 Parity bits are still generated per transaction */ 1809 #define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_MASK 0x03FFFFFF 1810 #define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_SHIFT 0 1811 1812 /**** pp_sel_awuser register ****/ 1813 /* Select whether to use addr[63:48] or PP awmisc as tgtid. 1814 Each bit if set to 1 selects the corresponding address bit. Otherwise, selects the corersponding awmis bit. */ 1815 #define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_MASK 0x0000FFFF 1816 #define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_SHIFT 0 1817 1818 #ifdef __cplusplus 1819 } 1820 #endif 1821 1822 #endif /* __AL_HAL_NB_REGS_H__ */ 1823 1824 /** @} end of ... group */ 1825 1826 1827