/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupInstTuning.cpp | 106 auto NewOpcPreferable = [&](unsigned NewOpc, in processInstruction() 134 if (!NewOpcPreferable(NewOpc)) in processInstruction() 139 MI.setDesc(TII->get(NewOpc)); in processInstruction() 149 if (!NewOpcPreferable(NewOpc)) in processInstruction() 154 MI.setDesc(TII->get(NewOpc)); in processInstruction() 168 MI.setDesc(TII->get(NewOpc)); in processInstruction() 190 MI.setDesc(TII->get(NewOpc)); in processInstruction() 202 MI.setDesc(TII->get(NewOpc)); in processInstruction() 210 return ProcessUNPCK(NewOpc, 0x00); in processInstruction() 216 return ProcessUNPCK(NewOpc, 0xff); in processInstruction() [all …]
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H A D | X86CompressEVEX.cpp | 56 uint16_t NewOpc; member 125 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { in performCustomAdjustments() argument 126 (void)NewOpc; in performCustomAdjustments() 133 assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) && in performCustomAdjustments() 149 assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr || in performCustomAdjustments() 150 NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) && in performCustomAdjustments() 243 if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) || in CompressEVEXImpl() 244 !performCustomAdjustments(MI, I->NewOpc)) in CompressEVEXImpl() 248 const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc); in CompressEVEXImpl()
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H A D | X86FixupLEAs.cpp | 810 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local 816 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 822 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 848 unsigned NewOpc = in processInstrForSlow3OpLEA() local 850 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 854 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local 855 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 882 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local 883 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg) in processInstrForSlow3OpLEA() 905 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local [all …]
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H A D | X86ISelDAGToDAG.cpp | 1124 unsigned NewOpc; in PreprocessISelDAG() local 1157 unsigned NewOpc; in PreprocessISelDAG() local 1160 case ISD::SHL: NewOpc = X86ISD::VSHLV; break; in PreprocessISelDAG() 1179 unsigned NewOpc; in PreprocessISelDAG() local 1183 NewOpc = ISD::SIGN_EXTEND; in PreprocessISelDAG() 1185 NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG() 1574 unsigned NewOpc; in PostprocessISelDAG() local 1618 unsigned NewOpc; in PostprocessISelDAG() local 3583 unsigned NewOpc = in foldLoadStoreIntoMemOperand() local 3653 unsigned NewOpc = SelectRegOpcode(Opc); in foldLoadStoreIntoMemOperand() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86EncodingOptimization.cpp | 25 unsigned NewOpc = 0; in optimizeInstFromVEX3ToVEX2() local 95 if (NewOpc) in optimizeInstFromVEX3ToVEX2() 105 unsigned NewOpc; in optimizeShiftRotateWithImmediateOne() local 254 unsigned NewOpc; in optimizeVPCMPWithImmediateOneOrSix() local 256 NewOpc = Opc1; in optimizeVPCMPWithImmediateOneOrSix() 258 NewOpc = Opc2; in optimizeVPCMPWithImmediateOneOrSix() 267 unsigned NewOpc; in optimizeMOVSX() local 291 unsigned NewOpc; in optimizeINCDEC() local 319 unsigned NewOpc; in optimizeMOV() local 374 unsigned NewOpc; in optimizeToFixedRegisterForm() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVExpandPseudoInsts.cpp | 205 unsigned NewOpc; in expandCCOp() local 209 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break; in expandCCOp() 210 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break; in expandCCOp() 211 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break; in expandCCOp() 212 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break; in expandCCOp() 213 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break; in expandCCOp() 214 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break; in expandCCOp() 215 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break; in expandCCOp() 216 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break; in expandCCOp() 217 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break; in expandCCOp() [all …]
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H A D | RISCVFoldMasks.cpp | 95 NewOpc = RISCV::PseudoVMV_V_V_##lmul; \ in convertVMergeToVMv() 97 unsigned NewOpc; in convertVMergeToVMv() local 121 MI.setDesc(TII->get(NewOpc)); in convertVMergeToVMv()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonRDFOpt.cpp | 226 unsigned OpNum, NewOpc; in rewrite() local 229 NewOpc = Hexagon::L2_loadri_io; in rewrite() 233 NewOpc = Hexagon::L2_loadrd_io; in rewrite() 237 NewOpc = Hexagon::V6_vL32b_ai; in rewrite() 241 NewOpc = Hexagon::S2_storeri_io; in rewrite() 245 NewOpc = Hexagon::S2_storerd_io; in rewrite() 249 NewOpc = Hexagon::V6_vS32b_ai; in rewrite() 275 MI.setDesc(HII.get(NewOpc)); in rewrite()
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H A D | HexagonGenPredicate.cpp | 387 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local 389 if (NewOpc == 0) { in convertToPredForm() 392 NewOpc = Hexagon::C2_not; in convertToPredForm() 395 NewOpc = TargetOpcode::COPY; in convertToPredForm() 422 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); in convertToPredForm()
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H A D | HexagonCopyToCombine.cpp | 863 unsigned NewOpc; in emitCombineRR() local 865 NewOpc = Hexagon::A2_combinew; in emitCombineRR() 868 NewOpc = Hexagon::V6_vcombine; in emitCombineRR() 872 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg) in emitCombineRR()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 685 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument 707 switch (NewOpc) { in genInstrWithNewOpc() 709 NewOpc = Mips::BEQZC; in genInstrWithNewOpc() 712 NewOpc = Mips::BNEZC; in genInstrWithNewOpc() 715 NewOpc = Mips::BGEZC; in genInstrWithNewOpc() 718 NewOpc = Mips::BLTZC; in genInstrWithNewOpc() 721 NewOpc = Mips::BEQZC64; in genInstrWithNewOpc() 724 NewOpc = Mips::BNEZC64; in genInstrWithNewOpc() 735 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc() 736 NewOpc == Mips::JIALC64) { in genInstrWithNewOpc() [all …]
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H A D | MipsSEInstrInfo.h | 98 unsigned NewOpc) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1500 unsigned NewOpc; in MergeBaseUpdateLoadStore() local 1543 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore() 1637 unsigned NewOpc; in MergeBaseUpdateLSDouble() local 1653 if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) { in MergeBaseUpdateLSDouble() 1656 assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST); in MergeBaseUpdateLSDouble() 1806 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1830 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 2265 NewOpc = ARM::LDRD; in CanFormLdStDWord() 2267 NewOpc = ARM::STRD; in CanFormLdStDWord() 2269 NewOpc = ARM::t2LDRDi8; in CanFormLdStDWord() [all …]
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H A D | ARMConstantIslandPass.cpp | 1845 unsigned NewOpc = 0; in optimizeThumb2Instructions() local 1866 if (!NewOpc) in optimizeThumb2Instructions() 1896 unsigned NewOpc = 0; in optimizeThumb2Branches() local 1902 NewOpc = ARM::tB; in optimizeThumb2Branches() 1907 NewOpc = ARM::tBcc; in optimizeThumb2Branches() 1912 if (NewOpc) { in optimizeThumb2Branches() 1930 unsigned NewOpc = 0; in optimizeThumb2Branches() member 1936 ImmCmp.NewOpc = 0; in optimizeThumb2Branches() 1944 unsigned NewOpc = 0; in optimizeThumb2Branches() local 1968 ImmCmp.NewOpc = NewOpc; in optimizeThumb2Branches() [all …]
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H A D | Thumb2InstrInfo.cpp | 590 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local 592 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex() 623 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local 633 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex() 646 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex() 651 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex() 711 if (NewOpc != Opcode) in rewriteT2FrameIndex() 712 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex() 755 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
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H A D | ARMInstructionSelector.cpp | 899 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); in select() local 900 if (NewOpc == I.getOpcode()) in select() 902 I.setDesc(TII.get(NewOpc)); in select() 1095 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select() local 1096 if (NewOpc == G_LOAD || NewOpc == G_STORE) in select() 1099 I.setDesc(TII.get(NewOpc)); in select() 1101 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH) in select()
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H A D | ARMExpandPseudoInsts.cpp | 879 unsigned NewOpc = in ExpandMQQPRLoadStore() local 884 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMQQPRLoadStore() 905 if (NewOpc == ARM::VSTMDIA) in ExpandMQQPRLoadStore() 2425 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI() 2466 unsigned NewOpc; in ExpandMI() local 2468 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI() 2469 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI() 2470 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI() 2471 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI() 2760 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostSelectOptimize.cpp | 204 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); in optimizeNZCVDefs() local 207 if (NewOpc) { in optimizeNZCVDefs() 212 II.setDesc(TII->get(NewOpc)); in optimizeNZCVDefs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local 293 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); in transformInstruction() 362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) in transformInstruction()
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H A D | AArch64CondBrTuning.cpp | 98 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode()); in convertToFlagSetting() local 104 TII->get(NewOpc), NewDestReg); in convertToFlagSetting()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 251 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local 254 assert(NewOpc != 0 && "Unknown merged node opcode"); in insertMergedInstruction() 258 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc)); in insertMergedInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
H A D | X86InstructionSelector.cpp | 580 if (NewOpc == Opc) in selectLoadStoreOp() 586 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp() 622 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep() 674 I.setDesc(TII.get(NewOpc)); in selectGlobalValue() 704 unsigned NewOpc; in selectConstant() local 707 NewOpc = X86::MOV8ri; in selectConstant() 710 NewOpc = X86::MOV16ri; in selectConstant() 713 NewOpc = X86::MOV32ri; in selectConstant() 718 NewOpc = X86::MOV64ri32; in selectConstant() 720 NewOpc = X86::MOV64ri; in selectConstant() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUPostLegalizerCombiner.cpp | 368 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN() local 378 assert(MI.getOpcode() != NewOpc); in applyCvtF32UByteN() 379 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
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H A D | SIInstrInfo.cpp | 1149 int NewOpc; in commuteOpcode() local 1153 if (NewOpc != -1) in commuteOpcode() 1155 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode() 1159 if (NewOpc != -1) in commuteOpcode() 1161 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1; in commuteOpcode() 3502 unsigned NewOpc = in FoldImmediate() local 3581 unsigned NewOpc = in FoldImmediate() local 3892 unsigned NewOpc = in convertToThreeAddress() local 3910 unsigned NewOpc = in convertToThreeAddress() local 6011 if (NewOpc < 0) in moveFlatAddrToVGPR() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 829 unsigned NewOpc = Node->getOpcode(); in PromoteFP_TO_INT() local 832 if (NewOpc == ISD::FP_TO_UINT && in PromoteFP_TO_INT() 834 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT() 836 if (NewOpc == ISD::STRICT_FP_TO_UINT && in PromoteFP_TO_INT() 838 NewOpc = ISD::STRICT_FP_TO_SINT; in PromoteFP_TO_INT() 843 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other}, in PromoteFP_TO_INT() 847 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0)); in PromoteFP_TO_INT() 854 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT() 856 NewOpc = ISD::AssertSext; in PromoteFP_TO_INT() 858 Promoted = DAG.getNode(NewOpc, dl, NVT, Promoted, in PromoteFP_TO_INT()
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