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Searched refs:PtrReg (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp331 Register PtrReg = Store.getPointerReg(); in applySplitStoreZero128() local
333 auto HighPtr = B.buildPtrAdd(MRI.getType(PtrReg), PtrReg, in applySplitStoreZero128()
338 B.buildStore(Zero, PtrReg, *LowMMO); in applySplitStoreZero128()
664 Register PtrReg = St->getPointerReg(); in optimizeConsecutiveMemOpAddressing() local
666 PtrReg, MRI, in optimizeConsecutiveMemOpAddressing()
668 GPtrAdd *PtrAdd = cast<GPtrAdd>(MRI.getVRegDef(PtrReg)); in optimizeConsecutiveMemOpAddressing()
H A DAArch64InstructionSelector.cpp2924 const Register PtrReg = LdSt.getPointerReg(); in select() local
2925 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2929 assert(MRI.getType(PtrReg).isPointer() && in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp430 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
431 lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]); in lowerParameter()
450 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
561 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
562 lowerParameterPtr(PtrReg, B, ArgOffset); in lowerFormalArgumentsKernel()
564 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
H A DAMDGPURegisterBankInfo.cpp1089 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1099 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1103 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1107 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0); in applyMappingLoad()
3425 Register PtrReg = MI.getOperand(0).getReg(); in applyMappingImpl() local
3431 unsigned AS = MRI.getType(PtrReg).getAddressSpace(); in applyMappingImpl()
3623 LLT PtrTy = MRI.getType(PtrReg); in getValueMappingForPtr()
3631 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
3642 Register PtrReg = MI.getOperand(1).getReg(); in getInstrMappingForLoad() local
3643 LLT PtrTy = MRI.getType(PtrReg); in getInstrMappingForLoad()
[all …]
H A DAMDGPULegalizerInfo.cpp2974 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
2975 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
2980 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
3032 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3040 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3045 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
3102 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
3106 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
3116 .addUse(PtrReg) in legalizeAtomicCmpXChg()
H A DAMDGPUInstructionSelector.cpp4308 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
4315 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp746 Register PtrReg = Op.getReg(); in replacePtrWithInt() local
747 assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer!"); in replacePtrWithInt()
750 auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg); in replacePtrWithInt()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp765 Register PtrReg = LoadMI->getPointerReg(); in matchCombineLoadWithAndMask() local
797 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
805 B.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, Dst, PtrReg, *NewMMO); in matchCombineLoadWithAndMask()
2299 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2307 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2309 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2312 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2317 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2324 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2329 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
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H A DLegalizerHelper.cpp1334 Register PtrReg = LoadMI.getPointerReg(); in narrowScalar() local
1341 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
3300 Register PtrReg = LoadMI.getPointerReg(); in lowerLoad() local
3338 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); in lowerLoad()
3400 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
3404 PtrReg, *LargeMMO); in lowerLoad()
3442 Register PtrReg = StoreMI.getPointerReg(); in lowerStore() local
3470 MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO); in lowerStore()
3517 LLT PtrTy = MRI.getType(PtrReg); in lowerStore()
3521 MIRBuilder.buildPtrAdd(PtrTy, PtrReg, OffsetCst); in lowerStore()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12074 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
12136 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
12141 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
12162 .addReg(PtrReg); in EmitPartwordAtomicBinary()
12205 .addReg(PtrReg); in EmitPartwordAtomicBinary()
13066 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
13135 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
13140 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
13172 .addReg(PtrReg); in EmitInstrWithCustomInserter()
13196 .addReg(PtrReg); in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5114 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
5115 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()