/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | micrel-ksz90x1.txt | 49 - rxdv-skew-ps : Skew control of RX CTL pad 52 - rxd0-skew-ps : Skew control of RX data 0 pad 53 - rxd1-skew-ps : Skew control of RX data 1 pad 54 - rxd2-skew-ps : Skew control of RX data 2 pad 55 - rxd3-skew-ps : Skew control of RX data 3 pad 137 - rxc-skew-ps : Skew control of RX clock pad 142 - rxdv-skew-ps : Skew control of RX CTL pad 144 - rxd0-skew-ps : Skew control of RX data 0 pad 145 - rxd1-skew-ps : Skew control of RX data 1 pad 146 - rxd2-skew-ps : Skew control of RX data 2 pad [all …]
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H A D | xlnx,axi-ethernet.yaml | 13 segments of memory for buffering TX and RX, as well as the capability of 14 offloading TX/RX checksum calculation off the processor. 46 present DMA node should contains TX/RX DMA interrupts else DMA interrupt 81 RX checksum offload. 0 or empty for disabling RX checksum offload, 82 1 to enable partial RX checksum offload and 2 to enable full RX 113 from that device (DMA registers and DMA TX/RX interrupts) rather than 128 description: TX and RX DMA channel phandle
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H A D | xilinx_axienet.txt | 7 segments of memory for buffering TX and RX, as well as the capability of 8 offloading TX/RX checksum calculation off the processor. 24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA, 26 specified, the TX/RX DMA interrupts should be on that node 41 - xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload 66 device (DMA registers and DMA TX/RX interrupts) rather
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H A D | lantiq,xrx200-net.txt | 9 - interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for 10 : the TX interrupt and "rx" for the RX interrupt.
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H A D | ethernet-controller.yaml | 78 # RX and TX delays are added by the MAC when required 81 # RGMII with internal RX and TX delays provided by the PHY, 82 # the MAC should not add the RX or TX delays in this case 85 # RGMII with internal RX delay provided by the PHY, the MAC 86 # should not add an RX delay in this case 279 controllers that have configurable RX internal delays. If this 280 property is present then the MAC applies the RX delay.
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H A D | intel,ixp4xx-hss.yaml | 39 - description: phandle to the RX trigger queue on the NPE 41 description: phandle to the RX trigger queue on the NPE 55 - description: phandle to the RX queue on the NPE 57 description: phandle to the packet RX queue on the NPE
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | starfive,jh7110-syscrg.yaml | 23 - description: GMAC1 RMII reference or GMAC1 RGMII RX 26 - description: External I2S RX bit clock 27 - description: External I2S RX left/right channel clock 37 - description: GMAC1 RGMII RX 40 - description: External I2S RX bit clock 41 - description: External I2S RX left/right channel clock
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H A D | qcom,sa8775p-gcc.yaml | 26 - description: UFS memory first RX symbol clock 27 - description: UFS memory second RX symbol clock 29 - description: UFS card first RX symbol clock 30 - description: UFS card second RX symbol clock
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H A D | starfive,jh7110-aoncrg.yaml | 23 - description: GMAC0 RMII reference or GMAC0 RGMII RX 30 - description: GMAC0 RMII reference or GMAC0 RGMII RX 31 - description: STG AXI/AHB or GMAC0 RGMII RX 39 - description: GMAC0 RGMII RX
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H A D | qcom,gcc-sc8280xp.yaml | 26 - description: UFS memory first RX symbol clock 27 - description: UFS memory second RX symbol clock 29 - description: UFS card first RX symbol clock 30 - description: UFS card second RX symbol clock
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H A D | qcom,gcc-apq8084.yaml | 32 - description: UFS RX symbol 0 clock 33 - description: UFS RX symbol 1 clock 37 - description: SATA RX clock
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/freebsd/sys/contrib/device-tree/Bindings/dma/ |
H A D | intel,ldma.yaml | 67 DMA byte enable is only valid for DMA write(RX). 79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst; 80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16. 81 It only applies to RX DMA and memcopy DMA.
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/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | nvidia,tegra30-ahub.txt | 59 For RX CIFs, the numbers indicate the register number within AHUB routing 60 register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
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H A D | allwinner,sun4i-a10-i2s.yaml | 94 - description: RX DMA Channel 98 data. In such a case, the RX DMA channel is to be omitted. 108 data. In such a case, the RX name is to be omitted. 114 - description: RX DMA Channel
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H A D | rockchip,i2s-tdm.yaml | 52 - description: clock for RX 103 description: Use TX BCLK/LRCK for both TX and RX. 107 description: Use RX BCLK/LRCK for both TX and RX. 115 Defines the mapping of I2S RX sdis to I2S data bus lines.
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/freebsd/sys/dev/qat/qat_common/ |
H A D | adf_cfg_instance.c | 41 bundle->rings[i]->mode == RX) { in crypto_instance_init() 53 bundle->rings[i]->mode == RX) { in crypto_instance_init() 85 bundle->rings[i]->mode == RX) { in dc_instance_init() 117 bundle->rings[i]->mode == RX) { in asym_instance_init() 149 bundle->rings[i]->mode == RX) { in sym_instance_init()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYInstrFormats.td | 77 // Format< OP[6] | RZ[5] | RX[5] | IMM[16] > 129 // Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] > 168 // Format< OP[6] | SOP[5] | RX[5] | IMM16[16] > 181 // Format< OP[6] | SOP[5] | RX[5] | OFFSET[16] > 195 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] > 236 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] > 242 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] > 400 // Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]> 430 // Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]> 444 // Format< OP[6] | RZ[5] | RX[5] | SOP[6] | SIZE[5] | LSB[5]> [all …]
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/freebsd/sys/contrib/device-tree/Bindings/media/ |
H A D | nxp,imx8-isi.yaml | 17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. 86 description: MIPI CSI-2 RX 102 description: MIPI CSI-2 RX 0 104 description: MIPI CSI-2 RX 1
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H A D | nxp,imx8mq-mipi-csi2.yaml | 13 This binding covers the CSI-2 RX PHY and host controller included in the 27 - description: core is the RX Controller Core Clock input. This clock 29 byteclock from the RX DPHY. 31 clock that the RX DPHY receives.
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/ |
H A D | meson-gxbb-nanopi-k2.dts | 236 gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", 247 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", 248 "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", 249 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", 285 "Bluetooth UART TX", "Bluetooth UART RX",
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H A D | meson-gxbb-odroidc2.dts | 279 gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", 290 "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", 291 "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", 292 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | qcom,qmp-usb-phy.yaml | 297 - description: RX lane 1 300 - description: RX lane 2 316 - description: RX lane 1 319 - description: RX lane 2 342 - description: RX 362 - description: RX
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H A D | qcom,qmp-ufs-phy.yaml | 173 - description: RX lane 1 176 - description: RX lane 2 191 - description: RX 209 - description: RX
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | omap2430.dtsi | 181 <60>, /* RX interrupt */ 182 <61>; /* RX overflow interrupt */ 198 <63>; /* RX interrupt */ 214 <90>; /* RX interrupt */ 230 <55>; /* RX interrupt */ 246 <82>; /* RX interrupt */
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx6ull-dhcom-drc02.dts | 23 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. 55 * GPIO line, however the i.MX6ULL UART driver assumes RX happens 57 * line. Hence, the RX is always enabled here.
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