| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInst.cpp | 21 void MCOperand::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
27 if (RegInfo) in print()
28 OS << RegInfo->getName(getReg()); in print()
41 getInst()->print(OS, RegInfo); in print()
72 void MCInst::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
76 getOperand(i).print(OS, RegInfo); in print()
83 const MCRegisterInfo *RegInfo) const { in dump_pretty()
85 dump_pretty(OS, InstName, Separator, RegInfo); in dump_pretty()
89 const MCRegisterInfo *RegInfo) const { in dump_pretty()
98 getOperand(i).print(OS, RegInfo); in dump_pretty()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 93 const MipsRegisterInfo &RegInfo; member in __anon3ad019b90111::ExpandPseudo
102 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
327 &RegInfo, 0); in expandBuildPairF64()
329 &RegInfo, 4); in expandBuildPairF64()
408 const MipsRegisterInfo &RegInfo = in emitPrologue() local
538 if (RegInfo.hasStackRealignment(MF)) { in emitPrologue()
[all …]
|
| H A D | MipsSERegisterInfo.cpp | 156 const MipsRegisterInfo *RegInfo = in eliminateFI() local
183 else if (RegInfo->hasStackRealignment(MF)) { in eliminateFI()
224 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
225 Register Reg = RegInfo.createVirtualRegister(PtrRC); in eliminateFI()
|
| H A D | Mips16ISelDAGToDAG.cpp | 72 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
|
| H A D | MipsSEISelLowering.cpp | 3054 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3060 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3123 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3129 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3177 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3240 Register Wt = RegInfo.createVirtualRegister( in emitINSERT_FW()
3434 Register Wt1 = RegInfo.createVirtualRegister( in emitFILL_FW()
3437 Register Wt2 = RegInfo.createVirtualRegister( in emitFILL_FW()
3567 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO()
3809 Register Ws1 = RegInfo.createVirtualRegister(RC); in emitFEXP2_W_1()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcFrameLowering.cpp | 94 const SparcRegisterInfo &RegInfo = in emitPrologue() local
100 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
102 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
151 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue()
164 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
165 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue()
256 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
260 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
269 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local
287 } else if (RegInfo->hasStackRealignment(MF)) { in getFrameIndexReference()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineUniformityAnalysis.cpp | 71 const auto &RegInfo = F.getRegInfo(); in pushUsers() local
72 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) { in pushUsers()
115 const auto &RegInfo = F.getRegInfo(); in propagateTemporalDivergence() local
122 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) { in propagateTemporalDivergence()
140 const auto &RegInfo = F.getRegInfo(); in isDivergentUse() local
141 auto *Def = RegInfo.getOneDef(Reg); in isDivergentUse()
|
| H A D | DetectDeadLanes.cpp | 216 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local
217 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep()
222 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep()
401 const DeadLaneDetector::VRegInfo &RegInfo) const;
418 const MachineOperand &MO, const DeadLaneDetector::VRegInfo &RegInfo) const { in isUndefRegAtInput()
421 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput()
510 const DeadLaneDetector::VRegInfo &RegInfo = DLD.getVRegInfo(RegIdx); in modifySubRegisterOperandStatus() local
511 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in modifySubRegisterOperandStatus()
519 if (isUndefRegAtInput(MO, RegInfo)) { in modifySubRegisterOperandStatus()
|
| H A D | TargetFrameLoweringImpl.cpp | 138 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in allocateScavengingFrameIndexesNearIncomingSP() local
139 return RegInfo->useFPForScavengingIndex(MF) && in allocateScavengingFrameIndexesNearIncomingSP()
140 !RegInfo->hasStackRealignment(MF); in allocateScavengingFrameIndexesNearIncomingSP()
|
| H A D | TargetRegisterInfo.cpp | 176 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
178 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { in printRegClassOrBank()
179 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
180 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
181 else if (RegInfo.getRegBankOrNull(Reg)) in printRegClassOrBank()
182 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); in printRegClassOrBank()
185 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && in printRegClassOrBank()
|
| H A D | MIRPrinter.cpp | 286 const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
289 OS << printRegClassOrBank(Reg, RegInfo, TRI); in printRegClassOrBank()
309 const MachineRegisterInfo &RegInfo, in convert() argument
311 MF.TracksRegLiveness = RegInfo.tracksLiveness(); in convert()
314 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) { in convert()
318 if (RegInfo.getVRegName(Reg) != "") in convert()
320 ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); in convert()
321 Register PreferredReg = RegInfo.getSimpleHint(Reg); in convert()
328 for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) { in convert()
337 if (RegInfo.isUpdatedCSRsInitialized()) { in convert()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallFrameOptimization.cpp | 114 const X86RegisterInfo &RegInfo,
242 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local
244 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction()
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
359 const X86RegisterInfo &RegInfo = in collectCallInfo() local
383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo()
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
|
| H A D | X86MachineFunctionInfo.cpp | 27 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
29 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | ControlHeightReduction.cpp | 132 struct RegInfo { struct
133 RegInfo() = default;
200 for (RegInfo &RI : RegInfos) in addSub()
249 for (const RegInfo &RI : RegInfos) in contains()
270 SmallVector<RegInfo, 8> CHRRegions;
447 for (const RegInfo &RI : RegInfos) { in print()
771 RegInfo RI(R); in findScope()
833 RegInfo RI(R); in findScope()
873 RegInfo &RI = Scope->RegInfos[0]; in checkScopeHoistable()
1107 for (RegInfo &RI : Scope->RegInfos) in getSelectsInScope()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1FrameLowering.cpp | 119 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
154 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
169 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
170 Register BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
450 if (RegInfo->hasStackRealignment(MF)) { in emitPrologue()
485 if (RegInfo->hasBasePointer(MF)) in emitPrologue()
507 const ThumbRegisterInfo *RegInfo = in emitEpilogue() local
516 Register FramePtr = RegInfo->getFrameRegister(MF); in emitEpilogue()
639 const ThumbRegisterInfo *RegInfo = in emitPopSpecialFixUp() local
1102 Register FPReg = RegInfo->getFrameRegister(MF); in spillCalleeSavedRegisters()
[all …]
|
| H A D | ARMFrameLowering.cpp | 1253 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
1459 if (RegInfo->hasStackRealignment(MF)) { in ResolveFrameIndexReference()
1465 assert(RegInfo->hasBasePointer(MF) && in ResolveFrameIndexReference()
1514 if (RegInfo->hasBasePointer(MF)) { in ResolveFrameIndexReference()
1515 FrameReg = RegInfo->getBaseRegister(); in ResolveFrameIndexReference()
2328 if (RegInfo->hasBasePointer(MF)) in determineCalleeSaves()
2474 if (RegInfo->hasBasePointer(MF)) in determineCalleeSaves()
3153 auto RegInfo = STI.getRegisterInfo(); in adjustForSegmentedStacks() local
3257 auto RegInfo = STI.getRegisterInfo(); in adjustForSegmentedStacks() local
3278 RegInfo->emitLoadConstPool( in adjustForSegmentedStacks()
[all …]
|
| H A D | Thumb1InstrInfo.cpp | 59 const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); in copyPhysReg() local
60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
64 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEFrameLowering.cpp | 314 const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); in emitPrologue() local
316 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
322 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
422 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
426 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
448 const VERegisterInfo *RegInfo = STI.getRegisterInfo(); in getFrameIndexReference() local
459 if (RegInfo->hasStackRealignment(MF) && !isFixed) { in getFrameIndexReference()
470 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 458 RegInfo->hasStackRealignment(MF)) in hasFP()
1118 if (RegInfo->hasStackRealignment(MF)) in shouldCombineCSRLocalStackBump()
2647 FrameReg = RegInfo->getFrameRegister(MF); in resolveFrameOffsetReference()
2651 FrameReg = RegInfo->hasBasePointer(MF) ? RegInfo->getBaseRegister() in resolveFrameOffsetReference()
2663 FrameReg = RegInfo->getFrameRegister(MF); in resolveFrameOffsetReference()
2668 if (RegInfo->hasBasePointer(MF)) in resolveFrameOffsetReference()
2669 FrameReg = RegInfo->getBaseRegister(); in resolveFrameOffsetReference()
3287 !RegInfo->isReservedReg(MF, Reg)) { in determineCalleeSaves()
3344 << ' ' << printReg(Reg, RegInfo); in determineCalleeSaves()
3470 unsigned Size = RegInfo->getSpillSize(*RC); in assignCalleeSavedSpillSlots()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.h | 26 const NVPTXRegisterInfo RegInfo; variable
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
|
| H A D | NVPTXInstrInfo.cpp | 30 NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {} in NVPTXInstrInfo()
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInst.h | 176 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
228 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
236 const MCRegisterInfo *RegInfo = nullptr) const;
238 const MCRegisterInfo *RegInfo = nullptr) const;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 314 unsigned LR = RegInfo->getRARegister(); in determineFrameLayout()
391 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
534 bool HasBP = RegInfo->hasBasePointer(MF); in twoUniqueScratchRegsRequired()
565 if (!RegInfo || !FI) in stackUpdateCanBeMoved()
644 bool HasBP = RegInfo->hasBasePointer(MF); in emitPrologue()
1262 bool HasBP = RegInfo->hasBasePointer(MF); in inlineStackProbe()
1571 bool HasBP = RegInfo->hasBasePointer(MF); in emitEpilogue()
1990 unsigned LR = RegInfo->getRARegister(); in determineCalleeSaves()
2010 if (!BPSI && RegInfo->hasBasePointer(MF)) { in determineCalleeSaves()
2031 if (RegInfo->hasBasePointer(MF)) in determineCalleeSaves()
[all …]
|
| /freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterContextPOSIX_s390x.h | 45 struct RegInfo { struct
55 RegInfo m_reg_info; argument
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchSubtarget.h | 54 LoongArchRegisterInfo RegInfo; variable
87 return &RegInfo; in getRegisterInfo()
|