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Searched refs:Regs (Results 1 – 25 of 94) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp149 for (auto Reg : Regs) { in getFrameHelperName()
316 assert(Regs.size() >= 2); in getOrCreateFrameHelper()
332 auto LRIdx = std::distance(Regs.begin(), llvm::find(Regs, AArch64::LR)); in getOrCreateFrameHelper()
338 emitStore(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], in getOrCreateFrameHelper()
347 emitStore(MF, MBB, MBB.end(), TII, Regs[I - 1], Regs[I], Size - I - 1, in getOrCreateFrameHelper()
373 emitLoad(MF, MBB, MBB.end(), TII, Regs[I], Regs[I + 1], Size - I - 2, in getOrCreateFrameHelper()
376 emitLoad(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], Size, in getOrCreateFrameHelper()
519 emitLoad(MF, MBB, MBBI, *TII, Regs[I], Regs[I + 1], Size - I - 2, false); in lowerEpilog()
521 emitLoad(MF, MBB, MBBI, *TII, Regs[Size - 2], Regs[Size - 1], Size, true); in lowerEpilog()
609 emitStore(MF, MBB, MBBI, *TII, Regs[Size - 2], Regs[Size - 1], -Size, true); in lowerProlog()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h316 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
317 if (!isAllocated(Regs[i])) in getFirstUnallocated()
319 return Regs.size(); in getFirstUnallocated()
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
351 if (FirstUnalloc == Regs.size()) in AllocateReg()
355 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
364 if (RegsRequired > Regs.size()) in AllocateRegBlock()
372 if (isAllocated(Regs[StartIdx + BlockIdx])) { in AllocateRegBlock()
380 MarkAllocated(Regs[StartIdx + BlockIdx]); in AllocateRegBlock()
382 return Regs[StartIdx]; in AllocateRegBlock()
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H A DRegisterPressure.h276 RegSet Regs; variable
298 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
299 if (I == Regs.end()) in contains()
308 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
321 RegSet::iterator I = Regs.find(SparseIndex); in erase()
322 if (I == Regs.end()) in erase()
330 return Regs.size(); in size()
335 for (const IndexMaskPair &P : Regs) { in appendTo()
412 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
H A DMachineOutliner.h167 bool isAnyUnavailableAcrossOrOutOfSeq(std::initializer_list<Register> Regs, in isAnyUnavailableAcrossOrOutOfSeq()
171 return any_of(Regs, [&](Register Reg) { in isAnyUnavailableAcrossOrOutOfSeq()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp351 assert(OrigRegs[0] == Regs[0]); in buildCopyFromRegs()
356 Regs.size() == 1) { in buildCopyFromRegs()
368 Register SrcReg = Regs[0]; in buildCopyFromRegs()
409 SmallVector<Register> CastRegs(Regs.begin(), Regs.end()); in buildCopyFromRegs()
417 Regs.size() == 1) { in buildCopyFromRegs()
455 for (Register Reg : Regs) in buildCopyFromRegs()
474 Regs = Regs.drop_front(PartsPerElt); in buildCopyFromRegs()
485 if (NumElts == Regs.size()) in buildCopyFromRegs()
503 for (Register R : Regs) { in buildCopyFromRegs()
750 Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end()); in handleAssignments()
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H A DInlineAsmLowering.cpp35 SmallVector<Register, 1> Regs; member in __anon316a06300111::GISelAsmOperandInfo
132 OpInfo.Regs.push_back(R); in getRegistersForValue()
346 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
369 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
492 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
499 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm()
520 Inst.addReg(OpInfo.Regs[0]); in lowerInlineAsm()
531 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
557 if (OpInfo.Regs.empty()) in lowerInlineAsm()
563 if (OpInfo.Regs.size() > 1) { in lowerInlineAsm()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp390 for (auto &RE : Regs) { in EmitRegMappingTables()
451 for (auto &RE : Regs) { in EmitRegMappingTables()
515 for (auto &RE : Regs) { in EmitRegMapping()
905 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { in runMCDesc()
984 for (const auto &Reg : Regs) { in runMCDesc()
1084 for (const auto &RE : Regs) { in runMCDesc()
1111 EmitRegMapping(OS, Regs, false); in runMCDesc()
1444 for (const auto &Reg : Regs) in runTargetDesc()
1454 for (const auto &Reg : Regs) { in runTargetDesc()
1670 EmitRegMapping(OS, Regs, true); in runTargetDesc()
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H A DCodeGenRegisters.cpp208 RegI(Regs.begin()), RegE(Regs.end()) { in RegUnitIterator()
1180 if (!Regs.empty() && Regs[0]->isSubClassOf("X86Reg")) { in CodeGenRegBank()
1191 Regs.insert(Regs.end(), TupRegs.begin(), TupRegs.end()); in CodeGenRegBank()
1194 llvm::sort(Regs, LessRecordRegister()); in CodeGenRegBank()
1197 getReg(Regs[i]); in CodeGenRegBank()
1202 getReg(Regs[i]); in CodeGenRegBank()
1668 CodeGenRegister::Vec Regs; member
1698 if (Regs.empty()) in computeUberSets()
1735 USet->Regs.push_back(&Reg); in computeUberSets()
1772 : I->Regs) dbgs() in computeUberWeights()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h63 SmallVector<Register, 4> Regs; member
81 ArgInfo(ArrayRef<Register> Regs, Type *Ty, unsigned OrigIndex,
84 : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()), in BaseArgInfo()
86 if (!Regs.empty() && Flags.empty()) in BaseArgInfo()
90 (Regs.empty() || Regs[0] == 0)) && in BaseArgInfo()
94 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue, unsigned OrigIndex,
97 : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed, &OrigValue) {}
287 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA); in assignValueToAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp923 auto *Regs = in isXPLeafCandidate() local
1074 SavedRegs.set(Regs.getFramePointerRegister()); in determineCalleeSaves()
1104 MIB.addReg(Regs.getStackPointerRegister()); in spillCalleeSavedRegisters()
1172 .addReg(Regs.getStackPointerRegister()) in restoreCalleeSavedRegisters()
1184 MIB.addReg(Regs.getStackPointerRegister()); in restoreCalleeSavedRegisters()
1279 Regs.getFramePointerRegister()) in emitPrologue()
1280 .addReg(Regs.getStackPointerRegister()); in emitPrologue()
1286 B.addLiveIn(Regs.getFramePointerRegister()); in emitPrologue()
1305 .addReg(Regs.getStackPointerRegister()) in emitPrologue()
1481 auto *Regs = in determineFrameLayout() local
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H A DSystemZRegisterInfo.cpp243 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
245 return Regs->getCalleeSavedRegs(MF); in getCalleeSavedRegs()
253 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
254 return Regs->getCallPreservedMask(MF, CC); in getCallPreservedMask()
262 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
265 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true); in getReservedRegs()
270 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true); in getReservedRegs()
435 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getFrameRegister() local
437 return TFI->hasFP(MF) ? Regs->getFramePointerRegister() in getFrameRegister()
438 : Regs->getStackPointerRegister(); in getFrameRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.cpp110 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
111 while (Regs) { in EmitVFPRegSave()
113 auto RangeMSB = llvm::bit_width(Regs); in EmitVFPRegSave()
114 auto RangeLen = llvm::countl_one(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
124 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DHWEventListener.h78 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
81 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
99 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
101 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp872 const unsigned *Regs; in parseRegister() local
887 if (Regs[Reg.Num] == 0) in parseRegister()
1113 const unsigned *Regs; in parseAddress() local
1115 case GR32Reg: Regs = SystemZMC::GR32Regs; break; in parseAddress()
1116 case GR64Reg: Regs = SystemZMC::GR64Regs; break; in parseAddress()
1126 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num]; in parseAddress()
1142 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num]; in parseAddress()
1148 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
1156 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
1174 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num]; in parseAddress()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp2046 Regs[I] = Regs[I + 1]; in insertMultibyteShift()
2050 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0); in insertMultibyteShift()
2053 Regs = Regs.drop_back(1); in insertMultibyteShift()
2066 .addReg(Regs[0].first, 0, Regs[0].second) in insertMultibyteShift()
2067 .addReg(Regs[0].first, 0, Regs[0].second); in insertMultibyteShift()
2077 Regs[I] = Regs[I - 1]; in insertMultibyteShift()
2084 Regs = Regs.drop_front(1); in insertMultibyteShift()
2115 .addReg(Regs[Idx].first, 0, Regs[Idx].second); in insertMultibyteShift()
2147 Register In = Regs[I].first; in insertMultibyteShift()
2158 Regs[I] = std::pair(Out, 0); in insertMultibyteShift()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVCallLowering.cpp406 if (Info.OrigRet.Regs.size() > 1) in lowerCall()
426 Info.OrigRet.Regs.empty() ? Register(0) : Info.OrigRet.Regs[0]; in lowerCall()
438 assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs"); in lowerCall()
439 ArgVRegs.push_back(Arg.Regs[0]); in lowerCall()
441 if (!GR->getSPIRVTypeForVReg(Arg.Regs[0])) in lowerCall()
442 GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MIRBuilder.getMF()); in lowerCall()
486 if (Arg.Regs.size() > 1) in lowerCall()
488 MIB.addUse(Arg.Regs[0]); in lowerCall()
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/
H A DTaint.cpp139 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
141 Regs = F.add(Regs, SubRegion, Kind); in addPartialTaint()
142 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs); in addPartialTaint()
283 if (const TaintedSubRegions *Regs = in getTaintedSymbolsImpl() local
286 for (auto I : *Regs) { in getTaintedSymbolsImpl()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp329 SmallVector<int, 4> Regs; in visitSoftInstr() local
341 auto I = partition_point(Regs, [&](int I) { in visitSoftInstr()
344 Regs.insert(I, rx); in visitSoftInstr()
350 while (!Regs.empty()) { in visitSoftInstr()
352 dv = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
H A DAggressiveAntiDepBreaker.cpp80 std::vector<unsigned> &Regs, in GetGroupRegs() argument
85 Regs.push_back(Reg); in GetGroupRegs()
546 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
547 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
548 assert(!Regs.empty() && "Empty register group!"); in FindSuitableFreeRegisters()
549 if (Regs.empty()) in FindSuitableFreeRegisters()
557 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters()
576 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters()
637 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp160 auto Regs = getRegisters(); in getRegister() local
161 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
162 if (It == Regs.end()) in getRegister()
671 auto Regs = getRegisters(); in toString() local
672 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { in toString()
673 if (I != Regs.begin()) in toString()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp312 Register ValVReg = Arg.Regs[RegIndex]; in assignValueToAddress()
445 if (CurVReg != CurArgInfo.Regs[0]) { in lowerReturn()
446 CurArgInfo.Regs[0] = CurVReg; in lowerReturn()
673 assert(OrigArg.Regs.size() == 1 && in lowerFormalArguments()
674 MRI.getType(OrigArg.Regs[0]).getSizeInBits() == 1 && in lowerFormalArguments()
680 Register OrigReg = OrigArg.Regs[0]; in lowerFormalArguments()
682 OrigArg.Regs[0] = WideReg; in lowerFormalArguments()
1238 assert(OutArg.Regs.size() == 1 && in lowerCall()
1239 MRI.getType(OutArg.Regs[0]).getSizeInBits() == 1 && in lowerCall()
1244 OutArg.Regs[0] = in lowerCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMachineFunctionInfo.h148 void setRVPushRegs(unsigned Regs) { RVPushRegs = Regs; }
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp182 Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end()); in assignCustomValue()
183 Arg.Regs = { CopyLo.getReg(0), CopyHi.getReg(0) }; in assignCustomValue()
270 MIRBuilder.buildUnmerge({LLT::scalar(32), LLT::scalar(32)}, Arg.Regs[0]); in assignCustomValue()
274 Arg.OrigRegs.assign(Arg.Regs.begin(), Arg.Regs.end()); in assignCustomValue()
275 Arg.Regs = { Lo, Hi }; in assignCustomValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp180 ArrayRef<std::pair<unsigned, bool>> Regs,
186 ArrayRef<std::pair<unsigned, bool>> Regs,
631 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti() argument
633 unsigned NumRegs = Regs.size(); in CreateLoadStoreMulti()
647 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()
687 NewBase = Regs[NumRegs-1].first; in CreateLoadStoreMulti()
838 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreDouble() argument
844 assert(Regs.size() == 2); in CreateLoadStoreDouble()
848 MIB.addReg(Regs[0].first, RegState::Define) in CreateLoadStoreDouble()
851 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp258 ? extendRegister(Arg.Regs[ValRegIndex], VA) in assignValueToAddress()
259 : Arg.Regs[ValRegIndex]; in assignValueToAddress()
348 if (Reg != RetInfo.Regs[0]) { in lowerReturnVal()
349 RetInfo.Regs[0] = Reg; in lowerReturnVal()
448 assert(SplitArg.Regs.size() == 1); in lowerParameter()
450 B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO); in lowerParameter()
1217 assert(ExecArg.Regs.size() == 1 && "Too many regs for EXEC"); in lowerTailCall()
1225 MIB.addReg(ExecArg.Regs[0]); in lowerTailCall()
1362 assert(Callee.Regs.size() == 1 && "Too many regs for the callee"); in lowerChainCall()
1363 Info.Callee = MachineOperand::CreateReg(Callee.Regs[0], false); in lowerChainCall()
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