/freebsd/sys/contrib/device-tree/Bindings/net/can/ |
H A D | bosch,m_can.yaml | 57 and each element(e.g Rx FIFO or Tx Buffer and etc) number 72 Rx FIFO 0 0-64 elements / 0-1152 words 73 Rx FIFO 1 0-64 elements / 0-1152 words 74 Rx Buffers 0-64 elements / 0-1152 words 92 - description: Rx FIFO 0 0-64 elements / 0-1152 words 95 - description: Rx FIFO 1 0-64 elements / 0-1152 words 98 - description: Rx Buffers 0-64 elements / 0-1152 words
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H A D | xilinx_can.txt | 20 - rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in 21 sequential Rx mode). 23 - rx-mailbox-count : Can Rx mailbox buffer count (CAN FD in mailbox Rx
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H A D | xilinx,can.yaml | 43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
H A D | fsl,cpm1-tsa.yaml | 59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx 60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. 85 Indicates the delay between the Rx sync and the first bit of the Rx 119 A list of tuple that indicates the Tx or Rx time-slots routes. 127 The source (Tx) or destination (Rx) serial interface
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/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | nvidia,tegra210-admaif.yaml | 14 ADMAIF Rx channel. 66 DMA channel specifiers, equally divided for Tx and Rx. 73 Should be "rx1", "rx2" ... "rx10" for DMA Rx channel 82 DMA channel specifiers, equally divided for Tx and Rx. 89 Should be "rx1", "rx2" ... "rx20" for DMA Rx channel
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | qcom,gcc-sm8350.yaml | 28 - description: UFS card Rx symbol 0 clock source (Optional clock) 29 - description: UFS card Rx symbol 1 clock source (Optional clock) 31 - description: UFS phy Rx symbol 0 clock source (Optional clock) 32 - description: UFS phy Rx symbol 1 clock source (Optional clock)
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H A D | qcom,sm4450-gcc.yaml | 27 - description: UFS Phy Rx symbol 0 clock source 28 - description: UFS Phy Rx symbol 1 clock source
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H A D | qcom,sm8550-gcc.yaml | 29 - description: UFS Phy Rx symbol 0 clock source 30 - description: UFS Phy Rx symbol 1 clock source
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H A D | qcom,sm8650-gcc.yaml | 30 - description: UFS Phy Rx symbol 0 clock source 31 - description: UFS Phy Rx symbol 1 clock source
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H A D | qcom,gcc-sm8450.yaml | 29 - description: UFS Phy Rx symbol 0 clock source (Optional clock) 30 - description: UFS Phy Rx symbol 1 clock source (Optional clock)
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstr64Bit.td | 1196 def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>; 1197 def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>; 1205 def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>; 1206 def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>; 1208 def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>; 1209 def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>; 1211 def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>; 1212 def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>; 1223 def : InstAlias<"mtdar $Rx", (MTSPR8 19, g8rc:$Rx)>; 1224 def : InstAlias<"mfdar $Rx", (MFSPR8 g8rc:$Rx, 19)>; [all …]
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H A D | PPCInstrInfo.td | 2743 def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2744 def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 4532 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4533 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4534 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4538 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4539 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4561 def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4562 def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4564 def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx6qdl-dhcom-drc02.dtsi | 14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD 72 * Due to the use of can2 the signals for can2 Tx and Rx are routed to 110 * can2 Tx and Rx.
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | altera_tse.txt | 14 "rx_csr" : xDMA Rx dispatcher control and status space region 15 "rx_desc": MSGDMA Rx dispatcher descriptor space region 16 "rx_resp": MSGDMA Rx dispatcher response space region 20 "rx_irq": xDMA Rx dispatcher interrupt
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H A D | sff,sfp.txt | 28 - rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate 29 Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
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H A D | amd-xgbe.txt | 8 - SerDes Rx/Tx registers 18 correct Rx interrupt watchdog timer value on a DMA channel 28 - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
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H A D | sff,sfp.yaml | 60 GPIO phandle and a specifier of the Rx Signaling Rate Select (AKA RS0) 61 output gpio signal, low - low Rx rate, high - high Rx rate Must not be
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H A D | xlnx,axi-ethernet.yaml | 43 - description: Rx DMA interrupt 54 Set to allocated memory buffer for Rx/Tx in the hardware. 135 Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel
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/freebsd/sys/contrib/device-tree/Bindings/serial/ |
H A D | mtk-uart.txt | 33 index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to 34 support Rx in-band wake up. If one would like to use this feature, 35 one must create an addtional pinctrl to reconfigure Rx pin to normal
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/freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
H A D | ti,secure-proxy.yaml | 47 Contains the interrupt name information for the Rx interrupt path for 54 Contains the interrupt information for the Rx interrupt path for secure
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/freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
H A D | keystone-navigator-dma.txt | 47 - Rx DMA channel configuration register region (rxchan). 49 - Rx DMA flow configuration register region (rxflow). 57 - ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | microchip,sparx5-serdes.yaml | 20 * Rx variable gain control 21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
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H A D | cdns,dphy-rx.yaml | 7 title: Cadence DPHY Rx
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/freebsd/sys/contrib/device-tree/Bindings/ata/ |
H A D | snps,dwc-ahci-common.yaml | 31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx) 103 description: Maximal size of Rx DMA transactions in FIFO words
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/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/ |
H A D | keystone-k2g-netcp.dtsi | 83 <0x4012000 0x400>, /* 32 Rx channels */ 85 <0x4013000 0x400>; /* 32 Rx flows */
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