1 /******************************************************************************* 2 Copyright (C) 2015 Annapurna Labs Ltd. 3 4 This file may be licensed under the terms of the Annapurna Labs Commercial 5 License Agreement. 6 7 Alternatively, this file can be distributed under the terms of the GNU General 8 Public License V2 as published by the Free Software Foundation and can be 9 found at http://www.gnu.org/licenses/gpl-2.0.html 10 11 Alternatively, redistribution and use in source and binary forms, with or 12 without modification, are permitted provided that the following conditions are 13 met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in 20 the documentation and/or other materials provided with the 21 distribution. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 34 *******************************************************************************/ 35 #ifndef _AL_SERDES_25G_INTERNAL_REGS_H_ 36 #define _AL_SERDES_25G_INTERNAL_REGS_H_ 37 38 #ifdef _cplusplus 39 extern "C" { 40 #endif 41 42 /******************************************************************************* 43 * TOP Registers 44 ******************************************************************************/ 45 #define SERDES_25G_TOP_BASE 0x00 46 #define SERDES_25G_TOP_SIZE 0x200 47 48 #define SERDES_25G_TOP_PHY_STAT0_ADDR 0x00 49 #define SERDES_25G_TOP_PHY_CTRL0_ADDR 0x08 50 #define SERDES_25G_TOP_PHY_CFG0_ADDR 0x09 51 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ADDR 0x30 52 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ADDR 0x31 53 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_ADDR 0x32 54 #define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_ADDR 0x33 55 #define SERDES_25G_TOP_AFE_ATEST_CTRL0_ADDR 0x38 56 #define SERDES_25G_TOP_AFE_ATEST_CTRL1_ADDR 0x39 57 #define SERDES_25G_TOP_RESET_CTRL_CM0_ADDR 0x50 58 #define SERDES_25G_TOP_RESET_CTRL_LN0_ADDR 0x54 59 #define SERDES_25G_TOP_RESET_CTRL_LN1_ADDR 0x55 60 #define SERDES_25G_TOP_RESET_CTRL_LN2_ADDR 0x56 61 #define SERDES_25G_TOP_RESET_CTRL_LN3_ADDR 0x57 62 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_ADDR 0x100 63 #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_ADDR 0x101 64 #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_ADDR 0x102 65 #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_ADDR 0x103 66 #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_ADDR 0x104 67 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_ADDR 0x105 68 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_ADDR 0x106 69 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_ADDR 0x107 70 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_ADDR 0x108 71 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_ADDR 0x109 72 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_ADDR 0x10A 73 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_ADDR 0x110 74 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_ADDR 0x111 75 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR 0x112 76 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_ADDR 0x113 77 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_ADDR 0x118 78 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_ADDR 0x119 79 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR 0x11A 80 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RXDIV_CORE_ADDR 0x11B 81 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_ADDR 0x120 82 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_ADDR 0x121 83 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_ADDR 0x122 84 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RXDIV_CORE_ADDR 0x123 85 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_ADDR 0x128 86 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_ADDR 0x129 87 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_ADDR 0x12A 88 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RXDIV_CORE_ADDR 0x12B 89 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_ADDR 0x130 90 #define SERDES_25G_TOP_INT0_STATUS_ADDR 0x131 91 #define SERDES_25G_TOP_REGBUS_TIMER_ADDR 0x170 92 #define SERDES_25G_TOP_ERR_CTRL0_ADDR 0x180 93 #define SERDES_25G_TOP_ERR_CTRL1_ADDR 0x181 94 #define SERDES_25G_TOP_ERR_CTRL2_ADDR 0x182 95 #define SERDES_25G_TOP_ERR_STATUS0_ADDR 0x185 96 #define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_ADDR 0x187 97 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ADDR 0x188 98 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_ADDR 0x189 99 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_ADDR 0x18A 100 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_ADDR 0x18B 101 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_ADDR 0x18C 102 #define SERDES_25G_TOP_TBUS_ADDR_7_0_ADDR 0x1A0 103 #define SERDES_25G_TOP_TBUS_ADDR_15_8_ADDR 0x1A1 104 #define SERDES_25G_TOP_TBUS_CTRL0_ADDR 0x1A2 105 #define SERDES_25G_TOP_TBUS_CTRL1_ADDR 0x1A3 106 #define SERDES_25G_TOP_TBUS_DATA_7_0_ADDR 0x1B0 107 #define SERDES_25G_TOP_TBUS_DATA_11_8_ADDR 0x1B1 108 #define SERDES_25G_TOP_SIM_CTRL_ADDR 0x1C0 109 110 /******************************************************************************* 111 * masks and shifts 112 ******************************************************************************/ 113 #define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_MASK 0x0F 114 #define SERDES_25G_TOP_PHY_STAT0_PHY_CTRL_CFG_SHIFT 0 115 116 #define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_MASK 0x0F 117 #define SERDES_25G_TOP_PHY_CTRL0_PHY_CTRL_CFG_OVR_VAL_SHIFT 0 118 119 #define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_MASK 0x80 120 #define SERDES_25G_TOP_PHY_CTRL0_OVR_EN_SHIFT 7 121 122 #define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_MASK 0xFF 123 #define SERDES_25G_TOP_PHY_CFG0_CPU_CLK_FREQ_SHIFT 0 124 125 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_MASK 0x0F 126 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL0_ACAL_EN_SHIFT 0 127 128 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_MASK 0x1F 129 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL1_ACAL_SEL_SHIFT 0 130 131 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_MASK 0x01 132 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_EN_SHIFT 0 133 134 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_MASK 0x02 135 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_MUTE_SHIFT 1 136 137 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_MASK 0x04 138 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SEL_SHIFT 2 139 140 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_MASK 0xF0 141 #define SERDES_25G_TOP_AFE_CALCOMP_CTRL2_CALCOMP_SPARE_SHIFT 4 142 143 #define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_MASK 0x01 144 #define SERDES_25G_TOP_AFE_CALCOMP_STATUS0_CALCOMP_OUT_SHIFT 0 145 146 #define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_MASK 0x0F 147 #define SERDES_25G_TOP_AFE_ATEST_CTRL0_ATEST_EN_SHIFT 0 148 149 #define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_MASK 0x3F 150 #define SERDES_25G_TOP_AFE_ATEST_CTRL1_ATEST_SEL_SHIFT 0 151 152 #define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_MASK 0x01 153 #define SERDES_25G_TOP_RESET_CTRL_CM0_CORE_SW_RESET_SHIFT 0 154 155 #define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_MASK 0x02 156 #define SERDES_25G_TOP_RESET_CTRL_CM0_REG_SW_RESET_SHIFT 1 157 158 #define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_MASK 0x04 159 #define SERDES_25G_TOP_RESET_CTRL_CM0_SUBCORE_SW_RESET_SHIFT 2 160 161 #define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_MASK 0x40 162 #define SERDES_25G_TOP_RESET_CTRL_CM0_CAL_SW_RESET_SHIFT 6 163 164 #define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_MASK 0x01 165 #define SERDES_25G_TOP_RESET_CTRL_LN0_CORE_SW_RESET_SHIFT 0 166 167 #define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_MASK 0x02 168 #define SERDES_25G_TOP_RESET_CTRL_LN0_REG_SW_RESET_SHIFT 1 169 170 #define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_MASK 0x04 171 #define SERDES_25G_TOP_RESET_CTRL_LN0_SUBCORE_SW_RESET_SHIFT 2 172 173 #define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_MASK 0x08 174 #define SERDES_25G_TOP_RESET_CTRL_LN0_TXDP_SW_RESET_SHIFT 3 175 176 #define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_MASK 0x10 177 #define SERDES_25G_TOP_RESET_CTRL_LN0_RXDP_SW_RESET_SHIFT 4 178 179 #define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_MASK 0x20 180 #define SERDES_25G_TOP_RESET_CTRL_LN0_LOS_SW_RESET_SHIFT 5 181 182 #define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_MASK 0x40 183 #define SERDES_25G_TOP_RESET_CTRL_LN0_CAL_SW_RESET_SHIFT 6 184 185 #define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_MASK 0x01 186 #define SERDES_25G_TOP_RESET_CTRL_LN1_CORE_SW_RESET_SHIFT 0 187 188 #define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_MASK 0x02 189 #define SERDES_25G_TOP_RESET_CTRL_LN1_REG_SW_RESET_SHIFT 1 190 191 #define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_MASK 0x04 192 #define SERDES_25G_TOP_RESET_CTRL_LN1_SUBCORE_SW_RESET_SHIFT 2 193 194 #define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_MASK 0x08 195 #define SERDES_25G_TOP_RESET_CTRL_LN1_TXDP_SW_RESET_SHIFT 3 196 197 #define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_MASK 0x10 198 #define SERDES_25G_TOP_RESET_CTRL_LN1_RXDP_SW_RESET_SHIFT 4 199 200 #define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_MASK 0x20 201 #define SERDES_25G_TOP_RESET_CTRL_LN1_LOS_SW_RESET_SHIFT 5 202 203 #define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_MASK 0x40 204 #define SERDES_25G_TOP_RESET_CTRL_LN1_CAL_SW_RESET_SHIFT 6 205 206 #define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_MASK 0x01 207 #define SERDES_25G_TOP_RESET_CTRL_LN2_CORE_SW_RESET_SHIFT 0 208 209 #define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_MASK 0x02 210 #define SERDES_25G_TOP_RESET_CTRL_LN2_REG_SW_RESET_SHIFT 1 211 212 #define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_MASK 0x04 213 #define SERDES_25G_TOP_RESET_CTRL_LN2_SUBCORE_SW_RESET_SHIFT 2 214 215 #define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_MASK 0x08 216 #define SERDES_25G_TOP_RESET_CTRL_LN2_TXDP_SW_RESET_SHIFT 3 217 218 #define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_MASK 0x10 219 #define SERDES_25G_TOP_RESET_CTRL_LN2_RXDP_SW_RESET_SHIFT 4 220 221 #define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_MASK 0x20 222 #define SERDES_25G_TOP_RESET_CTRL_LN2_LOS_SW_RESET_SHIFT 5 223 224 #define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_MASK 0x40 225 #define SERDES_25G_TOP_RESET_CTRL_LN2_CAL_SW_RESET_SHIFT 6 226 227 #define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_MASK 0x01 228 #define SERDES_25G_TOP_RESET_CTRL_LN3_CORE_SW_RESET_SHIFT 0 229 230 #define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_MASK 0x02 231 #define SERDES_25G_TOP_RESET_CTRL_LN3_REG_SW_RESET_SHIFT 1 232 233 #define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_MASK 0x04 234 #define SERDES_25G_TOP_RESET_CTRL_LN3_SUBCORE_SW_RESET_SHIFT 2 235 236 #define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_MASK 0x08 237 #define SERDES_25G_TOP_RESET_CTRL_LN3_TXDP_SW_RESET_SHIFT 3 238 239 #define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_MASK 0x10 240 #define SERDES_25G_TOP_RESET_CTRL_LN3_RXDP_SW_RESET_SHIFT 4 241 242 #define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_MASK 0x20 243 #define SERDES_25G_TOP_RESET_CTRL_LN3_LOS_SW_RESET_SHIFT 5 244 245 #define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_MASK 0x40 246 #define SERDES_25G_TOP_RESET_CTRL_LN3_CAL_SW_RESET_SHIFT 6 247 248 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_MASK 0x01 249 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_SRC_SEL_SHIFT 0 250 251 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_MASK 0x02 252 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_DEFAULT_CLK_EN_SHIFT 1 253 254 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_MASK 0x04 255 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_STAT_REF_CLK_EN_SHIFT 2 256 257 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK 0x80 258 #define SERDES_25G_TOP_CLOCK_AFE_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT 7 259 260 #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_MASK 0x01 261 #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_DIV_SEL_SHIFT 0 262 263 #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_MASK 0x80 264 #define SERDES_25G_TOP_CLOCK_CM0_CLK_REF_CTRL_TBUS_OUT_CG_EN_SHIFT 7 265 266 #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_MASK 0x01 267 #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_CG_EN_SHIFT 0 268 269 #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_MASK 0x80 270 #define SERDES_25G_TOP_CLOCK_CM0_REFCLK_CTRL_TBUS_OUT_CG_EN_SHIFT 7 271 272 #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_MASK 0x07 273 #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_DIV_SEL_SHIFT 0 274 275 #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_MASK 0x80 276 #define SERDES_25G_TOP_CLOCK_CM0_CLK_SSC_GEN_CTRL_TBUS_OUT_CG_EN_SHIFT 7 277 278 #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_MASK 0x07 279 #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_DIV_SEL_SHIFT 0 280 281 #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_MASK 0x80 282 #define SERDES_25G_TOP_CLOCK_CM0_CLK_GCFSM_CTRL_TBUS_OUT_CG_EN_SHIFT 7 283 284 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_MASK 0x01 285 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_DIV_SEL_SHIFT 0 286 287 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_MASK 0x02 288 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_CG_EN_SHIFT 1 289 290 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_MASK 0x80 291 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMPLL_VCO_CTRL_TBUS_OUT_CG_EN_SHIFT 7 292 293 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_MASK 0x01 294 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_SRC_SEL_SHIFT 0 295 296 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_MASK 0x02 297 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_DEFAULT_CLK_EN_SHIFT 1 298 299 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_MASK 0x04 300 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_STAT_CMU_CLK_EN_SHIFT 2 301 302 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_MASK 0xF8 303 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL_DIV_SEL_SHIFT 3 304 305 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_MASK 0x80 306 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_SHIFT 7 307 308 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_MASK 0x01 309 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_SRC_SEL_SHIFT 0 310 311 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_MASK 0x02 312 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_DEFAULT_CLK_EN_SHIFT 1 313 314 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_MASK 0x04 315 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_STAT_CMUDIV_CLK_EN_SHIFT 2 316 317 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_MASK 0xF8 318 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL_DIV_SEL_SHIFT 3 319 320 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_MASK 0x80 321 #define SERDES_25G_TOP_CLOCK_CM0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_SHIFT 7 322 323 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_MASK 0x01 324 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_FRCDIV_MODE_EN_SHIFT 0 325 326 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_MASK 0x06 327 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_SRC_SEL_SHIFT 1 328 329 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_MASK 0x08 330 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_DIV_SEL_SHIFT 3 331 332 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_MASK 0x80 333 #define SERDES_25G_TOP_CLOCK_CM0_CLK_FRACN_FBK_CTRL_TBUS_OUT_CG_EN_SHIFT 7 334 335 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_MASK 0x03 336 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_SHIFT 0 337 338 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_MASK 0x04 339 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_DIV_SEL_SHIFT 2 340 341 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 342 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 343 344 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 345 #define SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 346 347 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_MASK 0x01 348 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT 0 349 350 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 351 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 352 353 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 354 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 355 356 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 357 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 358 359 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_MASK 0x03 360 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_SRC_SEL_SHIFT 0 361 362 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_MASK 0x10 363 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT 4 364 365 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 366 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 367 368 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 369 #define SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 370 371 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_MASK 0x01 372 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_SRC_SEL_SHIFT 0 373 374 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_MASK 0x02 375 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_DEFAULT_CLK_EN_SHIFT 1 376 377 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_MASK 0x04 378 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_STAT_RX_CLKDIV_EN_SHIFT 2 379 380 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_MASK 0x80 381 #define SERDES_25G_TOP_CLOCK_AFE_LN0_CLK_RXDIV_CORE_CTRL_TBUS_OUT_CG_EN_SHIFT 7 382 383 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_MASK 0x03 384 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_SHIFT 0 385 386 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_MASK 0x04 387 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_DIV_SEL_SHIFT 2 388 389 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 390 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 391 392 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 393 #define SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 394 395 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_MASK 0x01 396 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT 0 397 398 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 399 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 400 401 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 402 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 403 404 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 405 #define SERDES_25G_TOP_CLOCK_AFE_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 406 407 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_MASK 0x03 408 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_SRC_SEL_SHIFT 0 409 410 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_MASK 0x10 411 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT 4 412 413 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 414 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 415 416 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 417 #define SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 418 419 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_MASK 0x03 420 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_SHIFT 0 421 422 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_MASK 0x04 423 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_DIV_SEL_SHIFT 2 424 425 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 426 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 427 428 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 429 #define SERDES_25G_TOP_CLOCK_LN2_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 430 431 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_MASK 0x01 432 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT 0 433 434 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 435 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 436 437 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 438 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 439 440 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 441 #define SERDES_25G_TOP_CLOCK_AFE_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 442 443 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_MASK 0x03 444 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_SRC_SEL_SHIFT 0 445 446 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_MASK 0x10 447 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_SHIFT 4 448 449 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 450 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 451 452 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 453 #define SERDES_25G_TOP_CLOCK_LN2_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 454 455 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_MASK 0x03 456 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_SHIFT 0 457 458 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_MASK 0x04 459 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_DIV_SEL_SHIFT 2 460 461 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_MASK 0x10 462 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_SHIFT 4 463 464 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 465 #define SERDES_25G_TOP_CLOCK_LN3_CLK_TX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 466 467 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_MASK 0x01 468 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT 0 469 470 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_MASK 0x02 471 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_DEFAULT_CLK_EN_SHIFT 1 472 473 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_MASK 0x04 474 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_STAT_RX_CLK_EN_SHIFT 2 475 476 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 477 #define SERDES_25G_TOP_CLOCK_AFE_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 478 479 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_MASK 0x03 480 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_SRC_SEL_SHIFT 0 481 482 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_MASK 0x10 483 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_SHIFT 4 484 485 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_MASK 0x20 486 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_SHIFT 5 487 488 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_MASK 0x80 489 #define SERDES_25G_TOP_CLOCK_LN3_CLK_RX_CTRL_TBUS_OUT_CG_EN_SHIFT 7 490 491 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_MASK 0x01 492 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN0_SHIFT 0 493 494 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_MASK 0x02 495 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN1_SHIFT 1 496 497 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_MASK 0x04 498 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN2_SHIFT 2 499 500 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_MASK 0x08 501 #define SERDES_25G_TOP_LOS_INT_EN_CTRL_LN3_SHIFT 3 502 503 #define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_MASK 0xFF 504 #define SERDES_25G_TOP_REGBUS_TIMER_LOAD_VAL_SHIFT 0 505 506 #define SERDES_25G_TOP_ERR_CTRL0_ERR_MASK 0x01 507 #define SERDES_25G_TOP_ERR_CTRL0_ERR_SHIFT 0 508 509 #define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 510 #define SERDES_25G_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 511 512 #define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 513 #define SERDES_25G_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 514 515 #define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_MASK 0x01 516 #define SERDES_25G_TOP_ERR_STATUS0_REGBUS_ERR_SHIFT 0 517 518 #define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_MASK 0x01 519 #define SERDES_25G_TOP_REGBUS_ERR_INFO_CTRL_CLR_SHIFT 0 520 521 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_MASK 0x03 522 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_SHIFT 0 523 524 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_MASK 0x04 525 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_SHIFT 2 526 527 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_MASK 0xFF 528 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS1_TRANSFER_ADDR_LSB_SHIFT 0 529 530 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_MASK 0x7F 531 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_SHIFT 0 532 533 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_MASK 0xFF 534 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS3_TRANSFER_WD_SHIFT 0 535 536 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_MASK 0xFF 537 #define SERDES_25G_TOP_REGBUS_ERR_INFO_STATUS4_TRANSFER_WR_BIT_EN_SHIFT 0 538 539 #define SERDES_25G_TOP_TBUS_ADDR_7_0_MASK 0xFF 540 #define SERDES_25G_TOP_TBUS_ADDR_7_0_SHIFT 0 541 542 #define SERDES_25G_TOP_TBUS_ADDR_15_8_MASK 0xFF 543 #define SERDES_25G_TOP_TBUS_ADDR_15_8_SHIFT 0 544 545 #define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_MASK 0xFF 546 #define SERDES_25G_TOP_TBUS_CTRL0_CLOCK_GATE0_SHIFT 0 547 548 #define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_MASK 0xFF 549 #define SERDES_25G_TOP_TBUS_CTRL1_CLOCK_GATE1_SHIFT 0 550 551 #define SERDES_25G_TOP_TBUS_DATA_7_0_MASK 0xFF 552 #define SERDES_25G_TOP_TBUS_DATA_7_0_SHIFT 0 553 554 #define SERDES_25G_TOP_TBUS_DATA_11_8_MASK 0x0F 555 #define SERDES_25G_TOP_TBUS_DATA_11_8_SHIFT 0 556 557 /*********************************** Mailbox **********************************/ 558 #define SERDES_25G_TOP_MB_BASE 0x200 559 560 #define SERDES_25G_TOP_CMD_ADDR (SERDES_25G_TOP_MB_BASE + 0x00) 561 #define SERDES_25G_TOP_CMD_FLAG_ADDR (SERDES_25G_TOP_MB_BASE + 0x02) 562 #define SERDES_25G_TOP_CMD_DATA0_ADDR (SERDES_25G_TOP_MB_BASE + 0x03) 563 #define SERDES_25G_TOP_CMD_DATA1_ADDR (SERDES_25G_TOP_MB_BASE + 0x04) 564 #define SERDES_25G_TOP_CMD_DATA2_ADDR (SERDES_25G_TOP_MB_BASE + 0x05) 565 #define SERDES_25G_TOP_CMD_DATA3_ADDR (SERDES_25G_TOP_MB_BASE + 0x06) 566 #define SERDES_25G_TOP_CMD_DATA4_ADDR (SERDES_25G_TOP_MB_BASE + 0x07) 567 #define SERDES_25G_TOP_CMD_DATA5_ADDR (SERDES_25G_TOP_MB_BASE + 0x08) 568 #define SERDES_25G_TOP_CMD_DATA6_ADDR (SERDES_25G_TOP_MB_BASE + 0x09) 569 #define SERDES_25G_TOP_CMD_DATA7_ADDR (SERDES_25G_TOP_MB_BASE + 0x0A) 570 #define SERDES_25G_TOP_RSP_ADDR (SERDES_25G_TOP_MB_BASE + 0x10) 571 #define SERDES_25G_TOP_RSP_FLAG_ADDR (SERDES_25G_TOP_MB_BASE + 0x12) 572 #define SERDES_25G_TOP_RSP_DATA0_ADDR (SERDES_25G_TOP_MB_BASE + 0x13) 573 #define SERDES_25G_TOP_RSP_DATA1_ADDR (SERDES_25G_TOP_MB_BASE + 0x14) 574 #define SERDES_25G_TOP_RSP_DATA2_ADDR (SERDES_25G_TOP_MB_BASE + 0x15) 575 #define SERDES_25G_TOP_RSP_DATA3_ADDR (SERDES_25G_TOP_MB_BASE + 0x16) 576 #define SERDES_25G_TOP_RSP_DATA4_ADDR (SERDES_25G_TOP_MB_BASE + 0x17) 577 #define SERDES_25G_TOP_RSP_DATA5_ADDR (SERDES_25G_TOP_MB_BASE + 0x18) 578 #define SERDES_25G_TOP_RSP_DATA6_ADDR (SERDES_25G_TOP_MB_BASE + 0x19) 579 #define SERDES_25G_TOP_RSP_DATA7_ADDR (SERDES_25G_TOP_MB_BASE + 0x1A) 580 #define SERDES_25G_TOP_RSP_DATA8_ADDR (SERDES_25G_TOP_MB_BASE + 0x1B) 581 #define SERDES_25G_TOP_RSP_DATA9_ADDR (SERDES_25G_TOP_MB_BASE + 0x1C) 582 #define SERDES_25G_TOP_RSP_DATA10_ADDR (SERDES_25G_TOP_MB_BASE + 0x1D) 583 #define SERDES_25G_TOP_RSP_DATA11_ADDR (SERDES_25G_TOP_MB_BASE + 0x1E) 584 #define SERDES_25G_TOP_RSP_DATA12_ADDR (SERDES_25G_TOP_MB_BASE + 0x1F) 585 #define SERDES_25G_TOP_RSP_DATA13_ADDR (SERDES_25G_TOP_MB_BASE + 0x20) 586 #define SERDES_25G_TOP_RSP_DATA14_ADDR (SERDES_25G_TOP_MB_BASE + 0x21) 587 #define SERDES_25G_TOP_RSP_DATA15_ADDR (SERDES_25G_TOP_MB_BASE + 0x22) 588 /******************************************************************************* 589 * masks and shifts 590 ******************************************************************************/ 591 #define SERDES_25G_TOP_CMD_MASK 0xFF 592 #define SERDES_25G_TOP_CMD_SHIFT 0 593 594 #define SERDES_25G_TOP_CMD_FLAG_MASK 0x01 595 #define SERDES_25G_TOP_CMD_FLAG_SHIFT 0 596 597 #define SERDES_25G_TOP_CMD_DATA0_MASK 0xFF 598 #define SERDES_25G_TOP_CMD_DATA0_SHIFT 0 599 600 #define SERDES_25G_TOP_CMD_DATA1_MASK 0xFF 601 #define SERDES_25G_TOP_CMD_DATA1_SHIFT 0 602 603 #define SERDES_25G_TOP_CMD_DATA2_MASK 0xFF 604 #define SERDES_25G_TOP_CMD_DATA2_SHIFT 0 605 606 #define SERDES_25G_TOP_CMD_DATA3_MASK 0xFF 607 #define SERDES_25G_TOP_CMD_DATA3_SHIFT 0 608 609 #define SERDES_25G_TOP_CMD_DATA4_MASK 0xFF 610 #define SERDES_25G_TOP_CMD_DATA4_SHIFT 0 611 612 #define SERDES_25G_TOP_CMD_DATA5_MASK 0xFF 613 #define SERDES_25G_TOP_CMD_DATA5_SHIFT 0 614 615 #define SERDES_25G_TOP_CMD_DATA6_MASK 0xFF 616 #define SERDES_25G_TOP_CMD_DATA6_SHIFT 0 617 618 #define SERDES_25G_TOP_CMD_DATA7_MASK 0xFF 619 #define SERDES_25G_TOP_CMD_DATA7_SHIFT 0 620 621 #define SERDES_25G_TOP_RSP_MASK 0xFF 622 #define SERDES_25G_TOP_RSP_SHIFT 0 623 624 #define SERDES_25G_TOP_RSP_FLAG_MASK 0x01 625 #define SERDES_25G_TOP_RSP_FLAG_SHIFT 0 626 627 #define SERDES_25G_TOP_RSP_DATA0_MASK 0xFF 628 #define SERDES_25G_TOP_RSP_DATA0_SHIFT 0 629 630 #define SERDES_25G_TOP_RSP_DATA1_MASK 0xFF 631 #define SERDES_25G_TOP_RSP_DATA1_SHIFT 0 632 633 #define SERDES_25G_TOP_RSP_DATA2_MASK 0xFF 634 #define SERDES_25G_TOP_RSP_DATA2_SHIFT 0 635 636 #define SERDES_25G_TOP_RSP_DATA3_MASK 0xFF 637 #define SERDES_25G_TOP_RSP_DATA3_SHIFT 0 638 639 #define SERDES_25G_TOP_RSP_DATA4_MASK 0xFF 640 #define SERDES_25G_TOP_RSP_DATA4_SHIFT 0 641 642 #define SERDES_25G_TOP_RSP_DATA5_MASK 0xFF 643 #define SERDES_25G_TOP_RSP_DATA5_SHIFT 0 644 645 #define SERDES_25G_TOP_RSP_DATA6_MASK 0xFF 646 #define SERDES_25G_TOP_RSP_DATA6_SHIFT 0 647 648 #define SERDES_25G_TOP_RSP_DATA7_MASK 0xFF 649 #define SERDES_25G_TOP_RSP_DATA7_SHIFT 0 650 651 #define SERDES_25G_TOP_RSP_DATA8_MASK 0xFF 652 #define SERDES_25G_TOP_RSP_DATA8_SHIFT 0 653 654 #define SERDES_25G_TOP_RSP_DATA9_MASK 0xFF 655 #define SERDES_25G_TOP_RSP_DATA9_SHIFT 0 656 657 #define SERDES_25G_TOP_RSP_DATA10_MASK 0xFF 658 #define SERDES_25G_TOP_RSP_DATA10_SHIFT 0 659 660 #define SERDES_25G_TOP_RSP_DATA11_MASK 0xFF 661 #define SERDES_25G_TOP_RSP_DATA11_SHIFT 0 662 663 #define SERDES_25G_TOP_RSP_DATA12_MASK 0xFF 664 #define SERDES_25G_TOP_RSP_DATA12_SHIFT 0 665 666 #define SERDES_25G_TOP_RSP_DATA13_MASK 0xFF 667 #define SERDES_25G_TOP_RSP_DATA13_SHIFT 0 668 669 #define SERDES_25G_TOP_RSP_DATA14_MASK 0xFF 670 #define SERDES_25G_TOP_RSP_DATA14_SHIFT 0 671 672 #define SERDES_25G_TOP_RSP_DATA15_MASK 0xFF 673 #define SERDES_25G_TOP_RSP_DATA15_SHIFT 0 674 675 /******************************************************************************* 676 * Common Registers 677 ******************************************************************************/ 678 #define SERDES_25G_CM_BASE 0xC00 679 #define SERDES_25G_CM_SIZE 0x400 680 681 #define SERDES_25G_CM_TOP_AFE_PD_CTRL0_ADDR 0x00 682 #define SERDES_25G_CM_TOP_AFE_PD_CTRL1_ADDR 0x01 683 #define SERDES_25G_CM_TOP_AFE_RST_CTRL0_ADDR 0x03 684 #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL0_ADDR 0x05 685 #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL1_ADDR 0x06 686 #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL2_ADDR 0x07 687 #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL3_ADDR 0x08 688 #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL4_ADDR 0x09 689 #define SERDES_25G_CM_TOP_AFE_BIAS_CTRL5_ADDR 0x0A 690 #define SERDES_25G_CM_TOP_AFE_REG_CTRL0_ADDR 0x0C 691 #define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL0_ADDR 0x1A 692 #define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL1_ADDR 0x1B 693 #define SERDES_25G_CM_TOP_AFE_REFCLK_CTRL2_ADDR 0x1F 694 #define SERDES_25G_CM_TOP_AFE_CMCP_CTRL0_ADDR 0x20 695 #define SERDES_25G_CM_TOP_AFE_CMCP_CTRL1_ADDR 0x21 696 #define SERDES_25G_CM_TOP_AFE_CMCP_CTRL2_ADDR 0x22 697 #define SERDES_25G_CM_TOP_AFE_MISC_CTRL0_ADDR 0x23 698 #define SERDES_25G_CM_TOP_AFE_CMCP_STATUS_ADDR 0x24 699 #define SERDES_25G_CM_TOP_AFE_TOGGLE_CTRL0_ADDR 0x25 700 #define SERDES_25G_CM_TOP_AFE_TSTCLK_CTRL0_ADDR 0x28 701 #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL0_ADDR 0x30 702 #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL1_ADDR 0x31 703 #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL2_ADDR 0x32 704 #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL3_ADDR 0x33 705 #define SERDES_25G_CM_TOP_AFE_TXTC_CTRL4_ADDR 0x34 706 #define SERDES_25G_CM_TOP_PWR_STATE_REQ_STATUS_ADDR 0x50 707 #define SERDES_25G_CM_TOP_PWR_STATE_ACK_CTRL_ADDR 0x51 708 #define SERDES_25G_CM_TOP_PHY_IF_STATUS_ADDR 0x52 709 #define SERDES_25G_CM_TOP_CMU_TOP_SPARE0_ADDR 0x58 710 #define SERDES_25G_CM_TOP_CMU_TOP_SPARE1_ADDR 0x59 711 #define SERDES_25G_CM_TOP_ERR_CTRL1_ADDR 0x80 712 #define SERDES_25G_CM_TOP_ERR_CTRL2_ADDR 0x81 713 #define SERDES_25G_CM_TOP_ERR_CTRL3_ADDR 0x82 714 #define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL0_ADDR 0x8A 715 #define SERDES_25G_CM_TOP_CMU_IF_OVR_CTRL1_ADDR 0x8B 716 /******************************************************************************* 717 * masks and shifts 718 ******************************************************************************/ 719 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_MASK 0x01 720 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SHIFT 0 721 722 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_MASK 0x02 723 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICV_SHIFT 1 724 725 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_MASK 0x04 726 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_ICC_SHIFT 2 727 728 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_MASK 0x08 729 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_IPTAT_SHIFT 3 730 731 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_MASK 0x10 732 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_BIAS_SLAVE_SHIFT 4 733 734 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_MASK 0x20 735 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REG_REF_SHIFT 5 736 737 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_MASK 0x40 738 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL0_PD_REFCLK_SHIFT 6 739 740 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_MASK 0x01 741 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_SHIFT 0 742 743 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_MASK 0x02 744 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_LEFT_SHIFT 1 745 746 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_MASK 0x04 747 #define SERDES_25G_CMU_TOP_AFE_PD_CTRL1_PD_CMCP_TXCLK_RIGHT_SHIFT 2 748 749 #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_MASK 0x01 750 #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMU_N_SHIFT 0 751 752 #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_MASK 0x02 753 #define SERDES_25G_CMU_TOP_AFE_RST_CTRL0_RST_CMCP_CLK_CMUDIV_N_SHIFT 1 754 755 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_MASK 0x0F 756 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICV_TRIM_SHIFT 0 757 758 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_MASK 0xF0 759 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL0_BIAS_ICC_TRIM_SHIFT 4 760 761 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_MASK 0x0F 762 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL1_BIAS_IPTAT_TRIM_SHIFT 0 763 764 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_MASK 0x01 765 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_BGSTART_BYP_SHIFT 0 766 767 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_MASK 0x02 768 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_BIAS_IPTATSTART_BYP_SHIFT 1 769 770 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_MASK 0x04 771 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL2_TERMCAL_EN_SHIFT 2 772 773 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_MASK 0x0F 774 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_PTRIM_SHIFT 0 775 776 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_MASK 0xF0 777 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL3_TERMCAL_NTRIM_SHIFT 4 778 779 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_MASK 0x0F 780 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL4_BIAS_SPARE_SHIFT 0 781 782 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_MASK 0x0F 783 #define SERDES_25G_CMU_TOP_AFE_BIAS_CTRL5_BIAS_CALREF_TRIM_SHIFT 0 784 785 #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_MASK 0x01 786 #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_PASS_EN_SHIFT 0 787 788 #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_MASK 0x0E 789 #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRIM_SHIFT 1 790 791 #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_MASK 0x30 792 #define SERDES_25G_CMU_TOP_AFE_REG_CTRL0_REG_REF_TRICKLE_SHIFT 4 793 794 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_MASK 0x03 795 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DIV_SHIFT 0 796 797 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_MASK 0x0C 798 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DPL_DIV_SHIFT 2 799 800 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_MASK 0x10 801 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL0_REFCLK_DEGLITCH_OVR_SHIFT 4 802 803 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_MASK 0x1F 804 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL1_REFCLK_TERM_SHIFT 0 805 806 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_MASK 0x0F 807 #define SERDES_25G_CMU_TOP_AFE_REFCLK_CTRL2_REFCLK_SPARE_SHIFT 0 808 809 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_MASK 0x01 810 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_QSAMPLE_EN_SHIFT 0 811 812 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_MASK 0x02 813 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_DCD_RANGE_SHIFT 1 814 815 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_MASK 0x1C 816 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUCLK_DIV_SHIFT 2 817 818 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_MASK 0xE0 819 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_SHIFT 5 820 821 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_MASK 0x03 822 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CLKDIV_SWING_SHIFT 0 823 824 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_MASK 0x0C 825 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_TXCLK_SWING_SHIFT 2 826 827 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_MASK 0x10 828 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL1_CMCP_CMUCLK_DIV2_BYPASS_SHIFT 4 829 830 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_MASK 0x03 831 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_CLKDIV_OVR_SHIFT 0 832 833 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_MASK 0x0C 834 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_BIASI_SHIFT 2 835 836 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_MASK 0x70 837 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_TXCLK_DIV_SHIFT 4 838 839 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_MASK 0x80 840 #define SERDES_25G_CMU_TOP_AFE_CMCP_CTRL2_CMCP_DIV1P5_DUMMY_EN_SHIFT 7 841 842 #define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_MASK 0xFF 843 #define SERDES_25G_CMU_TOP_AFE_MISC_CTRL0_CMCP_SPARE_SHIFT 0 844 845 #define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_MASK 0x0F 846 #define SERDES_25G_CMU_TOP_AFE_CMCP_STATUS_CMCP_DIV1P5_QSAMPLE_SHIFT 0 847 848 #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_MASK 0x01 849 #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CLK_TOGGLE_EN_SHIFT 0 850 851 #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_MASK 0x02 852 #define SERDES_25G_CMU_TOP_AFE_TOGGLE_CTRL0_CMCP_TOGGLE_EN_SHIFT 1 853 854 #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_MASK 0x03 855 #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_SHIFT 0 856 857 #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_MASK 0x1C 858 #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_SHIFT 2 859 860 #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_MASK 0x60 861 #define SERDES_25G_CMU_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_SWING_SHIFT 5 862 863 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_MASK 0x07 864 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_SHIFT 0 865 866 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_MASK 0x18 867 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_SHIFT 3 868 869 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_MASK 0x1F 870 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_SHIFT 0 871 872 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_MASK 0x60 873 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_SHIFT 5 874 875 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_MASK 0x07 876 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_SHIFT 0 877 878 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_MASK 0x18 879 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_SHIFT 3 880 881 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_MASK 0x1F 882 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_SHIFT 0 883 884 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_MASK 0x60 885 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_SHIFT 5 886 887 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_MASK 0x07 888 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_NEG_SHIFT 0 889 890 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_MASK 0x70 891 #define SERDES_25G_CMU_TOP_AFE_TXTC_CTRL4_TXTC_TERM_POS_SHIFT 4 892 893 #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07 894 #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0 895 896 #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08 897 #define SERDES_25G_CMU_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3 898 899 #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07 900 #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0 901 902 #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08 903 #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3 904 905 #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70 906 #define SERDES_25G_CMU_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4 907 908 #define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_MASK 0x01 909 #define SERDES_25G_CMU_TOP_PHY_IF_STATUS_CMU_OK_SHIFT 0 910 911 #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_MASK 0xFF 912 #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE0_SHIFT 0 913 914 #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_MASK 0xFF 915 #define SERDES_25G_CMU_TOP_CMU_TOP_SPARE1_SHIFT 0 916 917 #define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 918 #define SERDES_25G_CMU_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 919 920 #define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 921 #define SERDES_25G_CMU_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 922 923 #define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__MASK 0x01 924 #define SERDES_25G_CMU_TOP_ERR_CTRL3_CMU_ERR__SHIFT 0 925 926 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_MASK 0x01 927 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_EN_SHIFT 0 928 929 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_MASK 0x06 930 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL0_CMU_PD_OVR_VAL_SHIFT 1 931 932 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_MASK 0x01 933 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_EN_SHIFT 0 934 935 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_MASK 0x02 936 #define SERDES_25G_CMU_TOP_CMU_IF_OVR_CTRL1_CMU_RST_N_OVR_VAL_SHIFT 1 937 938 939 /******************************************************************************* 940 * Lane Registers 941 ******************************************************************************/ 942 #define SERDES_25G_LANE_BASE 0x1800 943 #define SERDES_25G_LANE_SIZE 0x800 944 945 /********************************** LANE_TOP **********************************/ 946 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR 0x00 947 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR 0x01 948 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR 0x02 949 #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR 0x03 950 #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR 0x04 951 #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR 0x05 952 #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR 0x06 953 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR 0x10 954 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR 0x12 955 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR 0x13 956 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR 0x14 957 #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR 0x16 958 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR 0x19 959 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR 0x1B 960 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR 0x1C 961 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR 0x22 962 #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR 0x24 963 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR 0x25 964 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR 0x26 965 #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR 0x27 966 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR 0x30 967 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR 0x31 968 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR 0x38 969 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR 0x39 970 #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR 0x3A 971 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR 0x3B 972 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR 0x3C 973 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR 0x3D 974 #define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR 0x40 975 #define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR 0x41 976 /******************************************************************************* 977 * masks and shifts 978 ******************************************************************************/ 979 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK 0x01 980 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT 0 981 982 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK 0x02 983 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT 1 984 985 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK 0x04 986 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT 2 987 988 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK 0x08 989 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT 3 990 991 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK 0x01 992 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT 0 993 994 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK 0x02 995 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT 1 996 997 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK 0x01 998 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT 0 999 1000 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK 0x02 1001 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT 1 1002 1003 #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK 0x01 1004 #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT 0 1005 1006 #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK 0x01 1007 #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT 0 1008 1009 #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK 0x04 1010 #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT 2 1011 1012 #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK 0x0F 1013 #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT 0 1014 1015 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK 0x0F 1016 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT 0 1017 1018 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK 0x30 1019 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT 4 1020 1021 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK 0x40 1022 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT 6 1023 1024 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK 0x01 1025 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT 0 1026 1027 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK 0x06 1028 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT 1 1029 1030 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK 0x0F 1031 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT 0 1032 1033 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK 0x03 1034 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT 0 1035 1036 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK 0x04 1037 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT 2 1038 1039 #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK 0xF0 1040 #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT 4 1041 1042 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK 0x07 1043 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT 0 1044 1045 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK 0xF0 1046 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT 4 1047 1048 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK 0x07 1049 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT 0 1050 1051 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK 0x08 1052 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT 3 1053 1054 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK 0x10 1055 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT 4 1056 1057 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK 0x1F 1058 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT 0 1059 1060 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK 0x03 1061 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT 0 1062 1063 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK 0x04 1064 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT 2 1065 1066 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK 0x10 1067 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT 4 1068 1069 #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK 0x01 1070 #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT 0 1071 1072 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07 1073 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0 1074 1075 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08 1076 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3 1077 1078 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07 1079 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0 1080 1081 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08 1082 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3 1083 1084 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70 1085 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4 1086 1087 #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK 0x01 1088 #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT 0 1089 1090 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK 0x07 1091 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT 0 1092 1093 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK 0x38 1094 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT 3 1095 1096 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK 0x07 1097 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT 0 1098 1099 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK 0x38 1100 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT 3 1101 1102 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK 0x01 1103 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT 0 1104 1105 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK 0x01 1106 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT 0 1107 1108 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK 0x02 1109 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT 1 1110 1111 #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK 0x01 1112 #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT 0 1113 1114 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK 0x01 1115 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT 0 1116 1117 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK 0x02 1118 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT 1 1119 1120 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK 0x04 1121 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT 2 1122 1123 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK 0x08 1124 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT 3 1125 1126 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK 0x10 1127 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT 4 1128 1129 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK 0x20 1130 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT 5 1131 1132 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK 0x40 1133 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT 6 1134 1135 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK 0x01 1136 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT 0 1137 1138 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK 0x06 1139 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT 1 1140 1141 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK 0x08 1142 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT 3 1143 1144 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK 0x01 1145 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT 0 1146 1147 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK 0x02 1148 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT 1 1149 1150 #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 1151 #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 1152 1153 #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 1154 #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 1155 1156 /********************************* Lane CDR RXCLK ***************************/ 1157 #define SERDES_25G_LANE_CDR_RXCLK_BASE 0x80 1158 1159 #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x10) 1160 #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x11) 1161 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x21) 1162 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x22) 1163 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x26) 1164 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x27) 1165 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x28) 1166 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x29) 1167 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2A) 1168 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2B) 1169 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x2D) 1170 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x30) 1171 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x31) 1172 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x32) 1173 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x34) 1174 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x36) 1175 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x37) 1176 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x39) 1177 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3A) 1178 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3B) 1179 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3C) 1180 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3D) 1181 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3E) 1182 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x3F) 1183 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x40) 1184 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x41) 1185 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x44) 1186 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x45) 1187 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x46) 1188 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x48) 1189 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x49) 1190 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4A) 1191 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4B) 1192 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4C) 1193 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4D) 1194 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4E) 1195 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x4F) 1196 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x60) 1197 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x61) 1198 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x62) 1199 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x63) 1200 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x68) 1201 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x69) 1202 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6A) 1203 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6B) 1204 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6C) 1205 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6D) 1206 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_ADDR (SERDES_25G_LANE_CDR_RXCLK_BASE + 0x6E) 1207 /******************************************************************************* 1208 * masks and shifts 1209 ******************************************************************************/ 1210 #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_MASK 0x01 1211 #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL0_DLPF_SRC_SEL_SHIFT 0 1212 1213 #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_MASK 0x07 1214 #define SERDES_25G_LANE_CDR_RXCLK_CAL_CTRL1_CFG_DOSC_MIN_SHIFT 0 1215 1216 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_MASK 0x0F 1217 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DECIMATION_MODE_SHIFT 0 1218 1219 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_MASK 0x30 1220 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL0_DLPF_MODE_SHIFT 4 1221 1222 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_MASK 0x03 1223 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_CTRL1_PD_OUT_MASK_SHIFT 0 1224 1225 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_MASK 0xFF 1226 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_DLPF_VAL_7_0_SHIFT 0 1227 1228 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_MASK 0x01 1229 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_SHIFT 0 1230 1231 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_MASK 0xFF 1232 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL2_DLPF_DITHER_VAL_7_0_SHIFT 0 1233 1234 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_MASK 0x07 1235 #define SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL3_DLPF_DITHER_VAL_10_8_SHIFT 0 1236 1237 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_MASK 0xFF 1238 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL0_DLPF_VAL_7_0_SHIFT 0 1239 1240 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_MASK 0x01 1241 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL1_DLPF_VAL_8_SHIFT 0 1242 1243 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_MASK 0x01 1244 #define SERDES_25G_LANE_CDR_RXCLK_FORCE_MODE_CTRL2_EN_SHIFT 0 1245 1246 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_MASK 0x0F 1247 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL0_NUM_DITHER_BITS_SHIFT 0 1248 1249 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_MASK 0xFF 1250 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL1_HIGH_THRESHOLD_7_0_SHIFT 0 1251 1252 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_MASK 0x01 1253 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL2_HIGH_THRESHOLD_8_SHIFT 0 1254 1255 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_MASK 0x0F 1256 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL3_HIGH_COUNT_SHIFT 0 1257 1258 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_MASK 0xFF 1259 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL4_LOW_THRESHOLD_7_0_SHIFT 0 1260 1261 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_MASK 0x01 1262 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL5_LOW_THRESHOLD_8_SHIFT 0 1263 1264 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_MASK 0x0F 1265 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL6_LOW_COUNT_SHIFT 0 1266 1267 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_MASK 0x01 1268 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCK_EN_SHIFT 0 1269 1270 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_MASK 0x02 1271 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOCKL_EN_SHIFT 1 1272 1273 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_MASK 0x04 1274 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_HIGH_EN_SHIFT 2 1275 1276 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_MASK 0x08 1277 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL7_LOW_EN_SHIFT 3 1278 1279 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_MASK 0x3F 1280 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_CTRL8_OUTPUT_SAMPLE_PERIOD_SHIFT 0 1281 1282 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_MASK 0xFF 1283 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS0_GREY_VAL_7_0_SHIFT 0 1284 1285 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_MASK 0x01 1286 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS1_GREY_VAL_8_SHIFT 0 1287 1288 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_MASK 0xFF 1289 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS2_BINARY_VAL_7_0_SHIFT 0 1290 1291 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_MASK 0x01 1292 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT 0 1293 1294 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_MASK 0x01 1295 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT 0 1296 1297 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_MASK 0x02 1298 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT 1 1299 1300 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_MASK 0x04 1301 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT 2 1302 1303 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_MASK 0x01 1304 #define SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT 0 1305 1306 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_MASK 0xFF 1307 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS0_ACCUMULATOR_7_0_SHIFT 0 1308 1309 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_MASK 0xFF 1310 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS1_ACCUMULATOR_15_8_SHIFT 0 1311 1312 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_MASK 0x0F 1313 #define SERDES_25G_LANE_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT 0 1314 1315 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_MASK 0x0F 1316 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_DITHER_BITS_SHIFT 0 1317 1318 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_MASK 0xF0 1319 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL0_SAMPLE_PERIOD_SHIFT 4 1320 1321 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_MASK 0xFF 1322 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL1_NUM_SAMPLES_SHIFT 0 1323 1324 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_MASK 0xFF 1325 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL2_SLOPE_THRESHOLD_SHIFT 0 1326 1327 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_MASK 0xFF 1328 #define SERDES_25G_LANE_CDR_RXCLK_LOCKD_CTRL3_RANGE_THRESHOLD_SHIFT 0 1329 1330 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_MASK 0x0F 1331 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_DITHER_BITS_SHIFT 0 1332 1333 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_MASK 0xF0 1334 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL0_SAMPLE_PERIOD_SHIFT 4 1335 1336 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_MASK 0xFF 1337 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL1_NUM_SAMPLES_SHIFT 0 1338 1339 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_MASK 0xFF 1340 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL2_SLOPE_THRESHOLD_SHIFT 0 1341 1342 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_MASK 0xFF 1343 #define SERDES_25G_LANE_CDR_RXCLK_LOCKL_CTRL3_RANGE_THRESHOLD_SHIFT 0 1344 1345 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_MASK 0x01 1346 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL0_EN_SHIFT 0 1347 1348 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_MASK 0x07 1349 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_SAMPLE_DROP_BITS_SHIFT 0 1350 1351 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_MASK 0xF0 1352 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL1_NUM_PEAKS_SHIFT 4 1353 1354 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_MASK 0xFF 1355 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL2_PEAK2PEAK_PERIOD_MIN_SHIFT 0 1356 1357 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_MASK 0xFF 1358 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_CTRL3_PEAK2PEAK_PERIOD_MAX_SHIFT 0 1359 1360 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_MASK 0x01 1361 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_DONE_SHIFT 0 1362 1363 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_MASK 0x02 1364 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_NOISY_SHIFT 1 1365 1366 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_MASK 0x04 1367 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_PEAK_DETECT_STATUS0_SLOW_SHIFT 2 1368 1369 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_MASK 0xFF 1370 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS0_VAL_7_0_SHIFT 0 1371 1372 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_MASK 0xFF 1373 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS1_VAL_15_8_SHIFT 0 1374 1375 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_MASK 0x0F 1376 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_FIRST_PEAK_STATUS2_VAL_19_16_SHIFT 0 1377 1378 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_MASK 0xFF 1379 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS0_VAL_7_0_SHIFT 0 1380 1381 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_MASK 0xFF 1382 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS1_VAL_15_8_SHIFT 0 1383 1384 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_MASK 0x0F 1385 #define SERDES_25G_LANE_CDR_RXCLK_ACCUM_LAST_PEAK_STATUS2_VAL_19_16_SHIFT 0 1386 1387 /********************************* Lane CDR_REFCLK ***************************/ 1388 #define SERDES_25G_LANE_CDR_REFCLK_BASE 0x180 1389 1390 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x00) 1391 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x01) 1392 #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x06) 1393 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0A) 1394 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0B) 1395 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x0C) 1396 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x10) 1397 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x11) 1398 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x18) 1399 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x19) 1400 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1A) 1401 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x1B) 1402 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x20) 1403 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x21) 1404 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x22) 1405 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x24) 1406 #define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ADDR (SERDES_25G_LANE_CDR_REFCLK_BASE + 0x30) 1407 /******************************************************************************* 1408 * masks and shifts 1409 ******************************************************************************/ 1410 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_MASK 0x01 1411 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_SHIFT 0 1412 1413 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_MASK 0x02 1414 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_PD_RXCDR_EYE_SHIFT 1 1415 1416 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_MASK 0x04 1417 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL0_RXCDR_TOGGLE_EN_SHIFT 2 1418 1419 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_MASK 0xFF 1420 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PD_CTRL1_RXCDR_PHD_EN_SHIFT 0 1421 1422 #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_MASK 0x01 1423 #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_PHD_N_SHIFT 0 1424 1425 #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_MASK 0x02 1426 #define SERDES_25G_LANE_CDR_REFCLK_AFE_RST_CTRL0_RST_RXCDR_CLKDIV_N_SHIFT 1 1427 1428 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_MASK 0x01 1429 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL0_RXCDR_VCO_KICK_SHIFT 0 1430 1431 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_MASK 0x01 1432 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REGDAC_BANDWIDTH_SHIFT 0 1433 1434 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_MASK 0x02 1435 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_SHORT_VOSC_PRP_SHIFT 1 1436 1437 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_MASK 0x0C 1438 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL1_RXCDR_REFDAC_GAIN_SHIFT 2 1439 1440 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_MASK 0x07 1441 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_SHIFT 0 1442 1443 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_MASK 0x1F 1444 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_BBSTEP_SHIFT 0 1445 1446 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_MASK 0x60 1447 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL0_RXCDR_CLKDIV_SHIFT 5 1448 1449 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_MASK 0x03 1450 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_CLKDIV_SWING_SHIFT 0 1451 1452 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_MASK 0x3C 1453 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CTRL1_RXCDR_SPARE_SHIFT 2 1454 1455 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_MASK 0x7F 1456 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_SHIFT 0 1457 1458 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_MASK 0x80 1459 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_SRC_SEL_SHIFT 7 1460 1461 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_MASK 0x7F 1462 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_SHIFT 0 1463 1464 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_MASK 0x80 1465 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_SRC_SEL_SHIFT 7 1466 1467 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_MASK 0x7F 1468 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_SHIFT 0 1469 1470 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_MASK 0x07 1471 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_CAP_SHIFT 0 1472 1473 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_MASK 0x18 1474 #define SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL3_RXCDR_PI_SWING_SHIFT 3 1475 1476 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_MASK 0x01 1477 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_CAL_EN_SHIFT 0 1478 1479 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_MASK 0x02 1480 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL0_RXCDR_VCOCAL_DIV4_SHIFT 1 1481 1482 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_MASK 0x0F 1483 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL1_RXCDR_VCOCAL_LOAD_VAL_11_8_SHIFT 0 1484 1485 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_MASK 0xFF 1486 #define SERDES_25G_LANE_CDR_REFCLK_AFE_CAL_CTRL2_RXCDR_VCOCAL_LOAD_VAL_7_0_SHIFT 0 1487 1488 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_MASK 0x01 1489 #define SERDES_25G_LANE_CDR_REFCLK_AFE_VCOCAL_STATUS0_RXCDR_VCOCAL_UP_SHIFT 0 1490 1491 #define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_MASK 0x7F 1492 #define SERDES_25G_LANE_CDR_REFCLK_RXCDR_HSCAN_EYE_CFG_ZERO_PHASE_SHIFT 0 1493 1494 /********************************* Lane BIST *********************************/ 1495 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_ADDR 0x00 1496 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_ADDR 0x01 1497 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_ADDR 0x02 1498 #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_ADDR 0x03 1499 #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_ADDR 0x04 1500 #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_ADDR 0x05 1501 #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_ADDR 0x06 1502 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR 0x10 1503 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_ADDR 0x12 1504 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_ADDR 0x13 1505 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_ADDR 0x14 1506 #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_ADDR 0x16 1507 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_ADDR 0x19 1508 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR 0x1B 1509 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR 0x1C 1510 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR 0x22 1511 #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_ADDR 0x24 1512 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_ADDR 0x25 1513 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ADDR 0x26 1514 #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_ADDR 0x27 1515 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_ADDR 0x30 1516 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_ADDR 0x31 1517 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR 0x38 1518 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_ADDR 0x39 1519 #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_ADDR 0x3A 1520 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_ADDR 0x3B 1521 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_ADDR 0x3C 1522 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_ADDR 0x3D 1523 #define SERDES_25G_LANE_TOP_ERR_CTRL1_ADDR 0x40 1524 #define SERDES_25G_LANE_TOP_ERR_CTRL2_ADDR 0x41 1525 /******************************************************************************* 1526 * masks and shifts 1527 ******************************************************************************/ 1528 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_MASK 0x01 1529 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT 0 1530 1531 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_MASK 0x02 1532 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT 1 1533 1534 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_MASK 0x04 1535 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT 2 1536 1537 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_MASK 0x08 1538 #define SERDES_25G_LANE_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT 3 1539 1540 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_MASK 0x01 1541 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXTERM_SHIFT 0 1542 1543 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_MASK 0x02 1544 #define SERDES_25G_LANE_TOP_AFE_RX_PD_CTRL_PD_RXDP_SHIFT 1 1545 1546 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_MASK 0x01 1547 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_REG_TXCP_SHIFT 0 1548 1549 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_MASK 0x02 1550 #define SERDES_25G_LANE_TOP_AFE_TX_PD_CTRL_PD_TXCP_SHIFT 1 1551 1552 #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_MASK 0x01 1553 #define SERDES_25G_LANE_TOP_AFE_BIAS_PD_CTRL_PD_BIAS_LANE_SHIFT 0 1554 1555 #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_MASK 0x01 1556 #define SERDES_25G_LANE_TOP_AFE_RX_RST_CTRL_RST_RXDP_N_SHIFT 0 1557 1558 #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_MASK 0x04 1559 #define SERDES_25G_LANE_TOP_AFE_TX_RST_CTRL_RST_TXDP_N_SHIFT 2 1560 1561 #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_MASK 0x0F 1562 #define SERDES_25G_LANE_TOP_AFE_BIAS_CTRL_BIAS_SPARE_SHIFT 0 1563 1564 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK 0x0F 1565 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_SHIFT 0 1566 1567 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_MASK 0x30 1568 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRICKLE_SHIFT 4 1569 1570 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_MASK 0x40 1571 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_PASS_EN_SHIFT 6 1572 1573 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_MASK 0x01 1574 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_TSTCLK_EN_SHIFT 0 1575 1576 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_MASK 0x06 1577 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL2_TXCP_CLKDIV_SHIFT 1 1578 1579 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_MASK 0x0F 1580 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL3_TXCP_SPARE_SHIFT 0 1581 1582 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_MASK 0x03 1583 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_CLKDIV_SWING_SHIFT 0 1584 1585 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_MASK 0x04 1586 #define SERDES_25G_LANE_TOP_AFE_TXCP_CTRL4_TXCP_TOGGLE_EN_SHIFT 2 1587 1588 #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_MASK 0xF0 1589 #define SERDES_25G_LANE_TOP_AFE_TXDP_CTRL0_TXDP_SPARE_SHIFT 4 1590 1591 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_MASK 0x07 1592 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_CLKDLY_SHIFT 0 1593 1594 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_MASK 0xF0 1595 #define SERDES_25G_LANE_TOP_AFE_RXDP_CTRL0_RXDP_SPARE_SHIFT 4 1596 1597 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_MASK 0x07 1598 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_CMFILT_SHIFT 0 1599 1600 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK 0x08 1601 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT 3 1602 1603 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK 0x10 1604 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT 4 1605 1606 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK 0x1F 1607 #define SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT 0 1608 1609 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK 0x03 1610 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT 0 1611 1612 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_MASK 0x04 1613 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT 2 1614 1615 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_MASK 0x10 1616 #define SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT 4 1617 1618 #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_MASK 0x01 1619 #define SERDES_25G_LANE_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT 0 1620 1621 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_MASK 0x07 1622 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_STATE_SHIFT 0 1623 1624 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_MASK 0x08 1625 #define SERDES_25G_LANE_TOP_PWR_STATE_REQ_STATUS_REQ_SHIFT 3 1626 1627 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_MASK 0x07 1628 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_STATE_SHIFT 0 1629 1630 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_MASK 0x08 1631 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_ACK_SHIFT 3 1632 1633 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_MASK 0x70 1634 #define SERDES_25G_LANE_TOP_PWR_STATE_ACK_CTRL_DELAY_LEN_SHIFT 4 1635 1636 #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_MASK 0x01 1637 #define SERDES_25G_LANE_TOP_PHY_IF_STATUS_LN_OK_SHIFT 0 1638 1639 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_MASK 0x07 1640 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_DATA_EDELAY_SHIFT 0 1641 1642 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_MASK 0x38 1643 #define SERDES_25G_LANE_TOP_DELAY_CTRL0_RX_EDGE_DELAY_SHIFT 3 1644 1645 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_MASK 0x07 1646 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_DATA_IDELAY_SHIFT 0 1647 1648 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_MASK 0x38 1649 #define SERDES_25G_LANE_TOP_DELAY_CTRL1_RX_EYE_DELAY_SHIFT 3 1650 1651 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK 0x01 1652 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT 0 1653 1654 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_MASK 0x01 1655 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_OVR_EN_SHIFT 0 1656 1657 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_MASK 0x02 1658 #define SERDES_25G_LANE_TOP_LN_STAT_CTRL_OVR_RST_PD_READY_SHIFT 1 1659 1660 #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_MASK 0x01 1661 #define SERDES_25G_LANE_TOP_LN_STAT_STATUS0_RST_PD_READY_SHIFT 0 1662 1663 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_MASK 0x01 1664 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT 0 1665 1666 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_MASK 0x02 1667 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT 1 1668 1669 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_MASK 0x04 1670 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT 2 1671 1672 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_MASK 0x08 1673 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_RXPOLARITY_SHIFT 3 1674 1675 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_MASK 0x10 1676 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_TX_EN_SHIFT 4 1677 1678 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_MASK 0x20 1679 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_EN_SHIFT 5 1680 1681 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_MASK 0x40 1682 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR0_LOS_EII_VALUE_SHIFT 6 1683 1684 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_MASK 0x01 1685 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_OVR_EN_SHIFT 0 1686 1687 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_MASK 0x06 1688 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_PD_SHIFT 1 1689 1690 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_MASK 0x08 1691 #define SERDES_25G_LANE_TOP_LN_CTRL_OVR1_RST_N_SHIFT 3 1692 1693 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_MASK 0x01 1694 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_TX_DATA_WIDTH_SHIFT 0 1695 1696 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_MASK 0x02 1697 #define SERDES_25G_LANE_TOP_LN_CTRL_STATUS0_RX_DATA_WIDTH_SHIFT 1 1698 1699 #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_MASK 0xFF 1700 #define SERDES_25G_LANE_TOP_ERR_CTRL1_ERR_CODE_7_0_SHIFT 0 1701 1702 #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_MASK 0xFF 1703 #define SERDES_25G_LANE_TOP_ERR_CTRL2_ERR_CODE_15_8_SHIFT 0 1704 1705 /********************************* LEQ_REFCLK *********************************/ 1706 #define SERDES_25G_LANE_LEQ_REFCLK_BASE 0x200 1707 1708 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x00) 1709 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x02) 1710 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x03) 1711 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x05) 1712 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x07) 1713 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x09) 1714 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0A) 1715 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0B) 1716 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0C) 1717 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0E) 1718 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x0F) 1719 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x10) 1720 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x11) 1721 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x20) 1722 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x21) 1723 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x22) 1724 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x23) 1725 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x24) 1726 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x25) 1727 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x26) 1728 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x27) 1729 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x28) 1730 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x29) 1731 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2A) 1732 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2B) 1733 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2C) 1734 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x2E) 1735 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x30) 1736 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x31) 1737 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x32) 1738 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x33) 1739 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x34) 1740 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x35) 1741 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x36) 1742 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x37) 1743 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x38) 1744 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x39) 1745 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3A) 1746 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3D) 1747 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x3E) 1748 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x40) 1749 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x41) 1750 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x42) 1751 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x43) 1752 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x44) 1753 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x45) 1754 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x46) 1755 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x50) 1756 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x51) 1757 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x52) 1758 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x53) 1759 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x54) 1760 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x55) 1761 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x56) 1762 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x57) 1763 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x58) 1764 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x59) 1765 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5A) 1766 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5B) 1767 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5C) 1768 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5D) 1769 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5E) 1770 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x5F) 1771 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x60) 1772 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x61) 1773 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x62) 1774 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x63) 1775 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x64) 1776 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x65) 1777 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x66) 1778 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x67) 1779 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x68) 1780 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x70) 1781 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x71) 1782 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x72) 1783 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x73) 1784 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x74) 1785 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x75) 1786 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x76) 1787 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x80) 1788 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x81) 1789 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x82) 1790 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x83) 1791 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x84) 1792 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x85) 1793 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x86) 1794 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x87) 1795 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x88) 1796 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x90) 1797 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x91) 1798 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x92) 1799 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x93) 1800 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x94) 1801 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x95) 1802 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x96) 1803 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x98) 1804 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x99) 1805 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9A) 1806 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9B) 1807 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9C) 1808 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0x9D) 1809 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA0) 1810 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA1) 1811 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA2) 1812 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA3) 1813 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA6) 1814 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA7) 1815 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA8) 1816 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xA9) 1817 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAB) 1818 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAC) 1819 #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAE) 1820 #define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xAF) 1821 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB8) 1822 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_ADDR (SERDES_25G_LANE_LEQ_REFCLK_BASE + 0xB9) 1823 1824 /******************************************************************************* 1825 * masks and shifts 1826 ******************************************************************************/ 1827 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_MASK 0x3F 1828 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_SHIFT 0 1829 1830 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_MASK 0x40 1831 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PD_CTRL0_PD_RXLEQ_BIASGEN_SHIFT 6 1832 1833 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_MASK 0xFF 1834 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL0_RXLEQ_BIAS_SHIFT 0 1835 1836 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_MASK 0x07 1837 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_VGSW_SEL_SHIFT 0 1838 1839 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_MASK 0x18 1840 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_SHIFT 3 1841 1842 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_MASK 0x01 1843 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_MUTE_SHIFT 0 1844 1845 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_MASK 0x06 1846 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_SHIFT 1 1847 1848 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_MASK 0x08 1849 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_PRECH_SHIFT 3 1850 1851 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_MASK 0x01 1852 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_EQ_CTRL0_RXLEQ_EQ_SQL_DIR_SHIFT 0 1853 1854 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_MASK 0x0F 1855 #define SERDES_25G_LANE_LEQ_REFCLK_AFE_MISC_CTRL0_RXLEQ_SPARE_SHIFT 0 1856 1857 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_MASK 0x07 1858 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START0_SHIFT 0 1859 1860 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_MASK 0x38 1861 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL0_GN_LOADRES_START1_SHIFT 3 1862 1863 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_MASK 0x07 1864 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START2_SHIFT 0 1865 1866 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_MASK 0x38 1867 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL1_GN_LOADRES_START3_SHIFT 3 1868 1869 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_MASK 0x03 1870 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE0_SHIFT 0 1871 1872 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_MASK 0x0C 1873 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE1_SHIFT 2 1874 1875 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_MASK 0x30 1876 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE2_SHIFT 4 1877 1878 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_MASK 0xC0 1879 #define SERDES_25G_LANE_LEQ_REFCLK_GN_CTRL2_GN_BIASI_RATE3_SHIFT 6 1880 1881 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_MASK 0x07 1882 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START0_SHIFT 0 1883 1884 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_MASK 0x38 1885 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL0_EQ_LOADRES_START1_SHIFT 3 1886 1887 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_MASK 0x07 1888 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START2_SHIFT 0 1889 1890 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_MASK 0x38 1891 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL1_EQ_LOADRES_START3_SHIFT 3 1892 1893 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_MASK 0x07 1894 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START0_SHIFT 0 1895 1896 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_MASK 0x38 1897 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL2_EQ_BIASRES_START1_SHIFT 3 1898 1899 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_MASK 0x07 1900 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START2_SHIFT 0 1901 1902 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_MASK 0x38 1903 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_CTRL3_EQ_BIASRES_START3_SHIFT 3 1904 1905 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK 0x01 1906 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT 0 1907 1908 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_MASK 0x04 1909 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_STATE_RESET_SHIFT 2 1910 1911 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_MASK 0x0F 1912 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_OPCODE_SHIFT 0 1913 1914 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_MASK 0xF0 1915 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_LEQ_FSM_CMD_TARGET_SHIFT 4 1916 1917 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_MASK 0xFF 1918 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_LEQ_FSM_CMD_SCRATCHPAD_SHIFT 0 1919 1920 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_MASK 0xFF 1921 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_LEQ_FSM_CMD_MISC_OPTION_SHIFT 0 1922 1923 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_MASK 0x07 1924 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_SHIFT 0 1925 1926 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_MASK 0x38 1927 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_SHIFT 3 1928 1929 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_MASK 0x40 1930 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MAX_CLAMP_SHIFT 6 1931 1932 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_MASK 0x80 1933 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_MIN_CLAMP_SHIFT 7 1934 1935 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_MASK 0x0F 1936 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_STATE_SHIFT 0 1937 1938 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_MASK 0xF0 1939 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS1_LEQ_FSM_LAST_RESULT_SHIFT 4 1940 1941 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_MASK 0xFF 1942 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS2_LEQ_FSM_LAST_STEP_SHIFT 0 1943 1944 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_MASK 0xFF 1945 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_LEQ_FSM_LAST_VALUE_SHIFT 0 1946 1947 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_MASK 0x0F 1948 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_OPCODE_SHIFT 0 1949 1950 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_MASK 0xF0 1951 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS4_LEQ_FSM_LAST_TARGET_SHIFT 4 1952 1953 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_MASK 0xFF 1954 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL1_LEQ_FSM_TIMEOUT_LIMIT_7_0_SHIFT 0 1955 1956 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_MASK 0xFF 1957 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL2_LEQ_FSM_TIMEOUT_LIMIT_15_8_SHIFT 0 1958 1959 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_MASK 0x02 1960 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_SHIFT 1 1961 1962 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_MASK 0xFF 1963 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS6_LEQ_FSM_2LST_VALUE_SHIFT 0 1964 1965 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_MASK 0xFF 1966 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_OUTINTF_CTRL0_LEQ_OUTINTF_RDY_WAIT_SHIFT 0 1967 1968 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_MASK 0x0F 1969 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT 0 1970 1971 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_MASK 0x0F 1972 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL1_AGCLOS_VALUE_MAX_SHIFT 0 1973 1974 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_MASK 0x0F 1975 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL2_AGCLOS_VALUE_MIN_SHIFT 0 1976 1977 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_MASK 0x0F 1978 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_WRWAIT_TIME_SHIFT 0 1979 1980 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_MASK 0x40 1981 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_INIT_TIMEOUT_DISABLE_SHIFT 6 1982 1983 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_MASK 0x80 1984 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL3_AGCLOS_MEASURE_TIMEOUT_DISABLE_SHIFT 7 1985 1986 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_MASK 0x01 1987 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_BY1_SHIFT 0 1988 1989 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_MASK 0x02 1990 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_ERROR_SIGN_SHIFT 1 1991 1992 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_MASK 0x1C 1993 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL4_AGCLOS_STEP_SIZE_SHIFT 2 1994 1995 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_MASK 0x0F 1996 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_BOUNCE_LIMIT_SHIFT 0 1997 1998 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_MASK 0x30 1999 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_AVG_SHIFT 4 2000 2001 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_MASK 0x40 2002 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL5_AGCLOS_LASTWR_FLOOR_SHIFT 6 2003 2004 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_MASK 0x0F 2005 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL6_AGCLOS_LASTWR_ADJUST_SHIFT 0 2006 2007 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_MASK 0xFF 2008 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL7_AGCLOS_PEAK_ACQ_TIME_7_0_SHIFT 0 2009 2010 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_MASK 0xFF 2011 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL8_AGCLOS_PEAK_ACQ_TIME_15_8_SHIFT 0 2012 2013 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_MASK 0xFF 2014 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL9_AGCLOS_PEAK_ACQ_TIME_23_16_SHIFT 0 2015 2016 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_MASK 0x03 2017 #define SERDES_25G_LANE_LEQ_REFCLK_AGCLOS_CTRL10_AGCLOS_PEAK_ACQ_TIME_25_24_SHIFT 0 2018 2019 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_MASK 0x0F 2020 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_WRWAIT_TIME_SHIFT 0 2021 2022 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_MASK 0x10 2023 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL0_PLE_LFG_STEP_BY1_SHIFT 4 2024 2025 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_MASK 0x07 2026 #define SERDES_25G_LANE_LEQ_REFCLK_PLE_LFG_CTRL1_PLE_LFG_START_SHIFT 0 2027 2028 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_MASK 0x1F 2029 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT 0 2030 2031 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_MASK 0x1F 2032 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL1_EQ_HFG_SQL_VALUE_MAX_SHIFT 0 2033 2034 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_MASK 0x1F 2035 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL2_EQ_HFG_SQL_VALUE_MIN_SHIFT 0 2036 2037 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_MASK 0x0F 2038 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_WRWAIT_TIME_SHIFT 0 2039 2040 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2041 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL3_EQ_HFG_SQL_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2042 2043 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_MASK 0x01 2044 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_BY1_SHIFT 0 2045 2046 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_MASK 0x02 2047 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_ERROR_SIGN_SHIFT 1 2048 2049 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_MASK 0x1C 2050 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL4_EQ_HFG_SQL_STEP_SIZE_SHIFT 2 2051 2052 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_MASK 0x0F 2053 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_BOUNCE_LIMIT_SHIFT 0 2054 2055 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_MASK 0x30 2056 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_AVG_SHIFT 4 2057 2058 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_MASK 0x40 2059 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL5_EQ_HFG_SQL_LASTWR_FLOOR_SHIFT 6 2060 2061 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_MASK 0x1F 2062 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_HFG_SQL_CTRL6_EQ_HFG_SQL_LASTWR_ADJUST_SHIFT 0 2063 2064 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_MASK 0x01 2065 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE0_SHIFT 0 2066 2067 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_MASK 0x02 2068 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE1_SHIFT 1 2069 2070 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_MASK 0x04 2071 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE2_SHIFT 2 2072 2073 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_MASK 0x08 2074 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL0_EQ_SQL_MAP_OPTION_RATE3_SHIFT 3 2075 2076 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_MASK 0x07 2077 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP0_RATE0_SHIFT 0 2078 2079 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_MASK 0x70 2080 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL1_EQ_SQL_MAP1_RATE0_SHIFT 4 2081 2082 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_MASK 0x07 2083 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP2_RATE0_SHIFT 0 2084 2085 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_MASK 0x70 2086 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL2_EQ_SQL_MAP3_RATE0_SHIFT 4 2087 2088 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_MASK 0x07 2089 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP4_RATE0_SHIFT 0 2090 2091 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_MASK 0x70 2092 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL3_EQ_SQL_MAP5_RATE0_SHIFT 4 2093 2094 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_MASK 0x07 2095 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP6_RATE0_SHIFT 0 2096 2097 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_MASK 0x70 2098 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL4_EQ_SQL_MAP7_RATE0_SHIFT 4 2099 2100 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_MASK 0x07 2101 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP8_RATE0_SHIFT 0 2102 2103 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_MASK 0x70 2104 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL5_EQ_SQL_MAP9_RATE0_SHIFT 4 2105 2106 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_MASK 0x07 2107 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP10_RATE0_SHIFT 0 2108 2109 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_MASK 0x70 2110 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL6_EQ_SQL_MAP11_RATE0_SHIFT 4 2111 2112 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_MASK 0x07 2113 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP0_RATE1_SHIFT 0 2114 2115 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_MASK 0x70 2116 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL7_EQ_SQL_MAP1_RATE1_SHIFT 4 2117 2118 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_MASK 0x07 2119 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP2_RATE1_SHIFT 0 2120 2121 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_MASK 0x70 2122 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL8_EQ_SQL_MAP3_RATE1_SHIFT 4 2123 2124 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_MASK 0x07 2125 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP4_RATE1_SHIFT 0 2126 2127 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_MASK 0x70 2128 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL9_EQ_SQL_MAP5_RATE1_SHIFT 4 2129 2130 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_MASK 0x07 2131 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP6_RATE1_SHIFT 0 2132 2133 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_MASK 0x70 2134 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL10_EQ_SQL_MAP7_RATE1_SHIFT 4 2135 2136 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_MASK 0x07 2137 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP8_RATE1_SHIFT 0 2138 2139 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_MASK 0x70 2140 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL11_EQ_SQL_MAP9_RATE1_SHIFT 4 2141 2142 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_MASK 0x07 2143 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP10_RATE1_SHIFT 0 2144 2145 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_MASK 0x70 2146 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL12_EQ_SQL_MAP11_RATE1_SHIFT 4 2147 2148 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_MASK 0x07 2149 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP0_RATE2_SHIFT 0 2150 2151 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_MASK 0x70 2152 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL13_EQ_SQL_MAP1_RATE2_SHIFT 4 2153 2154 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_MASK 0x07 2155 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP2_RATE2_SHIFT 0 2156 2157 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_MASK 0x70 2158 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL14_EQ_SQL_MAP3_RATE2_SHIFT 4 2159 2160 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_MASK 0x07 2161 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP4_RATE2_SHIFT 0 2162 2163 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_MASK 0x70 2164 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL15_EQ_SQL_MAP5_RATE2_SHIFT 4 2165 2166 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_MASK 0x07 2167 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP6_RATE2_SHIFT 0 2168 2169 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_MASK 0x70 2170 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL16_EQ_SQL_MAP7_RATE2_SHIFT 4 2171 2172 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_MASK 0x07 2173 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP8_RATE2_SHIFT 0 2174 2175 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_MASK 0x70 2176 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL17_EQ_SQL_MAP9_RATE2_SHIFT 4 2177 2178 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_MASK 0x07 2179 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP10_RATE2_SHIFT 0 2180 2181 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_MASK 0x70 2182 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL18_EQ_SQL_MAP11_RATE2_SHIFT 4 2183 2184 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_MASK 0x07 2185 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP0_RATE3_SHIFT 0 2186 2187 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_MASK 0x70 2188 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL19_EQ_SQL_MAP1_RATE3_SHIFT 4 2189 2190 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_MASK 0x07 2191 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP2_RATE3_SHIFT 0 2192 2193 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_MASK 0x70 2194 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL20_EQ_SQL_MAP3_RATE3_SHIFT 4 2195 2196 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_MASK 0x07 2197 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP4_RATE3_SHIFT 0 2198 2199 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_MASK 0x70 2200 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL21_EQ_SQL_MAP5_RATE3_SHIFT 4 2201 2202 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_MASK 0x07 2203 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP6_RATE3_SHIFT 0 2204 2205 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_MASK 0x70 2206 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL22_EQ_SQL_MAP7_RATE3_SHIFT 4 2207 2208 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_MASK 0x07 2209 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP8_RATE3_SHIFT 0 2210 2211 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_MASK 0x70 2212 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL23_EQ_SQL_MAP9_RATE3_SHIFT 4 2213 2214 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_MASK 0x07 2215 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP10_RATE3_SHIFT 0 2216 2217 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_MASK 0x70 2218 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_SQL_CTRL24_EQ_SQL_MAP11_RATE3_SHIFT 4 2219 2220 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_MASK 0x03 2221 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT 0 2222 2223 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_MASK 0x03 2224 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MAX_SHIFT 0 2225 2226 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_MASK 0x0C 2227 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL1_GN_APG_VALUE_MIN_SHIFT 2 2228 2229 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_MASK 0x0F 2230 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_WRWAIT_TIME_SHIFT 0 2231 2232 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2233 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL2_GN_APG_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2234 2235 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_MASK 0x01 2236 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_BY1_SHIFT 0 2237 2238 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_MASK 0x02 2239 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_ERROR_SIGN_SHIFT 1 2240 2241 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_MASK 0x0C 2242 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL3_GN_APG_STEP_SIZE_SHIFT 2 2243 2244 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_MASK 0x0F 2245 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_BOUNCE_LIMIT_SHIFT 0 2246 2247 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_MASK 0x30 2248 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_AVG_SHIFT 4 2249 2250 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_MASK 0x40 2251 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL4_GN_APG_LASTWR_FLOOR_SHIFT 6 2252 2253 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_MASK 0x03 2254 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL5_GN_APG_LASTWR_ADJUST_SHIFT 0 2255 2256 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_MASK 0x03 2257 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_DELTA_SHIFT 0 2258 2259 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_MASK 0x0C 2260 #define SERDES_25G_LANE_LEQ_REFCLK_GN_APG_CTRL6_GN_APG_CCL_MAX_SHIFT 2 2261 2262 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_MASK 0x1F 2263 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT 0 2264 2265 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_MASK 0x1F 2266 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT 0 2267 2268 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_MASK 0x1F 2269 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT 0 2270 2271 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_MASK 0x0F 2272 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_WRWAIT_TIME_SHIFT 0 2273 2274 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2275 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL3_EQ_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2276 2277 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_MASK 0x01 2278 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_BY1_SHIFT 0 2279 2280 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_MASK 0x02 2281 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_ERROR_SIGN_SHIFT 1 2282 2283 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_MASK 0x1C 2284 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL4_EQ_LFG_STEP_SIZE_SHIFT 2 2285 2286 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_MASK 0x0F 2287 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_BOUNCE_LIMIT_SHIFT 0 2288 2289 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_MASK 0x30 2290 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_AVG_SHIFT 4 2291 2292 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_MASK 0x40 2293 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL5_EQ_LFG_LASTWR_FLOOR_SHIFT 6 2294 2295 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_MASK 0x1F 2296 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL6_EQ_LFG_LASTWR_ADJUST_SHIFT 0 2297 2298 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_MASK 0x1F 2299 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL7_EQ_LFG_CCL_DELTA_SHIFT 0 2300 2301 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_MASK 0x1F 2302 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_LFG_CTRL8_EQ_LFG_CCL_MAX_SHIFT 0 2303 2304 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_MASK 0x1F 2305 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL0_GNEQ_CCL_LFG_START_SHIFT 0 2306 2307 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_MASK 0x1F 2308 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL1_GNEQ_CCL_LFG_VALUE_MAX_SHIFT 0 2309 2310 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_MASK 0x1F 2311 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL2_GNEQ_CCL_LFG_VALUE_MIN_SHIFT 0 2312 2313 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_MASK 0x0F 2314 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_WRWAIT_TIME_SHIFT 0 2315 2316 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_MASK 0x80 2317 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL3_GNEQ_CCL_LFG_MEASURE_TIMEOUT_DISABLE_SHIFT 7 2318 2319 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_MASK 0x01 2320 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_BY1_SHIFT 0 2321 2322 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_MASK 0x02 2323 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_ERROR_SIGN_SHIFT 1 2324 2325 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_MASK 0x1C 2326 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL4_GNEQ_CCL_LFG_STEP_SIZE_SHIFT 2 2327 2328 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_MASK 0x0F 2329 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_BOUNCE_LIMIT_SHIFT 0 2330 2331 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_MASK 0x30 2332 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_AVG_SHIFT 4 2333 2334 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_MASK 0x40 2335 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL5_GNEQ_CCL_LFG_LASTWR_FLOOR_SHIFT 6 2336 2337 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_MASK 0x1F 2338 #define SERDES_25G_LANE_LEQ_REFCLK_GNEQ_CCL_LFG_CTRL6_GNEQ_CCL_LFG_LASTWR_ADJUST_SHIFT 0 2339 2340 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_MASK 0x0F 2341 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_WRWAIT_TIME_SHIFT 0 2342 2343 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_MASK 0x10 2344 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL0_EQ_MB_STEP_BY1_SHIFT 4 2345 2346 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_MASK 0x0F 2347 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT 0 2348 2349 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_MASK 0xF0 2350 #define SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT 4 2351 2352 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_MASK 0xFF 2353 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL0_VSCAN_VALUE_MAX_SHIFT 0 2354 2355 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_MASK 0xFF 2356 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL1_VSCAN_VALUE_MIN_SHIFT 0 2357 2358 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_MASK 0x01 2359 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_BY1_SHIFT 0 2360 2361 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_MASK 0x02 2362 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_ERROR_SIGN_SHIFT 1 2363 2364 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_MASK 0x3C 2365 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL2_VSCAN_STEP_SIZE_SHIFT 2 2366 2367 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_MASK 0x0F 2368 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_BOUNCE_LIMIT_SHIFT 0 2369 2370 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_MASK 0x30 2371 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_AVG_SHIFT 4 2372 2373 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_MASK 0x40 2374 #define SERDES_25G_LANE_LEQ_REFCLK_VSCAN_CTRL3_VSCAN_LASTWR_FLOOR_SHIFT 6 2375 2376 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_MASK 0xFF 2377 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL0_HSCAN_VALUE_MAX_SHIFT 0 2378 2379 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_MASK 0xFF 2380 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL1_HSCAN_VALUE_MIN_SHIFT 0 2381 2382 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_MASK 0x01 2383 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_BY1_SHIFT 0 2384 2385 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_MASK 0x02 2386 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_ERROR_SIGN_SHIFT 1 2387 2388 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_MASK 0x3C 2389 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL2_HSCAN_STEP_SIZE_SHIFT 2 2390 2391 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_MASK 0x0F 2392 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_BOUNCE_LIMIT_SHIFT 0 2393 2394 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_MASK 0x30 2395 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_AVG_SHIFT 4 2396 2397 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_MASK 0x40 2398 #define SERDES_25G_LANE_LEQ_REFCLK_HSCAN_CTRL3_HSCAN_LASTWR_FLOOR_SHIFT 6 2399 2400 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_MASK 0xFF 2401 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD0_GN_APG_REF_N_SHIFT 0 2402 2403 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_MASK 0xFF 2404 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD1_GN_APG_REF_P_SHIFT 0 2405 2406 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_MASK 0xFF 2407 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD2_EQ_LFG_REF_N_SHIFT 0 2408 2409 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_MASK 0xFF 2410 #define SERDES_25G_LANE_LEQ_REFCLK_REF_THRESHOLD3_EQ_LFG_REF_P_SHIFT 0 2411 2412 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_MASK 0xFF 2413 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE0_EYE_PHASE_7_0_SHIFT 0 2414 2415 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_MASK 0x01 2416 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_8_SHIFT 0 2417 2418 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_MASK 0x02 2419 #define SERDES_25G_LANE_LEQ_REFCLK_EYE_PHASE1_EYE_PHASE_VALID_SHIFT 1 2420 2421 #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_MASK 0x01 2422 #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_ODDEYE_SHIFT 0 2423 2424 #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_MASK 0x02 2425 #define SERDES_25G_LANE_LEQ_REFCLK_EYEMON_CTRL0_EYE_MONITOR_PATH1_SHIFT 1 2426 2427 #define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_MASK 0x40 2428 #define SERDES_25G_LANE_LEQ_REFCLK_EYEINTF_CTRL0_EYEINTF_INIT_TIMEOUT_DISABLE_SHIFT 6 2429 2430 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_MASK 0xFF 2431 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE0_SHIFT 0 2432 2433 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_MASK 0xFF 2434 #define SERDES_25G_LANE_LEQ_REFCLK_LEQ_REFCLK_SPARE1_SHIFT 0 2435 2436 /********************************* DRV_REFCLK *********************************/ 2437 #define SERDES_25G_LANE_DRV_REFCLK_BASE 0x380 2438 2439 #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x00) 2440 #define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x01) 2441 #define SERDES_25G_LANE_DRV_AFE_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x03) 2442 #define SERDES_25G_LANE_DRV_AFE_CTRL2_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x04) 2443 #define SERDES_25G_LANE_DRV_AFE_CTRL3_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x05) 2444 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x06) 2445 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x08) 2446 #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x09) 2447 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0A) 2448 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0B) 2449 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0C) 2450 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x0D) 2451 #define SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x10) 2452 #define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x11) 2453 #define SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x12) 2454 #define SERDES_25G_LANE_DRV_TXEQ_CTRL2_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x13) 2455 #define SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x14) 2456 #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x15) 2457 #define SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR (SERDES_25G_LANE_DRV_REFCLK_BASE + 0x16) 2458 /******************************************************************************* 2459 * masks and shifts 2460 ******************************************************************************/ 2461 #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_MASK 0x01 2462 #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_PD_TXDRV_SHIFT 0 2463 2464 #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_MASK 0x02 2465 #define SERDES_25G_LANE_DRV_AFE_PD_CTRL0_TXDRV_LP_IDLE_SHIFT 1 2466 2467 #define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_MASK 0x01 2468 #define SERDES_25G_LANE_DRV_AFE_RST_CTRL0_RST_TXDRV_DIV2_N_SHIFT 0 2469 2470 #define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_MASK 0xFF 2471 #define SERDES_25G_LANE_DRV_AFE_CTRL1_TXDRV_SPARE_SHIFT 0 2472 2473 #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_MASK 0x01 2474 #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_TOGGLE_EN_SHIFT 0 2475 2476 #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_MASK 0x3E 2477 #define SERDES_25G_LANE_DRV_AFE_CTRL2_TXDRV_CLK_DELAY_SHIFT 1 2478 2479 #define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_MASK 0x07 2480 #define SERDES_25G_LANE_DRV_AFE_CTRL3_TXDRV_CO_POL_SHIFT 0 2481 2482 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_MASK 0x01 2483 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_P5_SHIFT 0 2484 2485 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_MASK 0x02 2486 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X1_SHIFT 1 2487 2488 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_MASK 0x1C 2489 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_C1_X2_SHIFT 2 2490 2491 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_MASK 0x20 2492 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X1_SHIFT 5 2493 2494 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_MASK 0xC0 2495 #define SERDES_25G_LANE_DRV_AFE_C1_CTRL0_TXDRV_SEL_CXC1_X2_SHIFT 6 2496 2497 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_MASK 0x01 2498 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_P5_SHIFT 0 2499 2500 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_MASK 0x02 2501 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X1_SHIFT 1 2502 2503 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_MASK 0x0C 2504 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CM1_X2_SHIFT 2 2505 2506 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_MASK 0x10 2507 #define SERDES_25G_LANE_DRV_AFE_CM1_CTRL0_TXDRV_SEL_CXCM1_X2_SHIFT 4 2508 2509 #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_MASK 0x07 2510 #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X1_SHIFT 0 2511 2512 #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_MASK 0xF8 2513 #define SERDES_25G_LANE_DRV_AFE_ATT_CTRL0_TXDRV_SEL_ATT_X2_SHIFT 3 2514 2515 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_MASK 0x07 2516 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_CXN_X1_SHIFT 0 2517 2518 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_MASK 0x18 2519 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL0_TXDRV_SEL_FIXEDCXN_X1_SHIFT 3 2520 2521 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_MASK 0x1F 2522 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_CXN_X2_SHIFT 0 2523 2524 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_MASK 0x60 2525 #define SERDES_25G_LANE_DRV_AFE_CALN_CTRL1_TXDRV_SEL_FIXEDCXN_XP5_SHIFT 5 2526 2527 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_MASK 0x07 2528 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_CXP_X1_SHIFT 0 2529 2530 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_MASK 0x18 2531 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL0_TXDRV_SEL_FIXEDCXP_X1_SHIFT 3 2532 2533 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_MASK 0x1F 2534 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_CXP_X2_SHIFT 0 2535 2536 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_MASK 0x60 2537 #define SERDES_25G_LANE_DRV_AFE_CALP_CTRL1_TXDRV_SEL_FIXEDCXP_XP5_SHIFT 5 2538 2539 #define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK 0x01 2540 #define SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT 0 2541 2542 #define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_MASK 0x01 2543 #define SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_SHIFT 0 2544 2545 #define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK 0x1F 2546 #define SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT 0 2547 2548 #define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_MASK 0x03 2549 #define SERDES_25G_LANE_DRV_TXEQ_CTRL2_TXEQ_C2_SHIFT 0 2550 2551 #define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK 0x0F 2552 #define SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT 0 2553 2554 #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_MASK 0x01 2555 #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_TXEQ_1LSB_MODE_SHIFT 0 2556 2557 #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_MASK 0x02 2558 #define SERDES_25G_LANE_DRV_TXEQ_CTRL4_SWING_1LSB_MODE_SHIFT 1 2559 2560 #define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK 0x0F 2561 #define SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT 0 2562 2563 /********************************* DFE REFCLK *********************************/ 2564 #define SERDES_25G_LANE_DFE_REFCLK_BASE 0x400 2565 2566 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x00) 2567 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x01) 2568 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x02) 2569 #define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x04) 2570 #define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x06) 2571 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0A) 2572 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0C) 2573 #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x0E) 2574 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x10) 2575 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x12) 2576 #define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x14) 2577 #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x16) 2578 #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x18) 2579 #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x19) 2580 #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x1B) 2581 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x20) 2582 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x21) 2583 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x22) 2584 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x23) 2585 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x24) 2586 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x25) 2587 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x26) 2588 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x27) 2589 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x28) 2590 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2A) 2591 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2B) 2592 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2C) 2593 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2D) 2594 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2E) 2595 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x2F) 2596 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x30) 2597 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x31) 2598 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x32) 2599 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x33) 2600 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x34) 2601 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x35) 2602 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x36) 2603 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x37) 2604 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x38) 2605 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x39) 2606 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3A) 2607 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3B) 2608 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3C) 2609 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3D) 2610 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3E) 2611 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x3F) 2612 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x40) 2613 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x41) 2614 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x42) 2615 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x50) 2616 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x51) 2617 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x52) 2618 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x53) 2619 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x54) 2620 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x55) 2621 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x56) 2622 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x57) 2623 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x58) 2624 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x59) 2625 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5A) 2626 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5B) 2627 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5C) 2628 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5D) 2629 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5E) 2630 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x5F) 2631 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x60) 2632 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x61) 2633 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x62) 2634 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x63) 2635 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x64) 2636 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ADDR (SERDES_25G_LANE_DFE_REFCLK_BASE + 0x65) 2637 /******************************************************************************* 2638 * masks and shifts 2639 ******************************************************************************/ 2640 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_MASK 0x01 2641 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_SHIFT 0 2642 2643 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_MASK 0x3E 2644 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL0_PD_RXDFE_TAP_SHIFT 1 2645 2646 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_MASK 0x03 2647 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_EVEN_PATH_SHIFT 0 2648 2649 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_MASK 0x0C 2650 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL1_PD_RXDFE_ODD_PATH_SHIFT 2 2651 2652 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_MASK 0x07 2653 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_EVEN_SHIFT 0 2654 2655 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_MASK 0x38 2656 #define SERDES_25G_LANE_DFE_REFCLK_AFE_PD_CTRL2_PD_RXDFE_EYE_ODD_SHIFT 3 2657 2658 #define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_MASK 0x01 2659 #define SERDES_25G_LANE_DFE_REFCLK_AFE_RST_CTRL0_RST_RXDFE_N_SHIFT 0 2660 2661 #define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_MASK 0x01 2662 #define SERDES_25G_LANE_DFE_REFCLK_AFE_TOGGLE_CTRL0_RXDFE_TOGGLE_EN_SHIFT 0 2663 2664 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_MASK 0x01 2665 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_EVEN_SHIFT 0 2666 2667 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_MASK 0x02 2668 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_MUTE_EYE_ODD_SHIFT 1 2669 2670 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_MASK 0x0C 2671 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MUTE_CTRL0_RXDFE_EDGE_MUTE_SHIFT 2 2672 2673 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_MASK 0x0F 2674 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLK_DELAY_SHIFT 0 2675 2676 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_MASK 0x30 2677 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CLK_CTRL0_RXDFE_CLKDIV_OVR_SHIFT 4 2678 2679 #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_MASK 0x0F 2680 #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYECLK_DELAY_SHIFT 0 2681 2682 #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_MASK 0x30 2683 #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_CLKDIVEYE_OVR_SHIFT 4 2684 2685 #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_MASK 0xC0 2686 #define SERDES_25G_LANE_DFE_REFCLK_AFE_EYECLK_CTRL0_RXDFE_EYERESAMP_ADJ_SHIFT 6 2687 2688 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_MASK 0x0F 2689 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLI_SHIFT 0 2690 2691 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_MASK 0x30 2692 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_SHIFT 4 2693 2694 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_MASK 0x40 2695 #define SERDES_25G_LANE_DFE_REFCLK_AFE_CML_CTRL0_RXDFE_CMLR_LTCH_SHIFT 6 2696 2697 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_MASK 0x01 2698 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_SUMGAIN_SHIFT 0 2699 2700 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_MASK 0x06 2701 #define SERDES_25G_LANE_DFE_REFCLK_AFE_MISC_CTRL0_RXDFE_LDR_SHIFT 1 2702 2703 #define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_MASK 0xFF 2704 #define SERDES_25G_LANE_DFE_REFCLK_AFE_SPARE_RXDFE_SPARE_SHIFT 0 2705 2706 #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_MASK 0x01 2707 #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIV_QSAMPLE_SHIFT 0 2708 2709 #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_MASK 0x1E 2710 #define SERDES_25G_LANE_DFE_REFCLK_AFE_QSAMPLE_STATUS0_RXDFE_CLKDIVEYE_QSAMPLE_SHIFT 1 2711 2712 #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_MASK 0xFF 2713 #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL0_MAG_SHIFT 0 2714 2715 #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_MASK 0x01 2716 #define SERDES_25G_LANE_DFE_REFCLK_EYE_VSCAN_CTRL1_POL_SHIFT 0 2717 2718 #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_MASK 0x1F 2719 #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_MAG_SHIFT 0 2720 2721 #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_MASK 0x80 2722 #define SERDES_25G_LANE_DFE_REFCLK_EYE_TAP1_CTRL0_POL_SHIFT 7 2723 2724 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_MASK 0x01 2725 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT 0 2726 2727 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_MASK 0x3E 2728 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT 1 2729 2730 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_MASK 0x40 2731 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_FINISH_SHIFT 6 2732 2733 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_MASK 0x80 2734 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT 7 2735 2736 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_MASK 0x0F 2737 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_NEXT_STATE_SHIFT 0 2738 2739 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_MASK 0x10 2740 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL1_CTRL_EN_SHIFT 4 2741 2742 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_MASK 0xFF 2743 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL2_WAIT_1_TIMER7_0_SHIFT 0 2744 2745 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_MASK 0x03 2746 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL3_WAIT_1_TIMER9_8_SHIFT 0 2747 2748 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_MASK 0xFF 2749 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL4_WAIT_2_TIMER7_0_SHIFT 0 2750 2751 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_MASK 0x03 2752 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL5_WAIT_2_TIMER9_8_SHIFT 0 2753 2754 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_MASK 0xFF 2755 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL6_TAP_DELAY_7_0_SHIFT 0 2756 2757 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_MASK 0x03 2758 #define SERDES_25G_LANE_DFE_REFCLK_FSM_CTRL7_TAP_DELAY_9_8_SHIFT 0 2759 2760 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_MASK 0x01 2761 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT 0 2762 2763 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_MASK 0x02 2764 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_SLICER_OFST_ACK_SHIFT 1 2765 2766 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_MASK 0x04 2767 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_ERR_FUNC_ACK_SHIFT 2 2768 2769 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_MASK 0x08 2770 #define SERDES_25G_LANE_DFE_REFCLK_FSM_STATUS0_AFE_DRV_ACK_SHIFT 3 2771 2772 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_MASK 0x01 2773 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT 0 2774 2775 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_MASK 0x02 2776 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT 1 2777 2778 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_MASK 0x04 2779 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT 2 2780 2781 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_MASK 0x08 2782 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT 3 2783 2784 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_MASK 0x10 2785 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT 4 2786 2787 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_MASK 0x20 2788 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT 5 2789 2790 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_MASK 0x40 2791 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT 6 2792 2793 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_MASK 0x80 2794 #define SERDES_25G_LANE_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT 7 2795 2796 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_MASK 0x1F 2797 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT 0 2798 2799 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK 0x80 2800 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT 7 2801 2802 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_MASK 0x1F 2803 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT 0 2804 2805 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK 0x80 2806 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT 7 2807 2808 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_MASK 0x1F 2809 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT 0 2810 2811 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK 0x80 2812 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT 7 2813 2814 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_MASK 0x1F 2815 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT 0 2816 2817 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK 0x80 2818 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT 7 2819 2820 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_MASK 0x0F 2821 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT 0 2822 2823 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_MASK 0x80 2824 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT 7 2825 2826 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_MASK 0x07 2827 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT 0 2828 2829 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_MASK 0x80 2830 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT 7 2831 2832 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_MASK 0x07 2833 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT 0 2834 2835 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_MASK 0x80 2836 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT 7 2837 2838 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_MASK 0x07 2839 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT 0 2840 2841 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_MASK 0x80 2842 #define SERDES_25G_LANE_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT 7 2843 2844 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_MASK 0x1F 2845 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT 0 2846 2847 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_MASK 0x80 2848 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT 7 2849 2850 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_MASK 0x1F 2851 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT 0 2852 2853 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_MASK 0x80 2854 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT 7 2855 2856 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_MASK 0x1F 2857 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT 0 2858 2859 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_MASK 0x80 2860 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT 7 2861 2862 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_MASK 0x1F 2863 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT 0 2864 2865 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_MASK 0x80 2866 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT 7 2867 2868 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_MASK 0x0F 2869 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT 0 2870 2871 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_MASK 0x80 2872 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT 7 2873 2874 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_MASK 0x07 2875 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT 0 2876 2877 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_MASK 0x80 2878 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT 7 2879 2880 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_MASK 0x07 2881 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT 0 2882 2883 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_MASK 0x80 2884 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT 7 2885 2886 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_MASK 0x07 2887 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT 0 2888 2889 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_MASK 0x80 2890 #define SERDES_25G_LANE_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT 7 2891 2892 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_MASK 0x1F 2893 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT 0 2894 2895 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_MASK 0x80 2896 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT 7 2897 2898 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_MASK 0x1F 2899 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT 0 2900 2901 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_MASK 0x80 2902 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT 7 2903 2904 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_MASK 0x1F 2905 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT 0 2906 2907 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_MASK 0x80 2908 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT 7 2909 2910 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_MASK 0x1F 2911 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT 0 2912 2913 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_MASK 0x80 2914 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT 7 2915 2916 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_MASK 0x0F 2917 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT 0 2918 2919 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_MASK 0x80 2920 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT 7 2921 2922 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_MASK 0x07 2923 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT 0 2924 2925 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_MASK 0x80 2926 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT 7 2927 2928 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_MASK 0x07 2929 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT 0 2930 2931 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_MASK 0x80 2932 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT 7 2933 2934 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_MASK 0x07 2935 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT 0 2936 2937 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_MASK 0x80 2938 #define SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT 7 2939 2940 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_MASK 0x01 2941 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN0_DATA_EN_SHIFT 0 2942 2943 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_MASK 0x02 2944 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN1_DATA_EN_SHIFT 1 2945 2946 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_MASK 0x04 2947 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD0_DATA_EN_SHIFT 2 2948 2949 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_MASK 0x08 2950 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD1_DATA_EN_SHIFT 3 2951 2952 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_MASK 0x10 2953 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EDGE_EN_SHIFT 4 2954 2955 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_MASK 0x20 2956 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EDGE_EN_SHIFT 5 2957 2958 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_MASK 0x40 2959 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_EVEN_EYE_EN_SHIFT 6 2960 2961 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_MASK 0x80 2962 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL0_ODD_EYE_EN_SHIFT 7 2963 2964 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_MASK 0x1F 2965 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL1_LIMIT_SHIFT 0 2966 2967 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_MASK 0x0F 2968 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_CTRL2_MAX_BOUNCES_SHIFT 0 2969 2970 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_MASK 0x3F 2971 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL0_EVEN0_DATA_SHIFT 0 2972 2973 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_MASK 0x3F 2974 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL1_EVEN1_DATA_SHIFT 0 2975 2976 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_MASK 0x3F 2977 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL2_ODD0_DATA_SHIFT 0 2978 2979 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_MASK 0x3F 2980 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL3_ODD1_DATA_SHIFT 0 2981 2982 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_MASK 0x3F 2983 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL4_EVEN_EDGE_SHIFT 0 2984 2985 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_MASK 0x3F 2986 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL5_ODD_EDGE_SHIFT 0 2987 2988 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_MASK 0x3F 2989 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL6_EVEN_EYE_SHIFT 0 2990 2991 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_MASK 0x3F 2992 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_VAL_CTRL7_ODD_EYE_SHIFT 0 2993 2994 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_MASK 0x3F 2995 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS0_EVEN0_DATA_SHIFT 0 2996 2997 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_MASK 0x3F 2998 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS1_EVEN1_DATA_SHIFT 0 2999 3000 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_MASK 0x3F 3001 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS2_ODD0_DATA_SHIFT 0 3002 3003 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_MASK 0x3F 3004 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS3_ODD1_DATA_SHIFT 0 3005 3006 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_MASK 0x3F 3007 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS4_EVEN_EDGE_SHIFT 0 3008 3009 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_MASK 0x3F 3010 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS5_ODD_EDGE_SHIFT 0 3011 3012 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_MASK 0x3F 3013 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS6_EVEN_EYE_SHIFT 0 3014 3015 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_MASK 0x3F 3016 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_VAL_STATUS7_ODD_EYE_SHIFT 0 3017 3018 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_MASK 0x01 3019 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN0_DATA_SHIFT 0 3020 3021 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_MASK 0x02 3022 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN1_DATA_SHIFT 1 3023 3024 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_MASK 0x04 3025 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD0_DATA_SHIFT 2 3026 3027 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_MASK 0x08 3028 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD1_DATA_SHIFT 3 3029 3030 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_MASK 0x10 3031 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EDGE_SHIFT 4 3032 3033 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_MASK 0x20 3034 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EDGE_SHIFT 5 3035 3036 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_MASK 0x40 3037 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_EVEN_EYE_SHIFT 6 3038 3039 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_MASK 0x80 3040 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_LOAD_SOURCE_CTRL0_ODD_EYE_SHIFT 7 3041 3042 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_MASK 0x01 3043 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_ERR_SHIFT 0 3044 3045 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_MASK 0x02 3046 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_INC_SHIFT 1 3047 3048 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_MASK 0x04 3049 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS0_DEC_SHIFT 2 3050 3051 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_MASK 0x01 3052 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN0_DATA_SHIFT 0 3053 3054 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_MASK 0x02 3055 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN1_DATA_SHIFT 1 3056 3057 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_MASK 0x04 3058 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD0_DATA_SHIFT 2 3059 3060 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_MASK 0x08 3061 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD1_DATA_SHIFT 3 3062 3063 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_MASK 0x10 3064 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EDGE_SHIFT 4 3065 3066 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_MASK 0x20 3067 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EDGE_SHIFT 5 3068 3069 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_MASK 0x40 3070 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_EVEN_EYE_SHIFT 6 3071 3072 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_MASK 0x80 3073 #define SERDES_25G_LANE_DFE_REFCLK_SLICER_OFST_STATUS1_ODD_EYE_SHIFT 7 3074 3075 /********************************** LOS REFCLK **********************************/ 3076 #define SERDES_25G_LANE_LOS_REFCLK_BASE 0x500 3077 3078 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x00) 3079 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x01) 3080 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x02) 3081 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x10) 3082 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x11) 3083 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x12) 3084 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x13) 3085 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x14) 3086 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x15) 3087 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x16) 3088 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x20) 3089 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x21) 3090 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x22) 3091 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x23) 3092 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x24) 3093 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x30) 3094 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x31) 3095 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x32) 3096 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x33) 3097 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x40) 3098 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x41) 3099 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x42) 3100 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x43) 3101 #define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x46) 3102 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x51) 3103 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x59) 3104 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x60) 3105 #define SERDES_25G_LANE_LOS_REFCLK_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x70) 3106 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x71) 3107 #define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x72) 3108 #define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_ADDR (SERDES_25G_LANE_LOS_REFCLK_BASE + 0x73) 3109 /******************************************************************************* 3110 * masks and shifts 3111 ******************************************************************************/ 3112 3113 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_MASK 0x01 3114 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT 0 3115 3116 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_MASK 0xFF 3117 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_CTRL1_ASSERT_THRESHOLD_SHIFT 0 3118 3119 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_MASK 0x01 3120 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT 0 3121 3122 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_MASK 0x02 3123 #define SERDES_25G_LANE_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT 1 3124 3125 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_MASK 0xFF 3126 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL0_ASSERT_THRESHOLD_7_0_SHIFT 0 3127 3128 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_MASK 0xFF 3129 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL1_ASSERT_THRESHOLD_15_8_SHIFT 0 3130 3131 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_MASK 0xFF 3132 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL2_DEASSERT_THRESHOLD_7_0_SHIFT 0 3133 3134 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_MASK 0xFF 3135 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL3_DEASSERT_THRESHOLD_15_8_SHIFT 0 3136 3137 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_MASK 0xFF 3138 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL4_DEASSERT_THRESHOLD_23_16_SHIFT 0 3139 3140 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_MASK 0x03 3141 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT 0 3142 3143 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_MASK 0x01 3144 #define SERDES_25G_LANE_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT 0 3145 3146 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_MASK 0x01 3147 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL0_EN_SHIFT 0 3148 3149 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_MASK 0xFF 3150 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL1_PERIOD_7_0_SHIFT 0 3151 3152 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_MASK 0xFF 3153 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL2_PERIOD_15_8_SHIFT 0 3154 3155 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_MASK 0xFF 3156 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL3_PERIOD_23_16_SHIFT 0 3157 3158 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_MASK 0x03 3159 #define SERDES_25G_LANE_LOS_REFCLK_TIMED_MODE_CTRL4_PERIOD_25_24_SHIFT 0 3160 3161 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_MASK 0x01 3162 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT 0 3163 3164 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_MASK 0x10 3165 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT 4 3166 3167 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_MASK 0x01 3168 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_EN_SHIFT 0 3169 3170 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_MASK 0x10 3171 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL1_LOS_I_VALUE_SHIFT 4 3172 3173 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_MASK 0x3F 3174 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_VALUE_SHIFT 0 3175 3176 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_MASK 0x40 3177 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL2_LOS_OFFSET_EN_SHIFT 6 3178 3179 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_MASK 0x3F 3180 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_VALUE_SHIFT 0 3181 3182 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_MASK 0x40 3183 #define SERDES_25G_LANE_LOS_REFCLK_OVERRIDE_CTRL3_AGC_OFFSET_EN_SHIFT 6 3184 3185 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_MASK 0x01 3186 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_BANDWIDTH_SHIFT 0 3187 3188 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_MASK 0x0E 3189 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_HYSTERESIS_SHIFT 1 3190 3191 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_MASK 0x10 3192 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL0_ENVDET_BYP_SHIFT 4 3193 3194 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_MASK 0x01 3195 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_GAIN_SHIFT 0 3196 3197 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_MASK 0x02 3198 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_LOS_INVERT_SHIFT 1 3199 3200 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_MASK 0x04 3201 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_AGC_INVERT_SHIFT 2 3202 3203 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_MASK 0x78 3204 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL1_THRESHOLD_SHIFT 3 3205 3206 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_MASK 0xFF 3207 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL2_MODE_SWITCH_WAIT_7_0_SHIFT 0 3208 3209 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_MASK 0xFF 3210 #define SERDES_25G_LANE_LOS_REFCLK_COMPARATOR_CTRL3_MODE_SWITCH_WAIT_15_8_SHIFT 0 3211 3212 #define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_MASK 0x01 3213 #define SERDES_25G_LANE_LOS_REFCLK_EYE_CTRL_EYE_DATA_PARITY_SHIFT 0 3214 3215 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_MASK 0x01 3216 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_EN_SHIFT 0 3217 3218 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_MASK 0x02 3219 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL0_MODE_SHIFT 1 3220 3221 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_MASK 0x3F 3222 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_LOS_OFFSET_SHIFT 0 3223 3224 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_MASK 0x40 3225 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_AGC_CALIB_DONE_SHIFT 6 3226 3227 #define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_MASK 0x01 3228 #define SERDES_25G_LANE_LOS_REFCLK_CTRL0_EN_SHIFT 0 3229 3230 #define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_MASK 0x02 3231 #define SERDES_25G_LANE_FEATURE_CTRL0_SRC_SELECT_SHIFT 1 3232 3233 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_MASK 0x01 3234 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_READY_SHIFT 0 3235 3236 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_MASK 0x02 3237 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_READY_SHIFT 1 3238 3239 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_MASK 0x04 3240 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_SHIFT 2 3241 3242 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_MASK 0x08 3243 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT 3 3244 3245 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_MASK 0x10 3246 #define SERDES_25G_LANE_LOS_REFCLK_STATUS0_AGC_SHIFT 4 3247 3248 #define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_MASK 0x0F 3249 #define SERDES_25G_LANE_LOS_REFCLK_AFE_SPARE_CTRL0_RXLOS_SPARE_SHIFT 0 3250 3251 #define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_MASK 0x01 3252 #define SERDES_25G_LANE_LOS_REFCLK_AFE_PD_CTRL0_PD_RXLOS_SHIFT 0 3253 3254 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_MASK 0x01 3255 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_CTRL6_REQ_SHIFT 0 3256 3257 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_MASK 0x01 3258 #define SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS2_ACK_SHIFT 0 3259 3260 /********************************** GCFSM2 **********************************/ 3261 #define SERDES_25G_LANE_GCFSM2_BASE 0x580 3262 3263 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x00) 3264 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x01) 3265 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x02) 3266 #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x03) 3267 #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x10) 3268 #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x11) 3269 #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x12) 3270 #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x13) 3271 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x20) 3272 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x21) 3273 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x22) 3274 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x23) 3275 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x24) 3276 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x25) 3277 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x26) 3278 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x30) 3279 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x31) 3280 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x32) 3281 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x40) 3282 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x41) 3283 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x42) 3284 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x43) 3285 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x44) 3286 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x45) 3287 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x46) 3288 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x47) 3289 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x48) 3290 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x50) 3291 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_ADDR (SERDES_25G_LANE_GCFSM2_BASE + 0x51) 3292 /******************************************************************************* 3293 * masks and shifts 3294 ******************************************************************************/ 3295 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK 0x01 3296 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT 0 3297 3298 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_MASK 0x07 3299 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_SHIFT 0 3300 3301 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_MASK 0xFF 3302 #define SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR_SHIFT 0 3303 3304 #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_MASK 0x01 3305 #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_SHIFT 0 3306 3307 #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_MASK 0x1E 3308 #define SERDES_25G_LANE_GCFSM2_CMD_STATUS_CODE_SHIFT 1 3309 3310 #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_MASK 0xFF 3311 #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_7_0_SHIFT 0 3312 3313 #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_MASK 0x0F 3314 #define SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_SHIFT 0 3315 3316 #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_MASK 0xFF 3317 #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS0_7_0_SHIFT 0 3318 3319 #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_MASK 0x01 3320 #define SERDES_25G_LANE_GCFSM2_AVG_UP_CNT_STATUS1_8_8_SHIFT 0 3321 3322 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_MASK 0x03 3323 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_TYPE_SHIFT 0 3324 3325 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_MASK 0x3C 3326 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL0_WIDTH_SHIFT 2 3327 3328 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_MASK 0xFF 3329 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL1_START_7_0_SHIFT 0 3330 3331 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_MASK 0x0F 3332 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL2_START_11_8_SHIFT 0 3333 3334 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_MASK 0xFF 3335 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL3_MIN_7_0_SHIFT 0 3336 3337 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_MASK 0x0F 3338 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL4_MIN_11_8_SHIFT 0 3339 3340 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_MASK 0xFF 3341 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL5_MAX_7_0_SHIFT 0 3342 3343 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_MASK 0x0F 3344 #define SERDES_25G_LANE_GCFSM2_DATA_CTRL6_MAX_11_8_SHIFT 0 3345 3346 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_MASK 0x1F 3347 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL0_STEP_SIZE_SHIFT 0 3348 3349 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_MASK 0x0F 3350 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_BOUNCE_NUM_SHIFT 0 3351 3352 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_MASK 0xF0 3353 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL1_COARSE_BOUNCE_NUM_SHIFT 4 3354 3355 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_MASK 0x01 3356 #define SERDES_25G_LANE_GCFSM2_PARAMETER_CTRL2_SETTLE_ON_LOWEST_AVG_EN_SHIFT 0 3357 3358 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_MASK 0x03 3359 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL0_LEN_DELAY_AFE_EN_SHIFT 0 3360 3361 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_MASK 0xFF 3362 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL1_LEN_AFE_1ST_LATCH_SETTLE_7_0_SHIFT 0 3363 3364 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_MASK 0xFF 3365 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL2_LEN_AFE_1ST_LATCH_SETTLE_15_8_SHIFT 0 3366 3367 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_MASK 0xFF 3368 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL3_LEN_AFE_LATCH_SETTLE_SHIFT 0 3369 3370 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_MASK 0xFF 3371 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL4_LEN_AFE_CMP_7_0_SHIFT 0 3372 3373 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_MASK 0xFF 3374 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL5_LEN_AFE_CMP_15_8_SHIFT 0 3375 3376 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_MASK 0xFF 3377 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL6_LEN_COARSE_BOUNCE_AFE_CMP_7_0_SHIFT 0 3378 3379 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_MASK 0xFF 3380 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL7_LEN_COARSE_BOUNCE_AFE_CMP_15_8_SHIFT 0 3381 3382 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_MASK 0x01 3383 #define SERDES_25G_LANE_GCFSM2_WAIT_CTRL8_WAIT_MODE_SHIFT 0 3384 3385 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_MASK 0x01 3386 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_INVERT_AFE_UP_SHIFT 0 3387 3388 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_MASK 0x1E 3389 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL0_LEN_WAIT_AFE_UP_SHIFT 1 3390 3391 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_MASK 0xFF 3392 #define SERDES_25G_LANE_GCFSM2_FEEDBACK_CTRL1_LEN_AVG_AFE_UP_SHIFT 0 3393 3394 /********************************** TX BIST **********************************/ 3395 #define SERDES_25G_LANE_TX_BIST_BASE 0x600 3396 3397 #define SERDES_25G_LANE_TX_BIST_CTRL_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x00) 3398 #define SERDES_25G_LANE_TX_BIST_BER_CTRL0_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x04) 3399 #define SERDES_25G_LANE_TX_BIST_BER_CTRL1_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x05) 3400 #define SERDES_25G_LANE_TX_BIST_BER_CTRL2_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x06) 3401 #define SERDES_25G_LANE_TX_BIST_BER_CTRL3_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x07) 3402 #define SERDES_25G_LANE_TX_BIST_BER_CTRL4_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x08) 3403 #define SERDES_25G_LANE_TX_BIST_BER_CTRL5_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x09) 3404 #define SERDES_25G_LANE_TX_BIST_BER_CTRL6_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x0A) 3405 #define SERDES_25G_LANE_TX_BIST_BER_CTRL7_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x0B) 3406 #define SERDES_25G_LANE_TX_BIST_UDP_SHIFT_AMOUNT_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x20) 3407 #define SERDES_25G_LANE_TX_BIST_UDP_ADDR(byte_num) \ 3408 ((SERDES_25G_LANE_TX_BIST_BASE + 0x24) + byte_num) 3409 #define SERDES_25G_LANE_TX_BIST_UDP_NUM_BYTES 20 3410 #define SERDES_25G_LANE_TX_BIST_UDP_7_0_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x24) 3411 #define SERDES_25G_LANE_TX_BIST_UDP_15_8_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x25) 3412 #define SERDES_25G_LANE_TX_BIST_UDP_23_16_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x26) 3413 #define SERDES_25G_LANE_TX_BIST_UDP_31_24_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x27) 3414 #define SERDES_25G_LANE_TX_BIST_UDP_39_32_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x28) 3415 #define SERDES_25G_LANE_TX_BIST_UDP_47_40_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x29) 3416 #define SERDES_25G_LANE_TX_BIST_UDP_55_48_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2A) 3417 #define SERDES_25G_LANE_TX_BIST_UDP_63_56_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2B) 3418 #define SERDES_25G_LANE_TX_BIST_UDP_71_64_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2C) 3419 #define SERDES_25G_LANE_TX_BIST_UDP_79_72_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2D) 3420 #define SERDES_25G_LANE_TX_BIST_UDP_87_80_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2E) 3421 #define SERDES_25G_LANE_TX_BIST_UDP_95_88_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x2F) 3422 #define SERDES_25G_LANE_TX_BIST_UDP_103_96_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x30) 3423 #define SERDES_25G_LANE_TX_BIST_UDP_111_104_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x31) 3424 #define SERDES_25G_LANE_TX_BIST_UDP_119_112_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x32) 3425 #define SERDES_25G_LANE_TX_BIST_UDP_127_120_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x33) 3426 #define SERDES_25G_LANE_TX_BIST_UDP_135_128_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x34) 3427 #define SERDES_25G_LANE_TX_BIST_UDP_143_136_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x35) 3428 #define SERDES_25G_LANE_TX_BIST_UDP_151_144_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x36) 3429 #define SERDES_25G_LANE_TX_BIST_UDP_159_152_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x37) 3430 #define SERDES_25G_LANE_TX_BIST_UDP_167_160_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x38) 3431 #define SERDES_25G_LANE_TX_BIST_UDP_175_168_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x39) 3432 #define SERDES_25G_LANE_TX_BIST_UDP_183_176_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3A) 3433 #define SERDES_25G_LANE_TX_BIST_UDP_191_184_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3B) 3434 #define SERDES_25G_LANE_TX_BIST_UDP_199_192_ADDR (SERDES_25G_LANE_TX_BIST_BASE + 0x3C) 3435 3436 #define SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK 0x01 3437 #define SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT 0 3438 3439 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_MASK 0x1E 3440 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_SHIFT 1 3441 3442 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS7 1 3443 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS9 2 3444 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS11 3 3445 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS15 4 3446 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS23 5 3447 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS31 6 3448 #define SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS_USER 7 3449 3450 #define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_MASK 0x03 3451 #define SERDES_25G_LANE_TX_BIST_BER_CTRL0_MODE_SHIFT 0 3452 3453 #define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_MASK 0xFF 3454 #define SERDES_25G_LANE_TX_BIST_BER_CTRL1_TIMER_7_0_SHIFT 0 3455 3456 #define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_MASK 0xFF 3457 #define SERDES_25G_LANE_TX_BIST_BER_CTRL2_TIMER_15_8_SHIFT 0 3458 3459 #define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_MASK 0xFF 3460 #define SERDES_25G_LANE_TX_BIST_BER_CTRL3_BIT_ERROR_FIELD_7_0_SHIFT 0 3461 3462 #define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_MASK 0xFF 3463 #define SERDES_25G_LANE_TX_BIST_BER_CTRL4_BIT_ERROR_FIELD_15_8_SHIFT 0 3464 3465 #define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_MASK 0xFF 3466 #define SERDES_25G_LANE_TX_BIST_BER_CTRL5_BIT_ERROR_FIELD_23_16_SHIFT 0 3467 3468 #define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_MASK 0xFF 3469 #define SERDES_25G_LANE_TX_BIST_BER_CTRL6_BIT_ERROR_FIELD_31_24_SHIFT 0 3470 3471 #define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_MASK 0xFF 3472 #define SERDES_25G_LANE_TX_BIST_BER_CTRL7_BIT_ERROR_FIELD_39_32_SHIFT 0 3473 3474 #define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_MASK 0xFF 3475 #define SERDES_25G_LANE_TX_BIST_SHIFT_AMOUNT_SHIFT 0 3476 3477 #define SERDES_25G_LANE_TX_BIST_UDP_7_0_MASK 0xFF 3478 #define SERDES_25G_LANE_TX_BIST_UDP_7_0_SHIFT 0 3479 3480 #define SERDES_25G_LANE_TX_BIST_UDP_15_8_MASK 0xFF 3481 #define SERDES_25G_LANE_TX_BIST_UDP_15_8_SHIFT 0 3482 3483 #define SERDES_25G_LANE_TX_BIST_UDP_23_16_MASK 0xFF 3484 #define SERDES_25G_LANE_TX_BIST_UDP_23_16_SHIFT 0 3485 3486 #define SERDES_25G_LANE_TX_BIST_UDP_31_24_MASK 0xFF 3487 #define SERDES_25G_LANE_TX_BIST_UDP_31_24_SHIFT 0 3488 3489 #define SERDES_25G_LANE_TX_BIST_UDP_39_32_MASK 0xFF 3490 #define SERDES_25G_LANE_TX_BIST_UDP_39_32_SHIFT 0 3491 3492 #define SERDES_25G_LANE_TX_BIST_UDP_47_40_MASK 0xFF 3493 #define SERDES_25G_LANE_TX_BIST_UDP_47_40_SHIFT 0 3494 3495 #define SERDES_25G_LANE_TX_BIST_UDP_55_48_MASK 0xFF 3496 #define SERDES_25G_LANE_TX_BIST_UDP_55_48_SHIFT 0 3497 3498 #define SERDES_25G_LANE_TX_BIST_UDP_63_56_MASK 0xFF 3499 #define SERDES_25G_LANE_TX_BIST_UDP_63_56_SHIFT 0 3500 3501 #define SERDES_25G_LANE_TX_BIST_UDP_71_64_MASK 0xFF 3502 #define SERDES_25G_LANE_TX_BIST_UDP_71_64_SHIFT 0 3503 3504 #define SERDES_25G_LANE_TX_BIST_UDP_79_72_MASK 0xFF 3505 #define SERDES_25G_LANE_TX_BIST_UDP_79_72_SHIFT 0 3506 3507 #define SERDES_25G_LANE_TX_BIST_UDP_87_80_MASK 0xFF 3508 #define SERDES_25G_LANE_TX_BIST_UDP_87_80_SHIFT 0 3509 3510 #define SERDES_25G_LANE_TX_BIST_UDP_95_88_MASK 0xFF 3511 #define SERDES_25G_LANE_TX_BIST_UDP_95_88_SHIFT 0 3512 3513 #define SERDES_25G_LANE_TX_BIST_UDP_103_96_MASK 0xFF 3514 #define SERDES_25G_LANE_TX_BIST_UDP_103_96_SHIFT 0 3515 3516 #define SERDES_25G_LANE_TX_BIST_UDP_111_104_MASK 0xFF 3517 #define SERDES_25G_LANE_TX_BIST_UDP_111_104_SHIFT 0 3518 3519 #define SERDES_25G_LANE_TX_BIST_UDP_119_112_MASK 0xFF 3520 #define SERDES_25G_LANE_TX_BIST_UDP_119_112_SHIFT 0 3521 3522 #define SERDES_25G_LANE_TX_BIST_UDP_127_120_MASK 0xFF 3523 #define SERDES_25G_LANE_TX_BIST_UDP_127_120_SHIFT 0 3524 3525 #define SERDES_25G_LANE_TX_BIST_UDP_135_128_MASK 0xFF 3526 #define SERDES_25G_LANE_TX_BIST_UDP_135_128_SHIFT 0 3527 3528 #define SERDES_25G_LANE_TX_BIST_UDP_143_136_MASK 0xFF 3529 #define SERDES_25G_LANE_TX_BIST_UDP_143_136_SHIFT 0 3530 3531 #define SERDES_25G_LANE_TX_BIST_UDP_151_144_MASK 0xFF 3532 #define SERDES_25G_LANE_TX_BIST_UDP_151_144_SHIFT 0 3533 3534 #define SERDES_25G_LANE_TX_BIST_UDP_159_152_MASK 0xFF 3535 #define SERDES_25G_LANE_TX_BIST_UDP_159_152_SHIFT 0 3536 3537 #define SERDES_25G_LANE_TX_BIST_UDP_167_160_MASK 0xFF 3538 #define SERDES_25G_LANE_TX_BIST_UDP_167_160_SHIFT 0 3539 3540 #define SERDES_25G_LANE_TX_BIST_UDP_175_168_MASK 0xFF 3541 #define SERDES_25G_LANE_TX_BIST_UDP_175_168_SHIFT 0 3542 3543 #define SERDES_25G_LANE_TX_BIST_UDP_183_176_MASK 0xFF 3544 #define SERDES_25G_LANE_TX_BIST_UDP_183_176_SHIFT 0 3545 3546 #define SERDES_25G_LANE_TX_BIST_UDP_191_184_MASK 0xFF 3547 #define SERDES_25G_LANE_TX_BIST_UDP_191_184_SHIFT 0 3548 3549 #define SERDES_25G_LANE_TX_BIST_UDP_199_192_MASK 0xFF 3550 #define SERDES_25G_LANE_TX_BIST_UDP_199_192_SHIFT 0 3551 3552 /********************************** RX BIST **********************************/ 3553 #define SERDES_25G_LANE_RX_BIST_BASE 0x680 3554 3555 #define SERDES_25G_LANE_RX_BIST_CTRL_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x00) 3556 #define SERDES_25G_LANE_RX_BIST_STATUS_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x04) 3557 #define SERDES_25G_LANE_RX_BIST_BER_STATUS0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x08) 3558 #define SERDES_25G_LANE_RX_BIST_BER_STATUS1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x09) 3559 #define SERDES_25G_LANE_RX_BIST_BER_STATUS2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0A) 3560 #define SERDES_25G_LANE_RX_BIST_BER_STATUS4_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0C) 3561 #define SERDES_25G_LANE_RX_BIST_BER_STATUS5_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0D) 3562 #define SERDES_25G_LANE_RX_BIST_BER_STATUS6_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x0E) 3563 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x14) 3564 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x15) 3565 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x16) 3566 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x17) 3567 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x20) 3568 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x21) 3569 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x22) 3570 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x23) 3571 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x24) 3572 #define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x30) 3573 #define SERDES_25G_LANE_RX_BIST_UDP_7_0_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x34) 3574 #define SERDES_25G_LANE_RX_BIST_UDP_15_8_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x35) 3575 #define SERDES_25G_LANE_RX_BIST_UDP_23_16_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x36) 3576 #define SERDES_25G_LANE_RX_BIST_UDP_31_24_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x37) 3577 #define SERDES_25G_LANE_RX_BIST_UDP_39_32_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x38) 3578 #define SERDES_25G_LANE_RX_BIST_UDP_47_40_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x39) 3579 #define SERDES_25G_LANE_RX_BIST_UDP_55_48_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3A) 3580 #define SERDES_25G_LANE_RX_BIST_UDP_63_56_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3B) 3581 #define SERDES_25G_LANE_RX_BIST_UDP_71_64_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3C) 3582 #define SERDES_25G_LANE_RX_BIST_UDP_79_72_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3D) 3583 #define SERDES_25G_LANE_RX_BIST_UDP_87_80_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3E) 3584 #define SERDES_25G_LANE_RX_BIST_UDP_95_88_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x3F) 3585 #define SERDES_25G_LANE_RX_BIST_UDP_103_96_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x40) 3586 #define SERDES_25G_LANE_RX_BIST_UDP_111_104_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x41) 3587 #define SERDES_25G_LANE_RX_BIST_UDP_119_112_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x42) 3588 #define SERDES_25G_LANE_RX_BIST_UDP_127_120_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x43) 3589 #define SERDES_25G_LANE_RX_BIST_UDP_135_128_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x44) 3590 #define SERDES_25G_LANE_RX_BIST_UDP_143_136_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x45) 3591 #define SERDES_25G_LANE_RX_BIST_UDP_151_144_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x46) 3592 #define SERDES_25G_LANE_RX_BIST_UDP_159_152_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x47) 3593 #define SERDES_25G_LANE_RX_BIST_UDP_167_160_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x48) 3594 #define SERDES_25G_LANE_RX_BIST_UDP_175_168_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x49) 3595 #define SERDES_25G_LANE_RX_BIST_UDP_183_176_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4A) 3596 #define SERDES_25G_LANE_RX_BIST_UDP_191_184_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4B) 3597 #define SERDES_25G_LANE_RX_BIST_UDP_199_192_ADDR (SERDES_25G_LANE_RX_BIST_BASE + 0x4C) 3598 3599 /******************************************************************************* 3600 * masks and shifts 3601 ******************************************************************************/ 3602 #define SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK 0x01 3603 #define SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT 0 3604 3605 #define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_MASK 0x1E 3606 #define SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_SHIFT 1 3607 3608 #define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK 0x20 3609 #define SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT 5 3610 3611 #define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_MASK 0x40 3612 #define SERDES_25G_LANE_RX_BIST_CTRL_STOP_ERROR_COUNT_SHIFT 6 3613 3614 #define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_MASK 0x80 3615 #define SERDES_25G_LANE_RX_BIST_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT 7 3616 3617 #define SERDES_25G_LANE_RX_BIST_STATUS_STATE_MASK 0x07 3618 #define SERDES_25G_LANE_RX_BIST_STATUS_STATE_SHIFT 0 3619 3620 #define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_MASK 0x78 3621 #define SERDES_25G_LANE_RX_BIST_STATUS_PATTERN_DET_SHIFT 3 3622 3623 #define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_MASK 0xFF 3624 #define SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_SHIFT 0 3625 3626 #define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_MASK 0xFF 3627 #define SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_SHIFT 0 3628 3629 #define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_MASK 0xFF 3630 #define SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_SHIFT 0 3631 3632 #define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_MASK 0xFF 3633 #define SERDES_25G_LANE_RX_BIST_BER_STATUS4_CYCLE_COUNT_7_0_SHIFT 0 3634 3635 #define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_MASK 0xFF 3636 #define SERDES_25G_LANE_RX_BIST_BER_STATUS5_CYCLE_COUNT_15_8_SHIFT 0 3637 3638 #define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_MASK 0xFF 3639 #define SERDES_25G_LANE_RX_BIST_BER_STATUS6_CYCLE_COUNT_23_16_SHIFT 0 3640 3641 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_MASK 0xFF 3642 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT 0 3643 3644 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_MASK 0xFF 3645 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT 0 3646 3647 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_MASK 0xFF 3648 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL2_MAX_ERRORS_7_0_SHIFT 0 3649 3650 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_MASK 0xFF 3651 #define SERDES_25G_LANE_RX_BIST_LOCK_CTRL3_MAX_ERRORS_15_8_SHIFT 0 3652 3653 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_MASK 0xFF 3654 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL0_NUM_CYCLES_7_0_SHIFT 0 3655 3656 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_MASK 0xFF 3657 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL1_NUM_CYCLES_15_8_SHIFT 0 3658 3659 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_MASK 0xFF 3660 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL2_MIN_ERRORS_7_0_SHIFT 0 3661 3662 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_MASK 0xFF 3663 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL3_MIN_ERRORS_15_8_SHIFT 0 3664 3665 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_MASK 0x01 3666 #define SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT 0 3667 3668 #define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_MASK 0xFF 3669 #define SERDES_25G_LANE_RX_BIST_SHIFT_AMOUNT_SHIFT 0 3670 3671 #define SERDES_25G_LANE_RX_BIST_UDP_7_0_MASK 0xFF 3672 #define SERDES_25G_LANE_RX_BIST_UDP_7_0_SHIFT 0 3673 3674 #define SERDES_25G_LANE_RX_BIST_UDP_15_8_MASK 0xFF 3675 #define SERDES_25G_LANE_RX_BIST_UDP_15_8_SHIFT 0 3676 3677 #define SERDES_25G_LANE_RX_BIST_UDP_23_16_MASK 0xFF 3678 #define SERDES_25G_LANE_RX_BIST_UDP_23_16_SHIFT 0 3679 3680 #define SERDES_25G_LANE_RX_BIST_UDP_31_24_MASK 0xFF 3681 #define SERDES_25G_LANE_RX_BIST_UDP_31_24_SHIFT 0 3682 3683 #define SERDES_25G_LANE_RX_BIST_UDP_39_32_MASK 0xFF 3684 #define SERDES_25G_LANE_RX_BIST_UDP_39_32_SHIFT 0 3685 3686 #define SERDES_25G_LANE_RX_BIST_UDP_47_40_MASK 0xFF 3687 #define SERDES_25G_LANE_RX_BIST_UDP_47_40_SHIFT 0 3688 3689 #define SERDES_25G_LANE_RX_BIST_UDP_55_48_MASK 0xFF 3690 #define SERDES_25G_LANE_RX_BIST_UDP_55_48_SHIFT 0 3691 3692 #define SERDES_25G_LANE_RX_BIST_UDP_63_56_MASK 0xFF 3693 #define SERDES_25G_LANE_RX_BIST_UDP_63_56_SHIFT 0 3694 3695 #define SERDES_25G_LANE_RX_BIST_UDP_71_64_MASK 0xFF 3696 #define SERDES_25G_LANE_RX_BIST_UDP_71_64_SHIFT 0 3697 3698 #define SERDES_25G_LANE_RX_BIST_UDP_79_72_MASK 0xFF 3699 #define SERDES_25G_LANE_RX_BIST_UDP_79_72_SHIFT 0 3700 3701 #define SERDES_25G_LANE_RX_BIST_UDP_87_80_MASK 0xFF 3702 #define SERDES_25G_LANE_RX_BIST_UDP_87_80_SHIFT 0 3703 3704 #define SERDES_25G_LANE_RX_BIST_UDP_95_88_MASK 0xFF 3705 #define SERDES_25G_LANE_RX_BIST_UDP_95_88_SHIFT 0 3706 3707 #define SERDES_25G_LANE_RX_BIST_UDP_103_96_MASK 0xFF 3708 #define SERDES_25G_LANE_RX_BIST_UDP_103_96_SHIFT 0 3709 3710 #define SERDES_25G_LANE_RX_BIST_UDP_111_104_MASK 0xFF 3711 #define SERDES_25G_LANE_RX_BIST_UDP_111_104_SHIFT 0 3712 3713 #define SERDES_25G_LANE_RX_BIST_UDP_119_112_MASK 0xFF 3714 #define SERDES_25G_LANE_RX_BIST_UDP_119_112_SHIFT 0 3715 3716 #define SERDES_25G_LANE_RX_BIST_UDP_127_120_MASK 0xFF 3717 #define SERDES_25G_LANE_RX_BIST_UDP_127_120_SHIFT 0 3718 3719 #define SERDES_25G_LANE_RX_BIST_UDP_135_128_MASK 0xFF 3720 #define SERDES_25G_LANE_RX_BIST_UDP_135_128_SHIFT 0 3721 3722 #define SERDES_25G_LANE_RX_BIST_UDP_143_136_MASK 0xFF 3723 #define SERDES_25G_LANE_RX_BIST_UDP_143_136_SHIFT 0 3724 3725 #define SERDES_25G_LANE_RX_BIST_UDP_151_144_MASK 0xFF 3726 #define SERDES_25G_LANE_RX_BIST_UDP_151_144_SHIFT 0 3727 3728 #define SERDES_25G_LANE_RX_BIST_UDP_159_152_MASK 0xFF 3729 #define SERDES_25G_LANE_RX_BIST_UDP_159_152_SHIFT 0 3730 3731 #define SERDES_25G_LANE_RX_BIST_UDP_167_160_MASK 0xFF 3732 #define SERDES_25G_LANE_RX_BIST_UDP_167_160_SHIFT 0 3733 3734 #define SERDES_25G_LANE_RX_BIST_UDP_175_168_MASK 0xFF 3735 #define SERDES_25G_LANE_RX_BIST_UDP_175_168_SHIFT 0 3736 3737 #define SERDES_25G_LANE_RX_BIST_UDP_183_176_MASK 0xFF 3738 #define SERDES_25G_LANE_RX_BIST_UDP_183_176_SHIFT 0 3739 3740 #define SERDES_25G_LANE_RX_BIST_UDP_191_184_MASK 0xFF 3741 #define SERDES_25G_LANE_RX_BIST_UDP_191_184_SHIFT 0 3742 3743 #define SERDES_25G_LANE_RX_BIST_UDP_199_192_MASK 0xFF 3744 #define SERDES_25G_LANE_RX_BIST_UDP_199_192_SHIFT 0 3745 3746 /*********************************** FEATURE **********************************/ 3747 #define SERDES_25G_LANE_FEATURE_BASE 0x700 3748 3749 #define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x00) 3750 #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x04) 3751 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x05) 3752 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x06) 3753 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x07) 3754 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x08) 3755 #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x09) 3756 #define SERDES_25G_LANE_FEATURE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x0C) 3757 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x10) 3758 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x11) 3759 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x12) 3760 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x13) 3761 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x14) 3762 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x15) 3763 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x16) 3764 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x17) 3765 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x18) 3766 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x19) 3767 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1A) 3768 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1B) 3769 #define SERDES_25G_LANE_FEATURE_DFE_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x1F) 3770 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x20) 3771 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x21) 3772 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x22) 3773 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x23) 3774 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x24) 3775 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x25) 3776 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x26) 3777 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x27) 3778 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x28) 3779 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x30) 3780 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x31) 3781 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x32) 3782 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x33) 3783 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x40) 3784 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x41) 3785 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x42) 3786 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x43) 3787 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x44) 3788 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x45) 3789 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x46) 3790 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x47) 3791 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x48) 3792 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x49) 3793 #define SERDES_25G_LANE_FEATURE_TEST_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x50) 3794 #define SERDES_25G_LANE_FEATURE_SPARE_CFG0_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x58) 3795 #define SERDES_25G_LANE_FEATURE_SPARE_CFG1_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x59) 3796 #define SERDES_25G_LANE_FEATURE_SPARE_CFG2_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5A) 3797 #define SERDES_25G_LANE_FEATURE_SPARE_CFG3_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5B) 3798 #define SERDES_25G_LANE_FEATURE_SPARE_CFG4_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5C) 3799 #define SERDES_25G_LANE_FEATURE_SPARE_CFG5_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5D) 3800 #define SERDES_25G_LANE_FEATURE_SPARE_CFG6_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5E) 3801 #define SERDES_25G_LANE_FEATURE_SPARE_CFG7_ADDR (SERDES_25G_LANE_FEATURE_BASE + 0x5F) 3802 /******************************************************************************* 3803 * masks and shifts 3804 ******************************************************************************/ 3805 #define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_MASK 0x01 3806 #define SERDES_25G_LANE_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT 0 3807 3808 #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_MASK 0x01 3809 #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_LOS_COMP_EN_SHIFT 0 3810 3811 #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_MASK 0x02 3812 #define SERDES_25G_LANE_FEATURE_LOS_CAL_CFG0_AGC_COMP_EN_SHIFT 1 3813 3814 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_MASK 0x01 3815 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_GN_EN_SHIFT 0 3816 3817 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_MASK 0x02 3818 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ1_EN_SHIFT 1 3819 3820 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_MASK 0x04 3821 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ2_EN_SHIFT 2 3822 3823 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_MASK 0x08 3824 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ3_EN_SHIFT 3 3825 3826 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_MASK 0x10 3827 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ4_EN_SHIFT 4 3828 3829 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_MASK 0x20 3830 #define SERDES_25G_LANE_FEATURE_LEQ_OFFSET_CAL_CFG0_EQ5_EN_SHIFT 5 3831 3832 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_MASK 0x01 3833 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMODD_EN_SHIFT 0 3834 3835 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_MASK 0x02 3836 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_SUMMEVEN_EN_SHIFT 1 3837 3838 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_MASK 0x04 3839 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANODD_EN_SHIFT 2 3840 3841 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_MASK 0x08 3842 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG0_VSCANEVEN_EN_SHIFT 3 3843 3844 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_MASK 0x01 3845 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN1_EN_SHIFT 0 3846 3847 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_MASK 0x02 3848 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICEREVEN0_EN_SHIFT 1 3849 3850 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_MASK 0x04 3851 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD1_EN_SHIFT 2 3852 3853 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_MASK 0x08 3854 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_DATASLICERODD0_EN_SHIFT 3 3855 3856 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_MASK 0x10 3857 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICEREVEN_EN_SHIFT 4 3858 3859 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_MASK 0x20 3860 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EDGESLICERODD_EN_SHIFT 5 3861 3862 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_MASK 0x40 3863 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICEREVEN_EN_SHIFT 6 3864 3865 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_MASK 0x80 3866 #define SERDES_25G_LANE_FEATURE_DFE_OFFSET_CAL_CFG1_EYESLICERODD_EN_SHIFT 7 3867 3868 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_MASK 0x01 3869 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_VCO_FREQ_EN_SHIFT 0 3870 3871 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_MASK 0x02 3872 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL1_EN_SHIFT 1 3873 3874 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_MASK 0x04 3875 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL2_EN_SHIFT 2 3876 3877 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_MASK 0x08 3878 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL3_EN_SHIFT 3 3879 3880 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_MASK 0x30 3881 #define SERDES_25G_LANE_FEATURE_CDR_CAL_CFG0_CDR_IQ_CAL_RESULT_SEL_SHIFT 4 3882 3883 #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_MASK 0x01 3884 #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_REG_EN_SHIFT 0 3885 3886 #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_MASK 0x02 3887 #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TX_DCD_EN_SHIFT 1 3888 3889 #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_MASK 0x04 3890 #define SERDES_25G_LANE_FEATURE_TX_CAL_CFG0_TXDP_CLOCK_PHASE_EN_SHIFT 2 3891 3892 #define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_MASK 0x01 3893 #define SERDES_25G_LANE_FEATURE_ADAPT_CFG_EYE_MON_SHIFT 0 3894 3895 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_MASK 0x03 3896 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT 0 3897 3898 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_MASK 0x0C 3899 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT 2 3900 3901 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_MASK 0x30 3902 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE0_SHIFT 4 3903 3904 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_MASK 0xC0 3905 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_EIE1_SHIFT 6 3906 3907 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK 0xFF 3908 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT 0 3909 3910 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK 0xFF 3911 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT 0 3912 3913 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK 0xFF 3914 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT 0 3915 3916 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_MASK 0x01 3917 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT 0 3918 3919 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_MASK 0x04 3920 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_AGC_CFG_EIE0_EN_SHIFT 2 3921 3922 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_MASK 0x01 3923 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT 0 3924 3925 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_MASK 0x04 3926 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_APG_MAP_CFG_EIE0_EN_SHIFT 2 3927 3928 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_MASK 0x03 3929 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT 0 3930 3931 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_MASK 0x0C 3932 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT 2 3933 3934 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_MASK 0x30 3935 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE0_SEL_SHIFT 4 3936 3937 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_MASK 0xC0 3938 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_LFG_CFG_EIE1_SEL_SHIFT 6 3939 3940 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_MASK 0x01 3941 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT 0 3942 3943 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_MASK 0x02 3944 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT 1 3945 3946 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_MASK 0x04 3947 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT 2 3948 3949 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_MASK 0x08 3950 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT 3 3951 3952 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_MASK 0x10 3953 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_EDGE_EN_SHIFT 4 3954 3955 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_MASK 0x20 3956 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE0_DATA_EN_SHIFT 5 3957 3958 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_MASK 0x40 3959 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_EDGE_EN_SHIFT 6 3960 3961 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_MASK 0x80 3962 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG0_EIE1_DATA_EN_SHIFT 7 3963 3964 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_MASK 0x03 3965 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT 0 3966 3967 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_MASK 0x0C 3968 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT 2 3969 3970 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_MASK 0x30 3971 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE0_RESULT_SEL_SHIFT 4 3972 3973 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_MASK 0xC0 3974 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG1_EIE1_RESULT_SEL_SHIFT 6 3975 3976 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_MASK 0x01 3977 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_EDGE_EN_SHIFT 0 3978 3979 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_MASK 0x02 3980 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_DATA_EN_SHIFT 1 3981 3982 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_MASK 0x0C 3983 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_HFG_CFG2_CONT_RESULT_SEL_SHIFT 2 3984 3985 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_MASK 0x01 3986 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT 0 3987 3988 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_MASK 0x02 3989 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT 1 3990 3991 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_MASK 0x04 3992 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE0_EN_SHIFT 2 3993 3994 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_MASK 0x08 3995 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_EIE1_EN_SHIFT 3 3996 3997 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_MASK 0x10 3998 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_CONT_EN_SHIFT 4 3999 4000 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_MASK 0x01 4001 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_AGCLOS_START_VAL_SEL_SHIFT 0 4002 4003 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_MASK 0x02 4004 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_PLE_ATT_START_VAL_SEL_SHIFT 1 4005 4006 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_MASK 0x04 4007 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GN_APG_START_VAL_SEL_SHIFT 2 4008 4009 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_MASK 0x08 4010 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_LFG_START_VAL_SEL_SHIFT 3 4011 4012 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_MASK 0x10 4013 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_GNEQ_CCL_LFG_START_VAL_SEL_SHIFT 4 4014 4015 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_MASK 0x20 4016 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_HFG_SQL_START_VAL_SEL_SHIFT 5 4017 4018 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_MASK 0x40 4019 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBF_START_VAL_SEL_SHIFT 6 4020 4021 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_MASK 0x80 4022 #define SERDES_25G_LANE_FEATURE_CTLE_ADAPT_EIE0_CFG_EQ_MBG_START_VAL_SEL_SHIFT 7 4023 4024 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_MASK 0x01 4025 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP1_EN_SHIFT 0 4026 4027 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_MASK 0x02 4028 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP2_EN_SHIFT 1 4029 4030 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_MASK 0x04 4031 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP3_EN_SHIFT 2 4032 4033 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_MASK 0x08 4034 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP4_EN_SHIFT 3 4035 4036 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_MASK 0x10 4037 #define SERDES_25G_LANE_FEATURE_DFE_CFG_TAP5_EN_SHIFT 4 4038 4039 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_MASK 0x01 4040 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT 0 4041 4042 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_MASK 0xFF 4043 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG0_INTERVAL_7_0_SHIFT 0 4044 4045 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_MASK 0xFF 4046 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG1_INTERVAL_15_8_SHIFT 0 4047 4048 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_MASK 0xFF 4049 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_CONT_CFG2_INTERVAL_23_16_SHIFT 0 4050 4051 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_MASK 0x01 4052 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT 0 4053 4054 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_MASK 0x02 4055 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_EIE_EN_SHIFT 1 4056 4057 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_MASK 0x04 4058 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_CONT_EN_SHIFT 2 4059 4060 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_MASK 0x08 4061 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_START_VAL_SEL_SHIFT 3 4062 4063 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_MASK 0x01 4064 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT 0 4065 4066 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_MASK 0x02 4067 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_EIE_EN_SHIFT 1 4068 4069 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_MASK 0x04 4070 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_CONT_EN_SHIFT 2 4071 4072 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_MASK 0x08 4073 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_START_VAL_SEL_SHIFT 3 4074 4075 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_MASK 0x01 4076 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT 0 4077 4078 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_MASK 0x02 4079 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_EIE_EN_SHIFT 1 4080 4081 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_MASK 0x04 4082 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_CONT_EN_SHIFT 2 4083 4084 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_MASK 0x08 4085 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_START_VAL_SEL_SHIFT 3 4086 4087 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_MASK 0x01 4088 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT 0 4089 4090 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_MASK 0x02 4091 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_EIE_EN_SHIFT 1 4092 4093 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_MASK 0x04 4094 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_CONT_EN_SHIFT 2 4095 4096 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_MASK 0x08 4097 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_START_VAL_SEL_SHIFT 3 4098 4099 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_MASK 0x01 4100 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT 0 4101 4102 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_MASK 0x02 4103 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_EIE_EN_SHIFT 1 4104 4105 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_MASK 0x04 4106 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_CONT_EN_SHIFT 2 4107 4108 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_MASK 0x08 4109 #define SERDES_25G_LANE_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_START_VAL_SEL_SHIFT 3 4110 4111 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_MASK 0x01 4112 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_EN_SHIFT 0 4113 4114 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_MASK 0xFE 4115 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG0_CDR_LOCKD_TIMEOUT_US_SHIFT 1 4116 4117 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_MASK 0xFF 4118 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG1_CDR_LOCK_WAIT_TIME_US_SHIFT 0 4119 4120 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_MASK 0x01 4121 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG2_CDR_FREQ_MEASURE_EN_SHIFT 0 4122 4123 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_MASK 0x01 4124 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_RXCLKDIV_EN_SHIFT 0 4125 4126 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_MASK 0x02 4127 #define SERDES_25G_LANE_FEATURE_RX_CTRL_CFG3_BIST_HANDSHAKE_EN_SHIFT 1 4128 4129 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_MASK 0x03 4130 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_SIG_DET_MODE_SHIFT 0 4131 4132 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_MASK 0x0C 4133 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG0_LOS_DET_MODE_SHIFT 2 4134 4135 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_MASK 0xFF 4136 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG1_SIG_DET_THRESHOLD_SHIFT 0 4137 4138 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_MASK 0xFF 4139 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG2_LOS_DET_THRESHOLD_SHIFT 0 4140 4141 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_MASK 0xFF 4142 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG3_INTERVAL_7_0_SHIFT 0 4143 4144 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_MASK 0xFF 4145 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG4_INTERVAL_15_8_SHIFT 0 4146 4147 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_MASK 0xFF 4148 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG5_SAMPLE_LEN_7_0_SHIFT 0 4149 4150 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_MASK 0x0F 4151 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG6_SAMPLE_LEN_11_8_SHIFT 0 4152 4153 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_MASK 0x07 4154 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_PLE_ATT_SHIFT 0 4155 4156 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_MASK 0xF8 4157 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG7_EQ_LFG_SHIFT 3 4158 4159 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_MASK 0x03 4160 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_GN_APG_SHIFT 0 4161 4162 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_MASK 0x7C 4163 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG8_HFG_SQL_SHIFT 2 4164 4165 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_MASK 0x0F 4166 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBF_SHIFT 0 4167 4168 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_MASK 0xF0 4169 #define SERDES_25G_LANE_FEATURE_EYE_LOS_CFG9_MBG_SHIFT 4 4170 4171 #define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_MASK 0x01 4172 #define SERDES_25G_LANE_FEATURE_TEST_CFG0_LANE_MSM_DIS_SHIFT 0 4173 4174 #define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_MASK 0x02 4175 #define SERDES_25G_LANE_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT 1 4176 4177 #define SERDES_25G_LANE_FEATURE_SPARE_CFG0_MASK 0xFF 4178 #define SERDES_25G_LANE_FEATURE_SPARE_CFG0_SHIFT 0 4179 4180 #define SERDES_25G_LANE_FEATURE_SPARE_CFG1_MASK 0xFF 4181 #define SERDES_25G_LANE_FEATURE_SPARE_CFG1_SHIFT 0 4182 4183 #define SERDES_25G_LANE_FEATURE_SPARE_CFG2_MASK 0xFF 4184 #define SERDES_25G_LANE_FEATURE_SPARE_CFG2_SHIFT 0 4185 4186 #define SERDES_25G_LANE_FEATURE_SPARE_CFG3_MASK 0xFF 4187 #define SERDES_25G_LANE_FEATURE_SPARE_CFG3_SHIFT 0 4188 4189 #define SERDES_25G_LANE_FEATURE_SPARE_CFG4_MASK 0xFF 4190 #define SERDES_25G_LANE_FEATURE_SPARE_CFG4_SHIFT 0 4191 4192 #define SERDES_25G_LANE_FEATURE_SPARE_CFG5_MASK 0xFF 4193 #define SERDES_25G_LANE_FEATURE_SPARE_CFG5_SHIFT 0 4194 4195 #define SERDES_25G_LANE_FEATURE_SPARE_CFG6_MASK 0xFF 4196 #define SERDES_25G_LANE_FEATURE_SPARE_CFG6_SHIFT 0 4197 4198 #define SERDES_25G_LANE_FEATURE_SPARE_CFG7_MASK 0xFF 4199 #define SERDES_25G_LANE_FEATURE_SPARE_CFG7_SHIFT 0 4200 4201 #ifdef _cplusplus 4202 } 4203 #endif 4204 4205 #endif 4206