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Searched refs:SPR_L2CR (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/powerpc/aim/
H A Dmp_cpudep.c157 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
163 mtspr(SPR_L2CR, ccr | L2CR_L2I); in mpc74xx_l2_enable()
165 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
168 mtspr(SPR_L2CR, l2cr_config); in mpc74xx_l2_enable()
298 bsp_state[2] = mfspr(SPR_L2CR); in cpudep_save_config()
H A Daim_machdep.c701 cache_reg = mfspr(SPR_L2CR); in flush_disable_caches()
704 mtspr(SPR_L2CR, cache_reg); in flush_disable_caches()
706 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); in flush_disable_caches()
707 while (mfspr(SPR_L2CR) & L2CR_L2HWF) in flush_disable_caches()
711 mtspr(SPR_L2CR, cache_reg); in flush_disable_caches()
713 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); in flush_disable_caches()
715 while (mfspr(SPR_L2CR) & L2CR_L2I) in flush_disable_caches()
/freebsd/sys/powerpc/powerpc/
H A Dcpu.c545 if (mfspr(SPR_L2CR) & L2CR_L2E) { in cpu_6xx_print_cacheinfo()
562 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) { in cpu_6xx_print_cacheinfo()
573 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT) in cpu_6xx_print_cacheinfo()
575 if (mfspr(SPR_L2CR) & L2CR_L2PE) in cpu_6xx_print_cacheinfo()
/freebsd/sys/powerpc/include/
H A Dspr.h608 #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ macro