| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
39 if (*SRI == Idx) in getSubReg()
41 ++SRI; in getSubReg()
51 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
54 return *SRI; in getSubRegIndex()
55 ++SRI; in getSubRegIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 82 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in initReg() local
83 ++SRI) in initReg()
84 if (RI.subregs(*SRI).empty()) in initReg()
86 Uses.insert(*SRI); in initReg()
148 for (MCRegAliasIterator SRI(R, &RI, RI.subregs(R).empty()); SRI.isValid(); in init() local
149 ++SRI) { in init()
150 if (!RI.subregs(*SRI).empty()) in init()
154 if (R == *SRI) { in init()
168 SoftDefs.insert(*SRI); in init()
172 LatePreds.insert(*SRI); in init()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 228 for (auto &[OldSubReg, SRI] : SubRegs) { in getRegClassWithShiftedSubregs()
229 auto &[SubRegRC, NewSubReg] = SRI; in getRegClassWithShiftedSubregs()
283 for (auto [SubReg, SRI] : SubRegs) in getRegClassWithShiftedSubregs()
285 assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg)); in getRegClassWithShiftedSubregs()
299 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
323 for (auto [SubReg, SRI] : SubRegs) in getMinSizeReg()
327 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
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| H A D | AMDGPUMachineCFGStructurizer.cpp | 2058 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2059 unsigned SourceReg = (*SRI).first; in prunePHIInfo()
2069 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2101 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2106 auto SRI = PHIInfo.sources_begin(DestReg); in createEntryPHI() local
2107 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2117 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2118 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2135 BackedgePHI.addMBB((*SRI).second); in createEntryPHI()
2147 MIB.addMBB((*SRI).second); in createEntryPHI()
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| H A D | GCNSchedStrategy.cpp | 122 const SIRegisterInfo *SRI, in initCandidate() argument
211 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in pickNodeFromQueue() local
223 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, in pickNodeFromQueue()
1277 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(DAG.TRI); in collectRematerializableInstructions() local
1284 if (!SRI->isVGPRClass(DAG.MRI.getRegClass(Reg)) || in collectRematerializableInstructions()
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| H A D | GCNSchedStrategy.h | 52 const SIRegisterInfo *SRI,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyCFGSort.cpp | 223 SortRegionInfo SRI(MLI, WEI); in sortBlocks() local
226 const SortRegion *R = SRI.getRegionFor(MBB); in sortBlocks()
344 const SortRegion *Region = SRI.getRegionFor(&MBB); in sortBlocks()
370 assert(OnStack.count(SRI.getRegionFor(&MBB)) && in sortBlocks()
373 while (OnStack.size() > 1 && &MBB == SRI.getBottom(OnStack.back())) in sortBlocks()
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| H A D | WebAssemblyCFGStackify.cpp | 402 SortRegionInfo SRI(MLI, WEI); in placeLoopMarker() local
411 MachineBasicBlock *Bottom = SRI.getBottom(Loop); in placeLoopMarker()
472 SortRegionInfo SRI(MLI, WEI); in placeTryMarker() local
492 MachineBasicBlock *Bottom = SRI.getBottom(WE); in placeTryMarker()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | VirtRegMap.cpp | 323 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
324 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
325 ++SRI; in addLiveInsForSubRanges()
326 if (SRI == SR->end()) in addLiveInsForSubRanges()
328 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 134 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
318 SubRegMap::const_iterator SRI = Map.find(Comp.first); in computeSubRegs() local
319 if (SRI == Map.end()) in computeSubRegs()
323 if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second)) in computeSubRegs()
326 SubRegs.insert(std::make_pair(Comp.second, SRI->second)); in computeSubRegs()
1237 for (CodeGenSubRegIndex &SRI : SubRegIndices) { in CodeGenRegBank()
1238 SRI.computeConcatTransitiveClosure(); in CodeGenRegBank()
1239 if (!SRI.ConcatenationOf.empty()) in CodeGenRegBank()
1242 SRI.ConcatenationOf.end()), &SRI)); in CodeGenRegBank()
1811 for (auto SRI : SRM) { in normalizeWeight() local
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| H A D | RegisterInfoEmitter.cpp | 1869 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump() local
1870 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1871 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1872 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1873 OS << "\tOffset, Size: " << SRI.Offset << ", " << SRI.Size << '\n'; in debugDump()
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| H A D | GlobalISelMatchTable.h | 2091 SubRegIndexRenderer(unsigned InsnID, const CodeGenSubRegIndex *SRI) in SubRegIndexRenderer() argument
2092 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
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| /freebsd/sys/dev/gpio/dwgpio/ |
| H A D | dwgpio_if.m | 4 # This software was developed by SRI International and the University of
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| /freebsd/sys/dts/arm/ |
| H A D | tegra124-jetson-tk1-fbsd.dts | 5 * This software was developed by SRI International and the University of
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| H A D | socfpga_cyclone5_sockit_sdmmc.dts | 5 * This software was developed by SRI International and the University of
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| H A D | socfpga_arria10_socdk_sdmmc.dts | 5 * This software was developed by SRI International and the University of
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| H A D | socfpga_cyclone5_sockit_beri_sdmmc.dts | 5 * This software was developed by SRI International and the University of
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| /freebsd/sys/arm64/coresight/ |
| H A D | coresight_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/dev/altera/pio/ |
| H A D | pio_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/dev/flash/ |
| H A D | qspi_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/dev/virtio/mmio/ |
| H A D | virtio_mmio_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/dev/xdma/ |
| H A D | xdma_if.m | 5 # This software was developed by SRI International and the University of
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| /freebsd/sys/arm64/iommu/ |
| H A D | iommu_if.m | 6 # This software was developed by SRI International and the University of
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| /freebsd/sbin/pfctl/tests/ |
| H A D | pfctl_test_list.inc | 6 * This software was developed by SRI International and the University of
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 1929 for (MCSubRegIndexIterator SRI(SrcRegNum, TRI); SRI.isValid(); ++SRI) { in performCopy() local
1930 unsigned SrcSubReg = SRI.getSubReg(); in performCopy()
1931 unsigned SubRegIdx = SRI.getSubRegIndex(); in performCopy()
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