| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZPostRewrite.cpp | 105 Register Src2Reg = MBBI->getOperand(2).getReg(); in selectSELRMux() local
108 bool Src2IsHigh = SystemZ::isHighReg(Src2Reg); in selectSELRMux()
113 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
126 Src2Reg = DestReg; in selectSELRMux()
132 if (DestReg != Src1Reg && DestReg == Src2Reg) { in selectSELRMux()
134 std::swap(Src1Reg, Src2Reg); in selectSELRMux()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
319 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
321 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
327 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
335 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
337 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
354 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
356 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
364 Src2Reg = MCI.getOperand(2).getReg(); in getDuplexCandidateGroup()
365 if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
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| H A D | HexagonMCCompound.cpp | 81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
99 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
102 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 276 Register Src2Reg = MI->getOperand(3).getReg(); in ExpandFPMLxInstruction() local
292 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 3398 Register DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3414 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
3896 Register DstReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
4035 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4037 isIntRegForSubInst(Src2Reg) && in getDuplexCandidateGroup()
4051 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4069 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4079 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
4080 if (isDblRegForSubInst(Src2Reg, HRI) && in getDuplexCandidateGroup()
4155 Src2Reg = MI.getOperand(2).getReg(); in getDuplexCandidateGroup()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1881 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorSHL() local
1914 Shl.addUse(Src2Reg); in selectVectorSHL()
1927 Register Src2Reg = I.getOperand(2).getReg(); in selectVectorAshrLshr() local
1971 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg}); in selectVectorAshrLshr()
3717 Register Src2Reg = I.getOperand(3).getReg(); in selectVectorICmp() local
3866 std::swap(SrcReg, Src2Reg); in selectVectorICmp()
3868 auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg}); in selectVectorICmp()
3954 Register Src2Reg = I.getOperand(2).getReg(); in selectMergeValues() local
5212 Register Src2Reg = I.getOperand(2).getReg(); in selectShuffleVector() local
5213 const LLT Src2Ty = MRI.getType(Src2Reg); in selectShuffleVector()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2655 Register Src2Reg = getRegForValue(Src2Val); in optimizeSelect() local
2656 if (!Src2Reg) in optimizeSelect()
2663 Src2Reg); in optimizeSelect()
2775 Register Src2Reg = getRegForValue(SI->getFalseValue()); in selectSelect() local
2777 if (!Src1Reg || !Src2Reg) in selectSelect()
2781 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
2783 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC); in selectSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1039 Register Src2Reg = getRegForValue(SI->getFalseValue()); in selectSelect() local
1042 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1058 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 4517 Register Src2Reg = PtrAdd.getOffsetReg(); in reassociationCanBreakAddressingModePattern() local
4525 auto C2 = getIConstantVRegVal(Src2Reg, MRI); in reassociationCanBreakAddressingModePattern()
4637 Register Src2Reg = MI.getOperand(2).getReg(); in matchReassocFoldConstantsInSubTree() local
4643 auto C2 = getIConstantVRegVal(Src2Reg, MRI); in matchReassocFoldConstantsInSubTree()
4648 auto NewCst = B.buildConstant(MRI.getType(Src2Reg), *C1 + *C2); in matchReassocFoldConstantsInSubTree()
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| H A D | LegalizerHelper.cpp | 4665 auto [DstReg, DstTy, Src1Reg, Src1Ty, Src2Reg, Src2Ty] = in fewerElementsVectorShuffle()
4685 extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs, MIRBuilder, MRI); in fewerElementsVectorShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3974 MCRegister Src2Reg = Src2.getReg(); in validateMFMA() local
3976 if (Src2Reg == DstReg) in validateMFMA()
3983 if (TRI->regsOverlap(Src2Reg, DstReg)) { in validateMFMA()
3984 Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands), in validateMFMA()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 16706 Register Src2Reg = MI.getOperand(2).getReg(); in emitQuietFCMP() local
16716 .addReg(Src2Reg); in emitQuietFCMP()
16727 .addReg(Src2Reg, getKillRegState(MI.getOperand(2).isKill())); in emitQuietFCMP()
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