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Searched refs:SrcReg (Results 1 – 25 of 204) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) in getCRFromCRBit()
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) in getCRFromCRBit()
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) in getCRFromCRBit()
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) in getCRFromCRBit()
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H A DPPCFastISel.cpp748 if (SrcReg == 0) in SelectStore()
964 if (!SrcReg) in SelectFPExt()
982 if (!SrcReg) in SelectFPTrunc()
999 SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg); in SelectFPTrunc()
1025 SrcReg = TmpReg; in PPCMoveToFPReg()
1083 if (SrcReg == 0) in SelectIToFP()
1121 SrcReg = TmpReg; in SelectIToFP()
1210 if (SrcReg == 0) in SelectFPToI()
1217 SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg); in SelectFPToI()
1219 SrcReg = copyRegToRegClass(&PPC::VSFRCRegClass, SrcReg); in SelectFPToI()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp136 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
138 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
142 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
156 Register SrcReg = Src2.getReg(); in runOnMachineFunction() local
157 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
173 Register SrcReg = Src1.getReg(); in runOnMachineFunction() local
175 std::make_pair(*&SrcReg, Hexagon::isub_hi); in runOnMachineFunction()
184 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
190 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
206 Register SrcReg = Src.getReg(); in runOnMachineFunction() local
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H A DHexagonInstrInfo.cpp865 .addReg(SrcReg, KillFlag); in copyPhysReg()
870 .addReg(SrcReg, KillFlag); in copyPhysReg()
876 .addReg(SrcReg).addReg(SrcReg, KillFlag); in copyPhysReg()
882 .addReg(SrcReg, KillFlag); in copyPhysReg()
888 .addReg(SrcReg, KillFlag); in copyPhysReg()
894 .addReg(SrcReg, KillFlag); in copyPhysReg()
900 .addReg(SrcReg, KillFlag); in copyPhysReg()
917 addReg(SrcReg, KillFlag); in copyPhysReg()
934 .addReg(SrcReg) in copyPhysReg()
4022 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg)) in getDuplexCandidateGroup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp42 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg()
53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
63 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
80 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
85 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) && in storeRegToStackSlot()
89 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
99 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h86 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
97 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
134 LLT SrcTy = MRI.getType(SrcReg); in tryCombineZExt()
204 LLT SrcTy = MRI.getType(SrcReg); in tryCombineSExt()
217 if (mi_match(SrcReg, MRI, in tryCombineSExt()
564 MRI.replaceRegWith(DstReg, SrcReg); in replaceRegOrBuildCopy()
565 UpdatedDefs.push_back(SrcReg); in replaceRegOrBuildCopy()
620 CurrentBest = SrcReg; in findValueFromConcat()
778 CurrentBest = SrcReg; in findValueFromExt()
1047 LLT OpTy = MRI.getType(SrcReg); in tryCombineUnmergeValues()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp45 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
61 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
68 LoongArch::GPRRegClass.contains(SrcReg)) { in copyPhysReg()
70 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
75 LoongArch::CFRRegClass.contains(SrcReg)) { in copyPhysReg()
107 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
140 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
187 Register SrcReg = LoongArch::R0; in movImm() local
207 .addReg(SrcReg, RegState::Kill) in movImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp34 MCRegister SrcReg, bool KillSrc) const { in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
47 Register SrcReg = MI->getOperand(1).getReg(); in expandMEMCPY() local
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg) in expandMEMCPY()
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset); in expandMEMCPY()
126 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
136 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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H A DBPFMISimplifyPatchable.cpp65 MachineInstr &MI, Register &SrcReg, Register &DstReg,
68 Register &SrcReg, const GlobalValue *GVal,
190 MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg, in processCandidate() argument
216 .addReg(SrcReg, 0, BPF::sub_32); in processCandidate()
221 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
225 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument
254 I->setReg(SrcReg); in processDstReg()
330 Register SrcReg = MI.getOperand(1).getReg(); in removeLD() local
332 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD()
355 processCandidate(MRI, MBB, MI, SrcReg, DstReg, GVal, IsAma); in removeLD()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp429 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
482 if (CSKY::GPRRegClass.contains(SrcReg) && in copyPhysReg()
486 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
489 assert(SrcReg < CSKY::R8); in copyPhysReg()
491 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
497 if (CSKY::CARRYRegClass.contains(SrcReg) && in copyPhysReg()
502 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
509 .addReg(SrcReg, RegState::Define) in copyPhysReg()
512 .addReg(SrcReg, getKillRegState(true)); in copyPhysReg()
522 if (CSKY::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
294 SrcReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
306 if (Hexagon::P0 == SrcReg) { in getDuplexCandidateGroup()
414 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
419 if (DstReg == SrcReg) { in getDuplexCandidateGroup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp102 SrcReg = 0; in copyPhysReg()
105 SrcReg = 0; in copyPhysReg()
150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
153 Opc = Mips::MFHI64, SrcReg = 0; in copyPhysReg()
155 Opc = Mips::MFLO64, SrcReg = 0; in copyPhysReg()
179 if (SrcReg) in copyPhysReg()
270 SrcReg = Mips::K0; in storeRegToStack()
273 SrcReg = Mips::K0_64; in storeRegToStack()
276 SrcReg = Mips::K0; in storeRegToStack()
279 SrcReg = Mips::K0_64; in storeRegToStack()
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H A DMipsFastISel.cpp847 .addReg(SrcReg) in emitStore()
907 unsigned SrcReg = 0; in selectStore() local
920 if (SrcReg == 0) in selectStore()
997 Register SrcReg = in selectFPExt() local
1000 if (!SrcReg) in selectFPExt()
1077 if (!SrcReg) in selectFPTrunc()
1113 if (SrcReg == 0) in selectFPToInt()
1592 if (SrcReg == 0) in fastLowerIntrinsicCall()
1752 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1786 if (!SrcReg) in selectTrunc()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DPHIElimination.cpp463 isImplicitlyDefined(SrcReg, *MRI); in LowerPHINode()
464 assert(SrcReg.isVirtual() && in LowerPHINode()
477 MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg); in LowerPHINode()
484 assert(MRI->use_empty(SrcReg) && in LowerPHINode()
502 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); in LowerPHINode()
532 !LV->isLiveOut(SrcReg, opBlock)) { in LowerPHINode()
552 if (Term->readsRegister(SrcReg)) in LowerPHINode()
566 if (KillInst->readsRegister(SrcReg)) in LowerPHINode()
610 if (Term->readsRegister(SrcReg)) in LowerPHINode()
624 if (KillInst->readsRegister(SrcReg)) in LowerPHINode()
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H A DOptimizePHIs.cpp112 Register SrcReg = MI->getOperand(i).getReg(); in IsSingleValuePHICycle() local
113 if (SrcReg == DstReg) in IsSingleValuePHICycle()
115 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
121 SrcReg = SrcMI->getOperand(1).getReg(); in IsSingleValuePHICycle()
122 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
132 if (SingleValReg != 0 && SingleValReg != SrcReg) in IsSingleValuePHICycle()
134 SingleValReg = SrcReg; in IsSingleValuePHICycle()
H A DRegisterCoalescer.h36 Register SrcReg; variable
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} in CoalescerPair()
100 Register getSrcReg() const { return SrcReg; } in getSrcReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp78 Register SrcReg = MI->getOperand(1).getReg(); in visitMBB() local
81 (SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) { in visitMBB()
83 if (SrcReg == SystemZ::CC) in visitMBB()
86 BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg); in visitMBB()
90 else if (SrcReg.isVirtual() && in visitMBB()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp454 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
456 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
464 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
468 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
479 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
493 SP::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
496 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
498 SP::ASRRegsRegClass.contains(SrcReg)) { in copyPhysReg()
500 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
512 Register Src = TRI->getSubReg(SrcReg, subRegIdx[i]); in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp160 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandArith()
687 .addReg(SrcReg) in expand()
795 .addReg(SrcReg) in expand()
811 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg).addReg(SrcReg).addImm(Imm + 2); in expand()
820 .addReg(SrcReg) in expand()
865 .addReg(SrcReg); in expandLPMWELPMW()
2428 if (SrcReg != DstLoReg) in expand()
2431 .addReg(SrcReg); in expand()
2433 if (SrcReg != DstHiReg) { in expand()
2436 .addReg(SrcReg); in expand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp255 Register SrcReg = MI.getOperand(1).getReg(); in matchUCharToFloat() local
256 unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits(); in matchUCharToFloat()
259 return Helper.getKnownBits()->maskedValueIsZero(SrcReg, Mask); in matchUCharToFloat()
272 Register SrcReg = MI.getOperand(1).getReg(); in applyUCharToFloat() local
274 LLT SrcTy = MRI.getType(SrcReg); in applyUCharToFloat()
276 SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0); in applyUCharToFloat()
279 B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg}, {SrcReg}, in applyUCharToFloat()
282 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, {SrcReg}, in applyUCharToFloat()
339 Register SrcReg = MI.getOperand(1).getReg(); in matchCvtF32UByteN() local
342 bool IsShr = mi_match(SrcReg, MRI, m_GZExt(m_Reg(SrcReg))); in matchCvtF32UByteN()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp178 auto [DstReg, SrcReg] = MI.getFirst2Regs(); in runOnMachineFunction()
186 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
187 assert(canReplaceReg(DstReg, SrcReg, MRI) && in runOnMachineFunction()
190 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
243 Register SrcReg = MI.getOperand(1).getReg(); in runOnMachineFunction() local
245 if (SrcReg.isVirtual() && DstReg.isVirtual()) { in runOnMachineFunction()
246 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction()
249 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp163 return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs; in forwardCopyWillClobberTuple()
265 if (MO.getReg() != SrcReg) in isConvertibleToVMV_V_V()
452 SrcReg = TRI->getMatchingSuperReg(SrcReg, RISCV::sub_16, in copyPhysReg()
477 RISCV::GPRRegClass.contains(SrcReg)) { in copyPhysReg()
491 RISCV::GPRRegClass.contains(SrcReg)) { in copyPhysReg()
822 Register SrcReg = RISCV::X0; in movImm() local
849 .addReg(SrcReg, SrcRegState) in movImm()
856 .addReg(SrcReg, SrcRegState) in movImm()
857 .addReg(SrcReg, SrcRegState) in movImm()
863 .addReg(SrcReg, SrcRegState) in movImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp297 .addReg(SrcReg) in selectCopy()
312 (SrcReg.isPhysical() && in selectCopy()
321 SrcReg.isPhysical()) { in selectCopy()
766 const LLT SrcTy = MRI.getType(SrcReg); in selectTruncOrPtrToInt()
830 const LLT SrcTy = MRI.getType(SrcReg); in selectZext()
860 Register DefReg = SrcReg; in selectZext()
871 .addReg(SrcReg) in selectZext()
934 .addReg(SrcReg) in selectAnyext()
1279 .addReg(SrcReg, 0, SubIdx); in emitExtractSubreg()
1317 .addReg(SrcReg); in emitInsertSubreg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp636 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
640 else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
645 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
656 if (M68k::DR8RegClass.contains(SrcReg)) { in copyPhysReg()
661 } else if (M68k::XR16RegClass.contains(SrcReg) && in copyPhysReg()
667 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
671 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
672 bool FromSR = SrcReg == M68k::SR; in copyPhysReg()
681 assert(M68k::DR8RegClass.contains(SrcReg) && in copyPhysReg()
689 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp215 .addReg(SrcReg) in visitAND()
275 Register SrcReg = MI.getOperand(2).getReg(); in visitORR() local
276 MRI->replaceRegWith(DefReg, SrcReg); in visitORR()
277 MRI->clearKillFlags(SrcReg); in visitORR()
388 .addReg(SrcReg) in visitADDSUB()
434 .addReg(SrcReg) in visitADDSSUBS()
533 Register SrcReg = MI.getOperand(1).getReg(); in splitTwoPartImm() local
542 MRI->constrainRegClass(SrcReg, FirstInstrOperandRC); in splitTwoPartImm()
548 BuildInstr(MI, Opcode, Imm0, Imm1, SrcReg, NewTmpReg, NewDstReg); in splitTwoPartImm()
597 Register SrcReg = SrcMI->getOperand(1).getReg(); in visitINSviGPR() local
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