| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 189 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
200 .addReg(SrcVec) in RebuildVector()
211 SrcVec = DstReg; in RebuildVector()
214 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
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| H A D | SIISelLowering.cpp | 4505 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
4509 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst()
4517 SrcVec->getReg(), in emitIndirectDst()
4528 .add(*SrcVec) in emitIndirectDst()
4547 .addReg(SrcVec->getReg()) in emitIndirectDst()
4557 .addReg(SrcVec->getReg()) in emitIndirectDst()
4574 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset, in emitIndirectDst()
8268 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
8271 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 399 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
401 if (Value *V = simplifyExtractElementInst(SrcVec, Index, in visitExtractElementInst()
459 if (auto *Phi = dyn_cast<PHINode>(SrcVec)) in visitExtractElementInst()
467 if (match(SrcVec, m_UnOp(UO)) && cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
475 if (match(SrcVec, m_BinOp(BO)) && cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
486 cheapToScalarize(SrcVec, Index)) { in visitExtractElementInst()
493 if (auto *I = dyn_cast<Instruction>(SrcVec)) { in visitExtractElementInst()
583 if (SrcVec->hasOneUse()) { in visitExtractElementInst()
599 if (V != SrcVec) { in visitExtractElementInst()
600 Worklist.addValue(SrcVec); in visitExtractElementInst()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 497 Register SrcVec = Left; in matchINS() local
501 SrcVec = Right; in matchINS()
505 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
515 Register DstVec, SrcVec; in applyINS() local
517 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
519 auto Extract = Builder.buildExtractVectorElement(ScalarTy, SrcVec, SrcCst); in applyINS()
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| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 1549 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1561 SrcVec = Src; in executeBitCastInst()
1567 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1588 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1593 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1596 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 630 Value *SrcVec; in foldInsExtFNeg() local
634 m_ExtractElt(m_Value(SrcVec), m_SpecificInt(Index)))))) in foldInsExtFNeg()
639 if (SrcVec->getType() != VecTy) in foldInsExtFNeg()
675 Value *VecFNeg = Builder.CreateFNegFMF(SrcVec, FNeg); in foldInsExtFNeg()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Verifier.cpp | 3173 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
3176 Check(SrcVec == DstVec, in visitUIToFPInst()
3183 if (SrcVec && DstVec) in visitUIToFPInst()
3196 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
3199 Check(SrcVec == DstVec, in visitSIToFPInst()
3206 if (SrcVec && DstVec) in visitSIToFPInst()
3219 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
3222 Check(SrcVec == DstVec, in visitFPToUIInst()
3228 if (SrcVec && DstVec) in visitFPToUIInst()
3244 Check(SrcVec == DstVec, in visitFPToSIInst()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 1031 CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
1034 {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
1039 CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
1042 {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenFunction.cpp | 2957 llvm::Value *CodeGenFunction::emitBoolVecConversion(llvm::Value *SrcVec, in emitBoolVecConversion() argument
2960 auto *SrcTy = cast<llvm::FixedVectorType>(SrcVec->getType()); in emitBoolVecConversion()
2963 return SrcVec; in emitBoolVecConversion()
2970 return Builder.CreateShuffleVector(SrcVec, ShuffleMask, Name); in emitBoolVecConversion()
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| H A D | CodeGenFunction.h | 4835 llvm::Value *emitBoolVecConversion(llvm::Value *SrcVec,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3114 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt()
3243 auto [Dst, DstTy, SrcVec, SrcVecTy, Val, ValTy, Idx, IdxTy] = in bitcastInsertVectorElt()
3255 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt()
4337 auto [DstReg, SrcVec] = MI.getFirst2Regs(); in fewerElementsVectorExtractInsertVectorElt()
4351 LLT VecTy = MRI.getType(SrcVec); in fewerElementsVectorExtractInsertVectorElt()
4367 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); in fewerElementsVectorExtractInsertVectorElt()
7131 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
7138 LLT VecTy = MRI.getType(SrcVec); in lowerExtractInsertVectorElt()
7145 extractParts(SrcVec, EltTy, NumElts, SrcRegs, MIRBuilder, MRI); in lowerExtractInsertVectorElt()
7170 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); in lowerExtractInsertVectorElt()
[all …]
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| H A D | CombinerHelper.cpp | 3985 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec() local
3986 LLT SrcTy = MRI.getType(SrcVec); in matchExtractVecEltBuildVec()
3996 MachineInstr *SrcVecMI = MRI.getVRegDef(SrcVec); in matchExtractVecEltBuildVec()
4006 if (!MRI.hasOneNonDBGUse(SrcVec) && in matchExtractVecEltBuildVec()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8359 SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec)); in createVariablePermute()
8426 DAG.getVectorShuffle(VT, DL, SrcVec, SrcVec, {0, 0}), in createVariablePermute()
8427 DAG.getVectorShuffle(VT, DL, SrcVec, SrcVec, {1, 1}), in createVariablePermute()
8482 SrcVec = DAG.getBitcast(MVT::v8f32, SrcVec); in createVariablePermute()
8483 SDValue LoLo = DAG.getVectorShuffle(MVT::v8f32, DL, SrcVec, SrcVec, in createVariablePermute()
8485 SDValue HiHi = DAG.getVectorShuffle(MVT::v8f32, DL, SrcVec, SrcVec, in createVariablePermute()
8506 SrcVec = widenSubVector(WidenSrcVT, SrcVec, false, Subtarget, DAG, in createVariablePermute()
8516 SrcVec = DAG.getBitcast(MVT::v4f64, SrcVec); in createVariablePermute()
8567 SrcVec = DAG.getBitcast(ShuffleVT, SrcVec); in createVariablePermute()
8600 if (!SrcVec) in LowerBUILD_VECTORAsVariablePermute()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1974 auto GetConvertedLane = [](SDValue Op, unsigned &Opcode, SDValue &SrcVec, in LowerConvertLow()
1997 SrcVec = ExtractVector.getOperand(0); in LowerConvertLow()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 861 auto IsBuildFromExtracts = [this,&Values] (SDValue &SrcVec, in buildHvxVectorReg()
883 SrcVec = Vec; in buildHvxVectorReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4723 SDValue SrcVec = (unsigned)SrcVecIdx >= VRegsPerSrc ? V2 : V1; in lowerShuffleViaVRegSplitting() local
4724 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec, in lowerShuffleViaVRegSplitting()
12131 SDValue SrcVec = RHS.getOperand(0); in combineBinOpOfExtractToReduceTree() local
12132 EVT SrcVecVT = SrcVec.getValueType(); in combineBinOpOfExtractToReduceTree()
12145 LHS.getOperand(0) == SrcVec && isa<ConstantSDNode>(LHS.getOperand(1))) { in combineBinOpOfExtractToReduceTree()
12150 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec, in combineBinOpOfExtractToReduceTree()
12172 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec, in combineBinOpOfExtractToReduceTree()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 26091 SDValue SrcVec = Scalar.getOperand(0); in visitSCALAR_TO_VECTOR() local
26092 EVT SrcVT = SrcVec.getValueType(); in visitSCALAR_TO_VECTOR()
26100 SrcVT, SDLoc(N), SrcVec, DAG.getUNDEF(SrcVT), Mask, DAG); in visitSCALAR_TO_VECTOR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14897 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
14901 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl)); in DAGCombineBuildVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12317 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
12320 SrcVec = V2; in LowerVECTOR_SHUFFLE()
12332 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
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