Searched refs:VReg2 (Results 1 – 3 of 3) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstructionSelector.cpp | 250 Register VReg2 = MIB.getReg(2); in selectMergeValues() local 251 (void)VReg2; in selectMergeValues() 252 assert(MRI.getType(VReg2).getSizeInBits() == 32 && in selectMergeValues() 253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues() 282 Register VReg2 = MIB.getReg(2); in selectUnmergeValues() local 283 (void)VReg2; in selectUnmergeValues() 284 assert(MRI.getType(VReg2).getSizeInBits() == 64 && in selectUnmergeValues() 285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
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H A D | ARMISelLowering.cpp | 11032 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock() local 11034 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() 11035 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2) in EmitSjLjDispatchBlock() 11043 .addReg(VReg2) in EmitSjLjDispatchBlock() 11169 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock() local 11171 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() 11172 BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2) in EmitSjLjDispatchBlock() 11180 .addReg(VReg2) in EmitSjLjDispatchBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 697 Register VReg2 = MRI->createVirtualRegister(RC); in generateLoadForNewConst() local 704 BuildMI(*MF, MI->getDebugLoc(), get(LoadOpcode), VReg2) in generateLoadForNewConst() 714 return VReg2; in generateLoadForNewConst()
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