| /freebsd/sys/dev/iicbus/controller/cadence/ |
| H A D | cdnc_i2c.c | 224 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow); in cdnc_i2c_set_freq()
238 WR2(sc, CDNC_I2C_CR, CDNC_I2C_CR_CLR_FIFO); in cdnc_i2c_init_hw()
242 WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL); in cdnc_i2c_init_hw()
243 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_ALL); in cdnc_i2c_init_hw()
313 WR2(sc, CDNC_I2C_ISR, status); in cdnc_i2c_intr()
359 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow); in cdnc_i2c_xfer_rd()
365 WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1); in cdnc_i2c_xfer_rd()
431 WR2(sc, CDNC_I2C_DATA, msg->buf[idx++]); in cdnc_i2c_xfer_wr()
443 WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1); in cdnc_i2c_xfer_wr()
646 WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL); in cdnc_i2c_detach()
[all …]
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| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx_wdog.c | 94 WR2(struct imx_wdog_softc *sc, bus_size_t offs, uint16_t val) in WR2() function
114 WR2(sc, WDOG_CR_REG, reg | WDOG_CR_WDE); in imx_wdog_enable()
117 WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1); in imx_wdog_enable()
118 WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2); in imx_wdog_enable()
123 WR2(sc, WDOG_MCR_REG, reg & ~WDOG_MCR_PDE); in imx_wdog_enable()
206 WR2(sc, WDOG_CR_REG, WDOG_CR_WDT | RD2(sc, WDOG_CR_REG)); in imx_wdog_attach()
210 WR2(sc, WDOG_ICR_REG, WDOG_ICR_WIE); /* Enable, count is 0. */ in imx_wdog_attach()
|
| /freebsd/sys/dev/sdhci/ |
| H A D | sdhci.c | 424 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); in sdhci_set_clock()
447 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); in sdhci_set_clock()
486 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
489 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
505 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
1353 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1421 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1436 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1740 WR2(slot, SDHCI_TRANSFER_MODE, mode);
2007 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
[all …]
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| /freebsd/sys/dev/ffec/ |
| H A D | if_ffec.c | 217 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) in WR2() function
293 WR2(sc, FEC_MIIGSK_ENR, 0); in ffec_miigasket_setup()
297 WR2(sc, FEC_MIIGSK_CFGR, ifmode); in ffec_miigasket_setup()
299 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); in ffec_miigasket_setup()
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_sdhost.c | 272 WR2(struct bcm_sdhost_softc *sc, bus_size_t off, uint16_t val) in WR2() function
1096 WR2(sc, HC_BLOCKSIZE, val); in bcm_sdhost_write_2()
1103 WR2(sc, HC_BLOCKCOUNT, val); in bcm_sdhost_write_2()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 628 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, in DecodeHvxWRRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 254 def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>;
|