/freebsd/sys/arm/freescale/vybrid/ |
H A D | vf_dcu4.c | 229 WRITE4(sc, DCU_INT_STATUS, reg); in dcu_intr() 294 WRITE4(sc, DCU_DISP_SIZE, reg); in dcu_init() 299 WRITE4(sc, DCU_HSYN_PARA, reg); in dcu_init() 304 WRITE4(sc, DCU_VSYN_PARA, reg); in dcu_init() 306 WRITE4(sc, DCU_BGND, 0); in dcu_init() 310 WRITE4(sc, DCU_SYNPOL, reg); in dcu_init() 316 WRITE4(sc, DCU_THRESHOLD, reg); in dcu_init() 319 WRITE4(sc, DCU_INT_MASK, 0xffffffff); in dcu_init() 336 WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); in dcu_init() 337 WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); in dcu_init() [all …]
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H A D | vf_anadig.c | 140 WRITE4(sc, pll_ctrl, reg); in enable_pll() 148 WRITE4(sc, pll_ctrl, reg); in enable_pll() 168 WRITE4(sc, ANADIG_PLL4_CTRL, reg); in pll4_configure_output() 169 WRITE4(sc, ANADIG_PLL4_NUM, mfn); in pll4_configure_output() 170 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); in pll4_configure_output() 208 WRITE4(sc, ANADIG_REG_3P0, reg); in anadig_attach() 213 WRITE4(sc, USB_MISC(0), reg); in anadig_attach() 217 WRITE4(sc, USB_MISC(1), reg); in anadig_attach()
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H A D | vf_spi.c | 166 WRITE4(sc, SPI_MCR, reg); in spi_attach() 170 WRITE4(sc, SPI_RSER, reg); in spi_attach() 174 WRITE4(sc, SPI_MCR, reg); in spi_attach() 192 WRITE4(sc, SPI_CTAR0, reg); in spi_attach() 197 WRITE4(sc, SPI_CTAR0, reg); in spi_attach() 222 WRITE4(sc, SPI_PUSHR, wreg); in spi_txrx() 233 WRITE4(sc, SPI_SR, reg); in spi_txrx()
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H A D | vf_adc.c | 171 WRITE4(sc, ADC_HC0, reg); in adc_enable() 208 WRITE4(sc, ADC_CFG, reg); in adc_attach() 213 WRITE4(sc, ADC_GC, reg); in adc_attach() 218 WRITE4(sc, ADC_HC0, reg); in adc_attach()
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H A D | vf_sai.c | 358 WRITE4(sc, I2S_TCR2, reg); in sai_configure_clock() 623 WRITE4(sc, I2S_TCSR, reg); in setup_sai() 627 WRITE4(sc, I2S_TCR3, reg); in setup_sai() 630 WRITE4(sc, I2S_TCR1, reg); in setup_sai() 636 WRITE4(sc, I2S_TCR2, reg); in setup_sai() 642 WRITE4(sc, I2S_TCR3, reg); in setup_sai() 651 WRITE4(sc, I2S_TCR4, reg); in setup_sai() 660 WRITE4(sc, I2S_TCR5, reg); in setup_sai() 666 WRITE4(sc, I2S_TCSR, reg); in setup_sai()
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/freebsd/sys/dev/flash/ |
H A D | cqspi.c | 433 WRITE4(sc, CQSPI_INDWR, 0); in cqspi_write() 442 WRITE4(sc, CQSPI_DEVWR, reg); in cqspi_write() 447 WRITE4(sc, CQSPI_DEVRD, reg); in cqspi_write() 485 WRITE4(sc, CQSPI_INDRD, 0); in cqspi_read() 496 WRITE4(sc, CQSPI_DEVRD, reg); in cqspi_read() 499 WRITE4(sc, CQSPI_IRQMASK, 0); in cqspi_read() 553 WRITE4(sc, CQSPI_CFG, reg); in cqspi_init() 558 WRITE4(sc, CQSPI_DEVSZ, reg); in cqspi_init() 569 WRITE4(sc, CQSPI_CFG, reg); in cqspi_init() 575 WRITE4(sc, CQSPI_DELAY, reg); in cqspi_init() [all …]
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/freebsd/sys/arm/freescale/imx/ |
H A D | imx6_sdma.c | 64 #define WRITE4(_sc, _reg, _val) \ macro 97 WRITE4(sc, SDMAARM_INTR, pending); in sdma_intr() 219 WRITE4(sc, SDMAARM_EVTOVR, reg); in sdma_overrides() 227 WRITE4(sc, SDMAARM_HOSTOVR, reg); in sdma_overrides() 235 WRITE4(sc, SDMAARM_DSPOVR, reg); in sdma_overrides() 327 WRITE4(sc, SDMAARM_HSTART, 1); in sdma_configure() 344 WRITE4(sc, SDMAARM_INTR, ret); in sdma_configure() 392 WRITE4(sc, SDMAARM_MC0PTR, 0); in boot_firmware() 428 WRITE4(sc, SDMAARM_CONFIG, 0); in boot_firmware() 439 WRITE4(sc, SDMAARM_HSTART, 1); in boot_firmware() [all …]
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H A D | imx_gpt.c | 50 #define WRITE4(_sc, _r, _v) \ macro 191 WRITE4(sc, IMX_GPT_CR, 0); in imx_gpt_attach() 192 WRITE4(sc, IMX_GPT_IR, 0); in imx_gpt_attach() 202 WRITE4(sc, IMX_GPT_CR, ctlreg); in imx_gpt_attach() 225 WRITE4(sc, IMX_GPT_PR, prescale); in imx_gpt_attach() 228 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); in imx_gpt_attach() 255 WRITE4(sc, IMX_GPT_OCR3, 0); in imx_gpt_attach() 298 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); in imx_gpt_timer_start() 304 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); in imx_gpt_timer_start() 328 WRITE4(sc, IMX_GPT_IR, sc->ir_reg); in imx_gpt_timer_stop() [all …]
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H A D | imx_gpio.c | 71 #define WRITE4(_sc, _r, _v) \ macro 76 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 382 WRITE4(sc, reg, wrk); in gpio_pic_setup_intr() 384 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); in gpio_pic_setup_intr() 436 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_filter() 450 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); in gpio_pic_post_ithread() 707 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_toggle() 730 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_access_32() 771 WRITE4(sc, IMX_GPIO_DR_REG, in imx51_gpio_pin_config_32() 773 WRITE4(sc, IMX_GPIO_OE_REG, in imx51_gpio_pin_config_32() [all …]
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H A D | imx6_audmux.c | 54 #define WRITE4(_sc, _reg, _val) \ macro 105 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg); in audmux_configure() 109 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg); in audmux_configure()
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/freebsd/sys/arm/altera/socfpga/ |
H A D | socfpga_a10_manager.c | 175 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open() 179 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open() 184 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open() 188 WRITE4(sc, IMGCFG_CTRL_00, reg); in fpga_open() 193 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open() 198 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open() 208 WRITE4(sc, IMGCFG_CTRL_00, reg); in fpga_open() 213 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open() 221 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_open() 275 WRITE4(sc, IMGCFG_CTRL_01, reg); in fpga_close() [all …]
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H A D | socfpga_manager.c | 224 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open() 229 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open() 234 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open() 245 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open() 253 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS); in fpga_open() 258 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_open() 270 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses() 273 WRITE4(sc, FPGAMGR_DCLKCNT, npulses); in fpga_wait_dclk_pulses() 279 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); in fpga_wait_dclk_pulses() 310 WRITE4(sc, FPGAMGR_CTRL, reg); in fpga_close() [all …]
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/freebsd/sys/dev/dwc/ |
H A D | dwc1000_core.c | 103 WRITE4(sc, GMII_ADDRESS, mii); in dwc1000_miibus_read_reg() 130 WRITE4(sc, GMII_DATA, val); in dwc1000_miibus_write_reg() 131 WRITE4(sc, GMII_ADDRESS, mii); in dwc1000_miibus_write_reg() 192 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_miibus_statchg() 201 WRITE4(sc, FLOW_CONTROL, reg); in dwc1000_miibus_statchg() 217 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_core_setup() 231 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_enable_mac() 245 WRITE4(sc, MAC_CONFIGURATION, reg); in dwc1000_enable_csum_offload() 342 WRITE4(sc, MAC_ADDRESS_LOW(0), lo); in dwc1000_setup_rxfilter() 399 WRITE4(sc, MMC_CONTROL, reg); in dwc1000_clear_stats() [all …]
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H A D | dwc1000_dma.c | 505 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); in dma1000_txstart() 556 WRITE4(sc, OPERATION_MODE, reg); in dma1000_start() 558 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); in dma1000_start() 563 WRITE4(sc, OPERATION_MODE, reg); in dma1000_start() 579 WRITE4(sc, OPERATION_MODE, reg); in dma1000_stop() 584 WRITE4(sc, OPERATION_MODE, reg); in dma1000_stop() 589 WRITE4(sc, OPERATION_MODE, reg); in dma1000_stop() 600 WRITE4(sc, BUS_MODE, reg); in dma1000_reset() 638 WRITE4(sc, BUS_MODE, reg); in dma1000_init() 649 WRITE4(sc, OPERATION_MODE, reg); in dma1000_init() [all …]
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/freebsd/sys/dev/mmc/host/ |
H A D | dwmmc.c | 216 WRITE4(sc, SDMMC_CTRL, reg); in dwmmc_ctrl_reset() 838 WRITE4(sc, SDMMC_CLKENA, 0); in dwmmc_setup_bus() 839 WRITE4(sc, SDMMC_CLKSRC, 0); in dwmmc_setup_bus() 888 WRITE4(sc, SDMMC_PWREN, 0); in dwmmc_update_ios() 891 WRITE4(sc, SDMMC_PWREN, 1); in dwmmc_update_ios() 902 WRITE4(sc, SDMMC_CTYPE, 0); in dwmmc_update_ios() 957 WRITE4(sc, SDMMC_CTRL, reg); in dma_stop() 962 WRITE4(sc, SDMMC_BMOD, reg); in dma_stop() 1006 WRITE4(sc, SDMMC_CTRL, reg); in dma_prepare() 1011 WRITE4(sc, SDMMC_BMOD, reg); in dma_prepare() [all …]
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H A D | dwmmc_samsung.c | 45 #define WRITE4(_sc, _reg, _val) \ macro 101 WRITE4(sc, EMMCP_MPSBEGIN0, 0); in samsung_dwmmc_attach() 102 WRITE4(sc, EMMCP_SEND0, 0); in samsung_dwmmc_attach() 103 WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT | in samsung_dwmmc_attach()
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/freebsd/sys/dev/xilinx/ |
H A D | axi_quad_spi.c | 66 #define WRITE4(_sc, _reg, _val) \ macro 140 WRITE4(sc, SPI_SRR, SRR_RESET); in spi_attach() 145 WRITE4(sc, SPI_CR, reg); in spi_attach() 146 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ in spi_attach() 149 WRITE4(sc, SPI_CR, reg); in spi_attach() 163 WRITE4(sc, SPI_DTR, out_buf[i]); in spi_txrx() 198 WRITE4(sc, SPI_SSR, reg); in spi_transfer() 209 WRITE4(sc, SPI_SSR, reg); in spi_transfer()
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H A D | if_xae.c | 349 WRITE4(sc, XAE_TC, reg); in xae_stop_locked() 354 WRITE4(sc, XAE_RCW1, reg); in xae_stop_locked() 450 WRITE4(sc, XAE_TC, TC_TX); in xae_init_locked() 527 WRITE4(sc, XAE_FFC, reg); in xae_write_maddr() 533 WRITE4(sc, XAE_FFV(0), reg); in xae_write_maddr() 537 WRITE4(sc, XAE_FFV(1), reg); in xae_write_maddr() 558 WRITE4(sc, XAE_FFC, reg); in xae_setup_rxfilter() 562 WRITE4(sc, XAE_FFC, reg); in xae_setup_rxfilter() 574 WRITE4(sc, XAE_UAW0, reg); in xae_setup_rxfilter() 578 WRITE4(sc, XAE_UAW1, reg); in xae_setup_rxfilter() [all …]
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/freebsd/sys/dev/clk/rockchip/ |
H A D | rk_clk_pll.c | 53 #define WRITE4(_clk, off, val) \ macro 89 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate() 150 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux() 231 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq() 246 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq() 264 WRITE4(clk, sc->base_offset + 12, in rk3066_clk_pll_set_freq() 290 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq() 454 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq() 461 WRITE4(clk, sc->base_offset, reg); in rk3328_clk_pll_set_freq() 493 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq() [all …]
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/freebsd/sys/dev/altera/pio/ |
H A D | pio.c | 60 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro 125 WRITE4(sc, PIO_OUTSET, bit); in pio_set() 127 WRITE4(sc, PIO_OUTCLR, bit); in pio_set() 139 WRITE4(sc, PIO_INT_MASK, mask); in pio_configure() 140 WRITE4(sc, PIO_DIR, dir); in pio_configure()
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/freebsd/sys/dev/clk/allwinner/ |
H A D | aw_clk_nkmp.c | 62 #define WRITE4(_clk, off, val) \ macro 111 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_gate() 132 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_mux() 205 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale() 212 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale() 220 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale() 226 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale() 233 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq_scale() 293 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq() 301 WRITE4(clk, sc->offset, val); in aw_clk_nkmp_set_freq()
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H A D | aw_clk_mipi.c | 65 #define WRITE4(_clk, off, val) \ macro 106 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_gate() 175 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq() 188 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq() 192 WRITE4(clk, sc->offset, val); in aw_clk_mipi_set_freq()
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/freebsd/sys/arm/ti/clk/ |
H A D | ti_clk_clkctrl.c | 70 #define WRITE4(_clk, off, val) \ macro 114 WRITE4(clk, sc->register_offset, val); in ti_clkctrl_set_gdbclk_gate() 153 WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE); in ti_clkctrl_set_gate() 155 WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE); in ti_clkctrl_set_gate()
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/freebsd/sys/dev/clk/starfive/ |
H A D | jh7110_clk.c | 47 #define WRITE4(_sc, _off, _val) \ macro 74 WRITE4(sc, offset, regvalue); in jh7110_reset_assert() 147 WRITE4(sc, sc_clk->offset, reg); in jh7110_clk_set_gate() 175 WRITE4(sc, sc_clk->offset, reg); in jh7110_clk_set_mux() 232 WRITE4(sc, sc_clk->offset, divisor); in jh7110_clk_set_freq()
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/freebsd/sys/dev/agp/ |
H A D | agp_ati.c | 58 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro 228 WRITE4(ATI_GART_FEATURE_ID, 0x00060000); in agp_ati_attach() 233 WRITE4(ATI_GART_BASE, sc->ag_pdir); in agp_ati_attach() 254 WRITE4(ATI_GART_BASE, 0); in agp_ati_detach() 341 WRITE4(ATI_GART_CACHE_CNTRL, 1); in agp_ati_flush_tlb()
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