1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * This file is available to you under your choice of the following two
7 * licenses:
8 *
9 * License 1: GPLv2
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Redistribution and use in source and binary forms, with or without
60 * modification, are permitted provided that the following conditions are met:
61 * * Redistributions of source code must retain the above copyright
62 * notice, this list of conditions and the following disclaimer.
63 * * Redistributions in binary form must reproduce the above copyright
64 * notice, this list of conditions and the following disclaimer in the
65 * documentation and/or other materials provided with the distribution.
66 * * Neither the name of Advanced Micro Devices, Inc. nor the
67 * names of its contributors may be used to endorse or promote products
68 * derived from this software without specific prior written permission.
69 *
70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 *
81 * This file incorporates work covered by the following copyright and
82 * permission notice:
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
86 * and you.
87 *
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
97 *
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
100 *
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
112 */
113
114 #include <sys/cdefs.h>
115 #include "xgbe.h"
116 #include "xgbe-common.h"
117
118 struct mtx xgbe_phy_comm_lock;
119
120 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
121 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
122 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
123 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
124
125 #define XGBE_MUTEX_RELEASE 0x80000000
126
127 #define XGBE_SFP_DIRECT 7
128 #define GPIO_MASK_WIDTH 4
129
130 /* I2C target addresses */
131 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
132 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
133 #define XGBE_SFP_PHY_ADDRESS 0x56
134 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
135
136 /* SFP sideband signal indicators */
137 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
138 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
139 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
140 #define XGBE_GPIO_NO_RX_LOS BIT(3)
141
142 /* Rate-change complete wait/retry count */
143 #define XGBE_RATECHANGE_COUNT 500
144
145 /* CDR delay values for KR support (in usec) */
146 #define XGBE_CDR_DELAY_INIT 10000
147 #define XGBE_CDR_DELAY_INC 10000
148 #define XGBE_CDR_DELAY_MAX 100000
149
150 /* RRC frequency during link status check */
151 #define XGBE_RRC_FREQUENCY 10
152
153 /* SFP port max PHY probe retries */
154 #define XGBE_SFP_PHY_RETRY_MAX 5
155
156 enum xgbe_port_mode {
157 XGBE_PORT_MODE_RSVD = 0,
158 XGBE_PORT_MODE_BACKPLANE,
159 XGBE_PORT_MODE_BACKPLANE_2500,
160 XGBE_PORT_MODE_1000BASE_T,
161 XGBE_PORT_MODE_1000BASE_X,
162 XGBE_PORT_MODE_NBASE_T,
163 XGBE_PORT_MODE_10GBASE_T,
164 XGBE_PORT_MODE_10GBASE_R,
165 XGBE_PORT_MODE_SFP,
166 XGBE_PORT_MODE_MAX,
167 };
168
169 enum xgbe_conn_type {
170 XGBE_CONN_TYPE_NONE = 0,
171 XGBE_CONN_TYPE_SFP,
172 XGBE_CONN_TYPE_MDIO,
173 XGBE_CONN_TYPE_RSVD1,
174 XGBE_CONN_TYPE_BACKPLANE,
175 XGBE_CONN_TYPE_MAX,
176 };
177
178 /* SFP/SFP+ related definitions */
179 enum xgbe_sfp_comm {
180 XGBE_SFP_COMM_DIRECT = 0,
181 XGBE_SFP_COMM_PCA9545,
182 };
183
184 enum xgbe_sfp_cable {
185 XGBE_SFP_CABLE_UNKNOWN = 0,
186 XGBE_SFP_CABLE_ACTIVE,
187 XGBE_SFP_CABLE_PASSIVE,
188 };
189
190 enum xgbe_sfp_base {
191 XGBE_SFP_BASE_UNKNOWN = 0,
192 XGBE_SFP_BASE_PX,
193 XGBE_SFP_BASE_BX10,
194 XGBE_SFP_BASE_100_FX,
195 XGBE_SFP_BASE_100_LX10,
196 XGBE_SFP_BASE_100_BX,
197 XGBE_SFP_BASE_1000_T,
198 XGBE_SFP_BASE_1000_SX,
199 XGBE_SFP_BASE_1000_LX,
200 XGBE_SFP_BASE_1000_CX,
201 XGBE_SFP_BASE_1000_BX,
202 XGBE_SFP_BASE_10000_SR,
203 XGBE_SFP_BASE_10000_LR,
204 XGBE_SFP_BASE_10000_LRM,
205 XGBE_SFP_BASE_10000_ER,
206 XGBE_SFP_BASE_10000_CR,
207 };
208
209 enum xgbe_sfp_speed {
210 XGBE_SFP_SPEED_UNKNOWN = 0,
211 XGBE_SFP_SPEED_100,
212 XGBE_SFP_SPEED_100_1000,
213 XGBE_SFP_SPEED_1000,
214 XGBE_SFP_SPEED_10000,
215 XGBE_SFP_SPEED_25000,
216 };
217
218 /* SFP Serial ID Base ID values relative to an offset of 0 */
219 #define XGBE_SFP_BASE_ID 0
220 #define XGBE_SFP_ID_SFP 0x03
221
222 #define XGBE_SFP_BASE_EXT_ID 1
223 #define XGBE_SFP_EXT_ID_SFP 0x04
224
225 #define XGBE_SFP_BASE_CV 2
226 #define XGBE_SFP_BASE_CV_CP 0x21
227
228 #define XGBE_SFP_BASE_10GBE_CC 3
229 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
230 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
231 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
232 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
233
234 #define XGBE_SFP_BASE_1GBE_CC 6
235 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
236 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
237 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
238 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
239 #define XGBE_SFP_BASE_100M_CC_LX10 BIT(4)
240 #define XGBE_SFP_BASE_100M_CC_FX BIT(5)
241 #define XGBE_SFP_BASE_CC_BX10 BIT(6)
242 #define XGBE_SFP_BASE_CC_PX BIT(7)
243
244 #define XGBE_SFP_BASE_CABLE 8
245 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
246 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
247
248 #define XGBE_SFP_BASE_BR 12
249 #define XGBE_SFP_BASE_BR_100M_MIN 0x1
250 #define XGBE_SFP_BASE_BR_100M_MAX 0x2
251 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
252 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
253 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
254 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
255 #define XGBE_SFP_BASE_BR_25GBE 0xFF
256
257 /* Single mode, length of fiber in units of km */
258 #define XGBE_SFP_BASE_SM_LEN_KM 14
259 #define XGBE_SFP_BASE_SM_LEN_KM_MIN 0x0A
260
261 /* Single mode, length of fiber in units of 100m */
262 #define XGBE_SFP_BASE_SM_LEN_100M 15
263 #define XGBE_SFP_BASE_SM_LEN_100M_MIN 0x64
264
265 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
266
267 #define XGBE_SFP_BASE_VENDOR_NAME 20
268 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
269 #define XGBE_SFP_BASE_VENDOR_PN 40
270 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
271 #define XGBE_SFP_BASE_VENDOR_REV 56
272 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
273
274 /*
275 * Optical specification compliance - denotes wavelength
276 * for optical tranceivers
277 */
278 #define XGBE_SFP_BASE_OSC 60
279 #define XGBE_SFP_BASE_OSC_LEN 2
280 #define XGBE_SFP_BASE_OSC_1310 0x051E
281
282 #define XGBE_SFP_BASE_CC 63
283
284 /* SFP Serial ID Extended ID values relative to an offset of 64 */
285 #define XGBE_SFP_BASE_VENDOR_SN 4
286 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
287
288 #define XGBE_SFP_EXTD_OPT1 1
289 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
290 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
291
292 #define XGBE_SFP_EXTD_DIAG 28
293 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
294
295 #define XGBE_SFP_EXTD_SFF_8472 30
296
297 #define XGBE_SFP_EXTD_CC 31
298
299 struct xgbe_sfp_eeprom {
300 uint8_t base[64];
301 uint8_t extd[32];
302 uint8_t vendor[32];
303 };
304
305 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
306 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
307 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
308
309 #define XGBE_SFP_EEPROM_BASE_LEN 256
310 #define XGBE_SFP_EEPROM_DIAG_LEN 256
311 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
312 XGBE_SFP_EEPROM_DIAG_LEN)
313
314 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
315 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
316
317 struct xgbe_sfp_ascii {
318 union {
319 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
320 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
321 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
322 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
323 } u;
324 };
325
326 /* MDIO PHY reset types */
327 enum xgbe_mdio_reset {
328 XGBE_MDIO_RESET_NONE = 0,
329 XGBE_MDIO_RESET_I2C_GPIO,
330 XGBE_MDIO_RESET_INT_GPIO,
331 XGBE_MDIO_RESET_MAX,
332 };
333
334 /* Re-driver related definitions */
335 enum xgbe_phy_redrv_if {
336 XGBE_PHY_REDRV_IF_MDIO = 0,
337 XGBE_PHY_REDRV_IF_I2C,
338 XGBE_PHY_REDRV_IF_MAX,
339 };
340
341 enum xgbe_phy_redrv_model {
342 XGBE_PHY_REDRV_MODEL_4223 = 0,
343 XGBE_PHY_REDRV_MODEL_4227,
344 XGBE_PHY_REDRV_MODEL_MAX,
345 };
346
347 enum xgbe_phy_redrv_mode {
348 XGBE_PHY_REDRV_MODE_CX = 5,
349 XGBE_PHY_REDRV_MODE_SR = 9,
350 };
351
352 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
353
354 /* PHY related configuration information */
355 struct xgbe_phy_data {
356 enum xgbe_port_mode port_mode;
357
358 unsigned int port_id;
359
360 unsigned int port_speeds;
361
362 enum xgbe_conn_type conn_type;
363
364 enum xgbe_mode cur_mode;
365 enum xgbe_mode start_mode;
366
367 unsigned int rrc_count;
368
369 unsigned int mdio_addr;
370
371 /* SFP Support */
372 enum xgbe_sfp_comm sfp_comm;
373 unsigned int sfp_mux_address;
374 unsigned int sfp_mux_channel;
375
376 unsigned int sfp_gpio_address;
377 unsigned int sfp_gpio_mask;
378 unsigned int sfp_gpio_inputs;
379 unsigned int sfp_gpio_outputs;
380 unsigned int sfp_gpio_polarity;
381 unsigned int sfp_gpio_configuration;
382 unsigned int sfp_gpio_rx_los;
383 unsigned int sfp_gpio_tx_fault;
384 unsigned int sfp_gpio_mod_absent;
385 unsigned int sfp_gpio_rate_select;
386
387 unsigned int sfp_rx_los;
388 unsigned int sfp_tx_fault;
389 unsigned int sfp_mod_absent;
390 unsigned int sfp_changed;
391 unsigned int sfp_phy_avail;
392 unsigned int sfp_cable_len;
393 enum xgbe_sfp_base sfp_base;
394 enum xgbe_sfp_cable sfp_cable;
395 enum xgbe_sfp_speed sfp_speed;
396 struct xgbe_sfp_eeprom sfp_eeprom;
397
398 /* External PHY support */
399 enum xgbe_mdio_mode phydev_mode;
400 uint32_t phy_id;
401 int phydev;
402 enum xgbe_mdio_reset mdio_reset;
403 unsigned int mdio_reset_addr;
404 unsigned int mdio_reset_gpio;
405 int sfp_phy_retries;
406
407 /* Re-driver support */
408 unsigned int redrv;
409 unsigned int redrv_if;
410 unsigned int redrv_addr;
411 unsigned int redrv_lane;
412 unsigned int redrv_model;
413
414 /* KR AN support */
415 unsigned int phy_cdr_notrack;
416 unsigned int phy_cdr_delay;
417
418 uint8_t port_sfp_inputs;
419 };
420
421 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
422 static int xgbe_phy_reset(struct xgbe_prv_data *pdata);
423 static int axgbe_ifmedia_upd(struct ifnet *ifp);
424 static void axgbe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
425
426 static int
xgbe_phy_i2c_xfer(struct xgbe_prv_data * pdata,struct xgbe_i2c_op * i2c_op)427 xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *i2c_op)
428 {
429 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op));
430 }
431
432 static int
xgbe_phy_redrv_write(struct xgbe_prv_data * pdata,unsigned int reg,unsigned int val)433 xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
434 unsigned int val)
435 {
436 struct xgbe_phy_data *phy_data = pdata->phy_data;
437 struct xgbe_i2c_op i2c_op;
438 __be16 *redrv_val;
439 uint8_t redrv_data[5], csum;
440 unsigned int i, retry;
441 int ret;
442
443 /* High byte of register contains read/write indicator */
444 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
445 redrv_data[1] = reg & 0xff;
446 redrv_val = (__be16 *)&redrv_data[2];
447 *redrv_val = cpu_to_be16(val);
448
449 /* Calculate 1 byte checksum */
450 csum = 0;
451 for (i = 0; i < 4; i++) {
452 csum += redrv_data[i];
453 if (redrv_data[i] > csum)
454 csum++;
455 }
456 redrv_data[4] = ~csum;
457
458 retry = 1;
459 again1:
460 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
461 i2c_op.target = phy_data->redrv_addr;
462 i2c_op.len = sizeof(redrv_data);
463 i2c_op.buf = redrv_data;
464 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
465 if (ret) {
466 if ((ret == -EAGAIN) && retry--)
467 goto again1;
468
469 return (ret);
470 }
471
472 retry = 1;
473 again2:
474 i2c_op.cmd = XGBE_I2C_CMD_READ;
475 i2c_op.target = phy_data->redrv_addr;
476 i2c_op.len = 1;
477 i2c_op.buf = redrv_data;
478 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
479 if (ret) {
480 if ((ret == -EAGAIN) && retry--)
481 goto again2;
482
483 return (ret);
484 }
485
486 if (redrv_data[0] != 0xff) {
487 axgbe_error("Redriver write checksum error\n");
488 ret = -EIO;
489 }
490
491 return (ret);
492 }
493
494 static int
xgbe_phy_i2c_write(struct xgbe_prv_data * pdata,unsigned int target,void * val,unsigned int val_len)495 xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, void *val,
496 unsigned int val_len)
497 {
498 struct xgbe_i2c_op i2c_op;
499 int retry, ret;
500
501 retry = 1;
502 again:
503 /* Write the specfied register */
504 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
505 i2c_op.target = target;
506 i2c_op.len = val_len;
507 i2c_op.buf = val;
508 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
509 if ((ret == -EAGAIN) && retry--)
510 goto again;
511
512 return (ret);
513 }
514
515 static int
xgbe_phy_i2c_read(struct xgbe_prv_data * pdata,unsigned int target,void * reg,unsigned int reg_len,void * val,unsigned int val_len)516 xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg,
517 unsigned int reg_len, void *val, unsigned int val_len)
518 {
519 struct xgbe_i2c_op i2c_op;
520 int retry, ret;
521
522 axgbe_printf(3, "%s: target 0x%x reg_len %d val_len %d\n", __func__,
523 target, reg_len, val_len);
524 retry = 1;
525 again1:
526 /* Set the specified register to read */
527 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
528 i2c_op.target = target;
529 i2c_op.len = reg_len;
530 i2c_op.buf = reg;
531 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
532 axgbe_printf(3, "%s: ret1 %d retry %d\n", __func__, ret, retry);
533 if (ret) {
534 if ((ret == -EAGAIN) && retry--)
535 goto again1;
536
537 return (ret);
538 }
539
540 retry = 1;
541 again2:
542 /* Read the specfied register */
543 i2c_op.cmd = XGBE_I2C_CMD_READ;
544 i2c_op.target = target;
545 i2c_op.len = val_len;
546 i2c_op.buf = val;
547 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
548 axgbe_printf(3, "%s: ret2 %d retry %d\n", __func__, ret, retry);
549 if ((ret == -EAGAIN) && retry--)
550 goto again2;
551
552 return (ret);
553 }
554
555 static int
xgbe_phy_sfp_put_mux(struct xgbe_prv_data * pdata)556 xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
557 {
558 struct xgbe_phy_data *phy_data = pdata->phy_data;
559 struct xgbe_i2c_op i2c_op;
560 uint8_t mux_channel;
561
562 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
563 return (0);
564
565 /* Select no mux channels */
566 mux_channel = 0;
567 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
568 i2c_op.target = phy_data->sfp_mux_address;
569 i2c_op.len = sizeof(mux_channel);
570 i2c_op.buf = &mux_channel;
571
572 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
573 }
574
575 static int
xgbe_phy_sfp_get_mux(struct xgbe_prv_data * pdata)576 xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
577 {
578 struct xgbe_phy_data *phy_data = pdata->phy_data;
579 struct xgbe_i2c_op i2c_op;
580 uint8_t mux_channel;
581
582 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
583 return (0);
584
585 /* Select desired mux channel */
586 mux_channel = 1 << phy_data->sfp_mux_channel;
587 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
588 i2c_op.target = phy_data->sfp_mux_address;
589 i2c_op.len = sizeof(mux_channel);
590 i2c_op.buf = &mux_channel;
591
592 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
593 }
594
595 static void
xgbe_phy_put_comm_ownership(struct xgbe_prv_data * pdata)596 xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
597 {
598 mtx_unlock(&xgbe_phy_comm_lock);
599 }
600
601 static int
xgbe_phy_get_comm_ownership(struct xgbe_prv_data * pdata)602 xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
603 {
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
605 unsigned long timeout;
606 unsigned int mutex_id;
607
608 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
609 * the driver needs to take the software mutex and then the hardware
610 * mutexes before being able to use the busses.
611 */
612 mtx_lock(&xgbe_phy_comm_lock);
613
614 /* Clear the mutexes */
615 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
616 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
617
618 /* Mutex formats are the same for I2C and MDIO/GPIO */
619 mutex_id = 0;
620 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
621 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
622
623 timeout = ticks + (5 * hz);
624 while (ticks < timeout) {
625 /* Must be all zeroes in order to obtain the mutex */
626 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
627 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
628 DELAY(200);
629 continue;
630 }
631
632 /* Obtain the mutex */
633 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
634 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
635
636 return (0);
637 }
638
639 mtx_unlock(&xgbe_phy_comm_lock);
640
641 axgbe_error("unable to obtain hardware mutexes\n");
642
643 return (-ETIMEDOUT);
644 }
645
646 static int
xgbe_phy_mdio_mii_write(struct xgbe_prv_data * pdata,int addr,int reg,uint16_t val)647 xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,
648 uint16_t val)
649 {
650 struct xgbe_phy_data *phy_data = pdata->phy_data;
651
652 if (reg & MII_ADDR_C45) {
653 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
654 return (-ENOTSUP);
655 } else {
656 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
657 return (-ENOTSUP);
658 }
659
660 return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val));
661 }
662
663 static int
xgbe_phy_i2c_mii_write(struct xgbe_prv_data * pdata,int reg,uint16_t val)664 xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val)
665 {
666 __be16 *mii_val;
667 uint8_t mii_data[3];
668 int ret;
669
670 ret = xgbe_phy_sfp_get_mux(pdata);
671 if (ret)
672 return (ret);
673
674 mii_data[0] = reg & 0xff;
675 mii_val = (__be16 *)&mii_data[1];
676 *mii_val = cpu_to_be16(val);
677
678 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
679 mii_data, sizeof(mii_data));
680
681 xgbe_phy_sfp_put_mux(pdata);
682
683 return (ret);
684 }
685
686 int
xgbe_phy_mii_write(struct xgbe_prv_data * pdata,int addr,int reg,uint16_t val)687 xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val)
688 {
689 struct xgbe_phy_data *phy_data = pdata->phy_data;
690 int ret;
691
692 axgbe_printf(3, "%s: addr %d reg %d val %#x\n", __func__, addr, reg, val);
693 ret = xgbe_phy_get_comm_ownership(pdata);
694 if (ret)
695 return (ret);
696
697 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
698 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
699 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
700 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
701 else
702 ret = -ENOTSUP;
703
704 xgbe_phy_put_comm_ownership(pdata);
705
706 return (ret);
707 }
708
709 static int
xgbe_phy_mdio_mii_read(struct xgbe_prv_data * pdata,int addr,int reg)710 xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
711 {
712 struct xgbe_phy_data *phy_data = pdata->phy_data;
713
714 if (reg & MII_ADDR_C45) {
715 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
716 return (-ENOTSUP);
717 } else {
718 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
719 return (-ENOTSUP);
720 }
721
722 return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg));
723 }
724
725 static int
xgbe_phy_i2c_mii_read(struct xgbe_prv_data * pdata,int reg)726 xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
727 {
728 __be16 mii_val;
729 uint8_t mii_reg;
730 int ret;
731
732 ret = xgbe_phy_sfp_get_mux(pdata);
733 if (ret)
734 return (ret);
735
736 mii_reg = reg;
737 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
738 &mii_reg, sizeof(mii_reg),
739 &mii_val, sizeof(mii_val));
740 if (!ret)
741 ret = be16_to_cpu(mii_val);
742
743 xgbe_phy_sfp_put_mux(pdata);
744
745 return (ret);
746 }
747
748 int
xgbe_phy_mii_read(struct xgbe_prv_data * pdata,int addr,int reg)749 xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
750 {
751 struct xgbe_phy_data *phy_data = pdata->phy_data;
752 int ret;
753
754 axgbe_printf(3, "%s: addr %d reg %d\n", __func__, addr, reg);
755 ret = xgbe_phy_get_comm_ownership(pdata);
756 if (ret)
757 return (ret);
758
759 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
760 ret = xgbe_phy_i2c_mii_read(pdata, reg);
761 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
762 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
763 else
764 ret = -ENOTSUP;
765
766 xgbe_phy_put_comm_ownership(pdata);
767
768 return (ret);
769 }
770
771 static void
xgbe_phy_sfp_phy_settings(struct xgbe_prv_data * pdata)772 xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
773 {
774 struct xgbe_phy_data *phy_data = pdata->phy_data;
775
776 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
777 return;
778
779 XGBE_ZERO_SUP(&pdata->phy);
780
781 if (phy_data->sfp_mod_absent) {
782 pdata->phy.speed = SPEED_UNKNOWN;
783 pdata->phy.duplex = DUPLEX_UNKNOWN;
784 pdata->phy.autoneg = AUTONEG_ENABLE;
785 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
786
787 XGBE_SET_SUP(&pdata->phy, Autoneg);
788 XGBE_SET_SUP(&pdata->phy, Pause);
789 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
790 XGBE_SET_SUP(&pdata->phy, TP);
791 XGBE_SET_SUP(&pdata->phy, FIBRE);
792
793 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
794
795 return;
796 }
797
798 switch (phy_data->sfp_base) {
799 case XGBE_SFP_BASE_100_FX:
800 case XGBE_SFP_BASE_100_LX10:
801 case XGBE_SFP_BASE_100_BX:
802 pdata->phy.speed = SPEED_100;
803 pdata->phy.duplex = DUPLEX_FULL;
804 pdata->phy.autoneg = AUTONEG_DISABLE;
805 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
806 break;
807 case XGBE_SFP_BASE_1000_T:
808 case XGBE_SFP_BASE_1000_SX:
809 case XGBE_SFP_BASE_1000_LX:
810 case XGBE_SFP_BASE_1000_CX:
811 pdata->phy.speed = SPEED_UNKNOWN;
812 pdata->phy.duplex = DUPLEX_UNKNOWN;
813 pdata->phy.autoneg = AUTONEG_ENABLE;
814 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
815 XGBE_SET_SUP(&pdata->phy, Autoneg);
816 XGBE_SET_SUP(&pdata->phy, Pause);
817 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
818 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
819 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
820 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
821 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
822 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
823 } else {
824 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
825 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
826 }
827 break;
828 case XGBE_SFP_BASE_1000_BX:
829 case XGBE_SFP_BASE_PX:
830 pdata->phy.speed = SPEED_1000;
831 pdata->phy.duplex = DUPLEX_FULL;
832 pdata->phy.autoneg = AUTONEG_DISABLE;
833 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
834 break;
835 case XGBE_SFP_BASE_10000_SR:
836 case XGBE_SFP_BASE_10000_LR:
837 case XGBE_SFP_BASE_10000_LRM:
838 case XGBE_SFP_BASE_10000_ER:
839 case XGBE_SFP_BASE_10000_CR:
840 pdata->phy.speed = SPEED_10000;
841 pdata->phy.duplex = DUPLEX_FULL;
842 pdata->phy.autoneg = AUTONEG_DISABLE;
843 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
844 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
845 switch (phy_data->sfp_base) {
846 case XGBE_SFP_BASE_10000_SR:
847 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
848 break;
849 case XGBE_SFP_BASE_10000_LR:
850 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
851 break;
852 case XGBE_SFP_BASE_10000_LRM:
853 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
854 break;
855 case XGBE_SFP_BASE_10000_ER:
856 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
857 break;
858 case XGBE_SFP_BASE_10000_CR:
859 XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full);
860 break;
861 default:
862 break;
863 }
864 }
865 break;
866 default:
867 pdata->phy.speed = SPEED_UNKNOWN;
868 pdata->phy.duplex = DUPLEX_UNKNOWN;
869 pdata->phy.autoneg = AUTONEG_DISABLE;
870 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
871 break;
872 }
873
874 switch (phy_data->sfp_base) {
875 case XGBE_SFP_BASE_1000_T:
876 case XGBE_SFP_BASE_1000_CX:
877 case XGBE_SFP_BASE_10000_CR:
878 XGBE_SET_SUP(&pdata->phy, TP);
879 break;
880 default:
881 XGBE_SET_SUP(&pdata->phy, FIBRE);
882 break;
883 }
884
885 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
886
887 axgbe_printf(1, "%s: link speed %d spf_base 0x%x pause_autoneg %d "
888 "advert 0x%x support 0x%x\n", __func__, pdata->phy.speed,
889 phy_data->sfp_base, pdata->phy.pause_autoneg,
890 pdata->phy.advertising, pdata->phy.supported);
891 }
892
893 static bool
xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom * sfp_eeprom,enum xgbe_sfp_speed sfp_speed)894 xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
895 enum xgbe_sfp_speed sfp_speed)
896 {
897 uint8_t *sfp_base, min, max;
898
899 sfp_base = sfp_eeprom->base;
900
901 switch (sfp_speed) {
902 case XGBE_SFP_SPEED_100:
903 min = XGBE_SFP_BASE_BR_100M_MIN;
904 max = XGBE_SFP_BASE_BR_100M_MAX;
905 break;
906 case XGBE_SFP_SPEED_1000:
907 min = XGBE_SFP_BASE_BR_1GBE_MIN;
908 max = XGBE_SFP_BASE_BR_1GBE_MAX;
909 break;
910 case XGBE_SFP_SPEED_10000:
911 min = XGBE_SFP_BASE_BR_10GBE_MIN;
912 max = XGBE_SFP_BASE_BR_10GBE_MAX;
913 break;
914 case XGBE_SFP_SPEED_25000:
915 min = XGBE_SFP_BASE_BR_25GBE;
916 max = XGBE_SFP_BASE_BR_25GBE;
917 break;
918 default:
919 return (false);
920 }
921
922 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
923 (sfp_base[XGBE_SFP_BASE_BR] <= max));
924 }
925
926 static void
xgbe_phy_free_phy_device(struct xgbe_prv_data * pdata)927 xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
928 {
929 struct xgbe_phy_data *phy_data = pdata->phy_data;
930
931 if (phy_data->phydev)
932 phy_data->phydev = 0;
933
934 if (pdata->axgbe_miibus != NULL) {
935 device_delete_child(pdata->dev, pdata->axgbe_miibus);
936 pdata->axgbe_miibus = NULL;
937 }
938 }
939
940 static bool
xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data * pdata)941 xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
942 {
943 struct xgbe_phy_data *phy_data = pdata->phy_data;
944 unsigned int phy_id = phy_data->phy_id;
945
946 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
947 return (false);
948
949 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
950 return (false);
951
952 /* Enable Base-T AN */
953 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001);
954 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
955 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000);
956
957 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
958 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084);
959 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00);
960 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140);
961 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01);
962 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
963
964 axgbe_printf(3, "Finisar PHY quirk in place\n");
965
966 return (true);
967 }
968
969 static bool
xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data * pdata)970 xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
971 {
972 struct xgbe_phy_data *phy_data = pdata->phy_data;
973 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
974 unsigned int phy_id = phy_data->phy_id;
975 int reg;
976
977 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
978 return (false);
979
980 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
981 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
982 return (false);
983
984 /* For Bel-Fuse, use the extra AN flag */
985 pdata->an_again = 1;
986
987 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
988 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
989 return (false);
990
991 if ((phy_id & 0xfffffff0) != 0x03625d10)
992 return (false);
993
994 /* Disable RGMII mode */
995 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007);
996 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);
997 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);
998
999 /* Enable fiber register bank */
1000 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1001 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1002 reg &= 0x03ff;
1003 reg &= ~0x0001;
1004 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1005 reg | 0x0001);
1006
1007 /* Power down SerDes */
1008 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1009 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);
1010
1011 /* Configure SGMII-to-Copper mode */
1012 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1013 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1014 reg &= 0x03ff;
1015 reg &= ~0x0006;
1016 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1017 reg | 0x0004);
1018
1019 /* Power up SerDes */
1020 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1021 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1022
1023 /* Enable copper register bank */
1024 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
1025 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
1026 reg &= 0x03ff;
1027 reg &= ~0x0001;
1028 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
1029 reg);
1030
1031 /* Power up SerDes */
1032 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
1033 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
1034
1035 axgbe_printf(3, "BelFuse PHY quirk in place\n");
1036
1037 return (true);
1038 }
1039
1040 static void
xgbe_phy_external_phy_quirks(struct xgbe_prv_data * pdata)1041 xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
1042 {
1043 if (xgbe_phy_belfuse_phy_quirks(pdata))
1044 return;
1045
1046 if (xgbe_phy_finisar_phy_quirks(pdata))
1047 return;
1048 }
1049
1050 static int
xgbe_get_phy_id(struct xgbe_prv_data * pdata)1051 xgbe_get_phy_id(struct xgbe_prv_data *pdata)
1052 {
1053 struct xgbe_phy_data *phy_data = pdata->phy_data;
1054 uint32_t oui, model, phy_id1, phy_id2;
1055 int phy_reg;
1056
1057 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02);
1058 if (phy_reg < 0)
1059 return (-EIO);
1060
1061 phy_id1 = (phy_reg & 0xffff);
1062 phy_data->phy_id = (phy_reg & 0xffff) << 16;
1063
1064 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03);
1065 if (phy_reg < 0)
1066 return (-EIO);
1067
1068 phy_id2 = (phy_reg & 0xffff);
1069 phy_data->phy_id |= (phy_reg & 0xffff);
1070
1071 oui = MII_OUI(phy_id1, phy_id2);
1072 model = MII_MODEL(phy_id2);
1073
1074 axgbe_printf(2, "%s: phy_id1: 0x%x phy_id2: 0x%x oui: %#x model %#x\n",
1075 __func__, phy_id1, phy_id2, oui, model);
1076
1077 return (0);
1078 }
1079
1080 static int
xgbe_phy_find_phy_device(struct xgbe_prv_data * pdata)1081 xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
1082 {
1083 struct xgbe_phy_data *phy_data = pdata->phy_data;
1084 int ret;
1085
1086 axgbe_printf(2, "%s: phydev %d phydev_mode %d sfp_phy_avail %d phy_id "
1087 "0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode,
1088 phy_data->sfp_phy_avail, phy_data->phy_id);
1089
1090 /* If we already have a PHY, just return */
1091 if (phy_data->phydev) {
1092 axgbe_printf(3, "%s: phy present already\n", __func__);
1093 return (0);
1094 }
1095
1096 /* Clear the extra AN flag */
1097 pdata->an_again = 0;
1098
1099 /* Check for the use of an external PHY */
1100 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
1101 axgbe_printf(3, "%s: phydev_mode %d\n", __func__,
1102 phy_data->phydev_mode);
1103 return (0);
1104 }
1105
1106 /* For SFP, only use an external PHY if available */
1107 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1108 !phy_data->sfp_phy_avail) {
1109 axgbe_printf(3, "%s: port_mode %d avail %d\n", __func__,
1110 phy_data->port_mode, phy_data->sfp_phy_avail);
1111 return (0);
1112 }
1113
1114 /* Set the proper MDIO mode for the PHY */
1115 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1116 phy_data->phydev_mode);
1117 if (ret) {
1118 axgbe_error("mdio port/clause not compatible (%u/%u) ret %d\n",
1119 phy_data->mdio_addr, phy_data->phydev_mode, ret);
1120 return (ret);
1121 }
1122
1123 ret = xgbe_get_phy_id(pdata);
1124 if (ret)
1125 return (ret);
1126 axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id);
1127
1128 phy_data->phydev = 1;
1129 xgbe_phy_external_phy_quirks(pdata);
1130
1131 return (0);
1132 }
1133
1134 static void
xgbe_phy_sfp_external_phy(struct xgbe_prv_data * pdata)1135 xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1136 {
1137 struct xgbe_phy_data *phy_data = pdata->phy_data;
1138 int ret;
1139
1140 axgbe_printf(3, "%s: sfp_changed: 0x%x\n", __func__,
1141 phy_data->sfp_changed);
1142 if (!phy_data->sfp_phy_retries && !phy_data->sfp_changed)
1143 return;
1144
1145 phy_data->sfp_phy_avail = 0;
1146
1147 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1148 return;
1149
1150 /* Check access to the PHY by reading CTRL1 */
1151 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1152 if (ret < 0) {
1153 phy_data->sfp_phy_retries++;
1154 if (phy_data->sfp_phy_retries >= XGBE_SFP_PHY_RETRY_MAX)
1155 phy_data->sfp_phy_retries = 0;
1156 axgbe_printf(1, "%s: ext phy fail %d. retrying.\n", __func__, ret);
1157 return;
1158 }
1159
1160 /* Successfully accessed the PHY */
1161 phy_data->sfp_phy_avail = 1;
1162 axgbe_printf(3, "Successfully accessed External PHY\n");
1163
1164 /* Attach external PHY to the miibus */
1165 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
1166 (ifm_change_cb_t)axgbe_ifmedia_upd,
1167 (ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK,
1168 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
1169
1170 if (ret) {
1171 axgbe_error("mii attach failed with err=(%d)\n", ret);
1172 }
1173 }
1174
1175 static bool
xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data * phy_data)1176 xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1177 {
1178 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1179
1180 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1181 return (false);
1182
1183 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1184 return (false);
1185
1186 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1187 return (true);
1188
1189 return (false);
1190 }
1191
1192 static bool
xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data * phy_data)1193 xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1194 {
1195 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1196
1197 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1198 return (false);
1199
1200 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1201 return (false);
1202
1203 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1204 return (true);
1205
1206 return (false);
1207 }
1208
1209 static bool
xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data * phy_data)1210 xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1211 {
1212 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1213 return (false);
1214
1215 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1216 return (true);
1217
1218 return (false);
1219 }
1220
1221 static void
xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data * pdata)1222 xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1223 {
1224 struct xgbe_phy_data *phy_data = pdata->phy_data;
1225 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1226 uint8_t *sfp_base;
1227 uint16_t wavelen = 0;
1228
1229 sfp_base = sfp_eeprom->base;
1230
1231 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) {
1232 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_ID]);
1233 return;
1234 }
1235
1236 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) {
1237 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_EXT_ID]);
1238 return;
1239 }
1240
1241 /* Update transceiver signals (eeprom extd/options) */
1242 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1243 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1244
1245 /* Assume ACTIVE cable unless told it is PASSIVE */
1246 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1247 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1248 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1249 } else
1250 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1251
1252 wavelen = (sfp_base[XGBE_SFP_BASE_OSC] << 8) | sfp_base[XGBE_SFP_BASE_OSC + 1];
1253
1254 /*
1255 * Determine the type of SFP. Certain 10G SFP+ modules read as
1256 * 1000BASE-CX. To prevent 10G DAC cables to be recognized as
1257 * 1G, we first check if it is a DAC and the bitrate is 10G.
1258 * If it's greater than 10G, we assume the DAC is capable
1259 * of multiple bitrates, set the MAC to 10G and hope for the best.
1260 */
1261 if (((sfp_base[XGBE_SFP_BASE_CV] & XGBE_SFP_BASE_CV_CP) ||
1262 (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE)) &&
1263 (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000) ||
1264 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_25000)))
1265 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1266 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1267 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1268 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1269 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1270 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1271 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1272 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1273 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1274 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1275 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1276 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1277 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1278 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1279 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1280 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1281 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1282 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_100M_CC_LX10)
1283 phy_data->sfp_base = XGBE_SFP_BASE_100_LX10;
1284 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_100M_CC_FX)
1285 phy_data->sfp_base = XGBE_SFP_BASE_100_FX;
1286 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_CC_BX10) {
1287 /* BX10 can be either 100 or 1000 */
1288 if (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_100)) {
1289 phy_data->sfp_base = XGBE_SFP_BASE_100_BX;
1290 } else {
1291 /* default to 1000 */
1292 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX;
1293 }
1294 } else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_CC_PX)
1295 phy_data->sfp_base = XGBE_SFP_BASE_PX;
1296 else if (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_1000)
1297 && (sfp_base[XGBE_SFP_BASE_SM_LEN_KM] >= XGBE_SFP_BASE_SM_LEN_KM_MIN
1298 || sfp_base[XGBE_SFP_BASE_SM_LEN_100M] >= XGBE_SFP_BASE_SM_LEN_100M_MIN)
1299 && wavelen >= XGBE_SFP_BASE_OSC_1310)
1300 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX;
1301 else if (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_100)
1302 && (sfp_base[XGBE_SFP_BASE_SM_LEN_KM] >= XGBE_SFP_BASE_SM_LEN_KM_MIN
1303 || sfp_base[XGBE_SFP_BASE_SM_LEN_100M] >= XGBE_SFP_BASE_SM_LEN_100M_MIN)
1304 && wavelen >= XGBE_SFP_BASE_OSC_1310)
1305 phy_data->sfp_base = XGBE_SFP_BASE_100_BX;
1306
1307 switch (phy_data->sfp_base) {
1308 case XGBE_SFP_BASE_100_FX:
1309 case XGBE_SFP_BASE_100_LX10:
1310 case XGBE_SFP_BASE_100_BX:
1311 phy_data->sfp_speed = XGBE_SFP_SPEED_100;
1312 case XGBE_SFP_BASE_1000_T:
1313 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1314 break;
1315 case XGBE_SFP_BASE_PX:
1316 case XGBE_SFP_BASE_1000_SX:
1317 case XGBE_SFP_BASE_1000_LX:
1318 case XGBE_SFP_BASE_1000_CX:
1319 case XGBE_SFP_BASE_1000_BX:
1320 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1321 break;
1322 case XGBE_SFP_BASE_10000_SR:
1323 case XGBE_SFP_BASE_10000_LR:
1324 case XGBE_SFP_BASE_10000_LRM:
1325 case XGBE_SFP_BASE_10000_ER:
1326 case XGBE_SFP_BASE_10000_CR:
1327 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1328 break;
1329 default:
1330 break;
1331 }
1332 axgbe_printf(3, "%s: sfp_base: 0x%x sfp_speed: 0x%x sfp_cable: 0x%x "
1333 "rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base,
1334 phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los,
1335 phy_data->sfp_tx_fault);
1336 }
1337
1338 static void
xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data * pdata,struct xgbe_sfp_eeprom * sfp_eeprom)1339 xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1340 struct xgbe_sfp_eeprom *sfp_eeprom)
1341 {
1342 struct xgbe_sfp_ascii sfp_ascii;
1343 char *sfp_data = (char *)&sfp_ascii;
1344
1345 axgbe_printf(0, "SFP detected:\n");
1346 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1347 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1348 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1349 axgbe_printf(0, " vendor: %s\n",
1350 sfp_data);
1351
1352 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1353 XGBE_SFP_BASE_VENDOR_PN_LEN);
1354 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1355 axgbe_printf(0, " part number: %s\n",
1356 sfp_data);
1357
1358 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1359 XGBE_SFP_BASE_VENDOR_REV_LEN);
1360 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1361 axgbe_printf(0, " revision level: %s\n",
1362 sfp_data);
1363
1364 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1365 XGBE_SFP_BASE_VENDOR_SN_LEN);
1366 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1367 axgbe_printf(0, " serial number: %s\n",
1368 sfp_data);
1369 }
1370
1371 static bool
xgbe_phy_sfp_verify_eeprom(uint8_t cc_in,uint8_t * buf,unsigned int len)1372 xgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, unsigned int len)
1373 {
1374 uint8_t cc;
1375
1376 for (cc = 0; len; buf++, len--)
1377 cc += *buf;
1378
1379 return ((cc == cc_in) ? true : false);
1380 }
1381
1382 static void
dump_sfp_eeprom(struct xgbe_prv_data * pdata,uint8_t * sfp_base)1383 dump_sfp_eeprom(struct xgbe_prv_data *pdata, uint8_t *sfp_base)
1384 {
1385 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_ID] : 0x%04x\n",
1386 sfp_base[XGBE_SFP_BASE_ID]);
1387 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_EXT_ID] : 0x%04x\n",
1388 sfp_base[XGBE_SFP_BASE_EXT_ID]);
1389 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_CABLE] : 0x%04x\n",
1390 sfp_base[XGBE_SFP_BASE_CABLE]);
1391 }
1392
1393 static int
xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data * pdata)1394 xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1395 {
1396 struct xgbe_phy_data *phy_data = pdata->phy_data;
1397 struct xgbe_sfp_eeprom sfp_eeprom, *eeprom;
1398 uint8_t eeprom_addr, *base;
1399 int ret;
1400
1401 ret = xgbe_phy_sfp_get_mux(pdata);
1402 if (ret) {
1403 axgbe_error("I2C error setting SFP MUX\n");
1404 return (ret);
1405 }
1406
1407 /* Read the SFP serial ID eeprom */
1408 eeprom_addr = 0;
1409 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1410 &eeprom_addr, sizeof(eeprom_addr),
1411 &sfp_eeprom, sizeof(sfp_eeprom));
1412
1413 if (ret) {
1414 axgbe_error("I2C error reading SFP EEPROM\n");
1415 goto put;
1416 }
1417
1418 eeprom = &sfp_eeprom;
1419 base = eeprom->base;
1420 dump_sfp_eeprom(pdata, base);
1421
1422 /* Validate the contents read */
1423 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1424 sfp_eeprom.base, sizeof(sfp_eeprom.base) - 1)) {
1425 axgbe_error("verify eeprom base failed\n");
1426 ret = -EINVAL;
1427 goto put;
1428 }
1429
1430 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1431 sfp_eeprom.extd, sizeof(sfp_eeprom.extd) - 1)) {
1432 axgbe_error("verify eeprom extd failed\n");
1433 ret = -EINVAL;
1434 goto put;
1435 }
1436
1437 /* Check for an added or changed SFP */
1438 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1439 phy_data->sfp_changed = 1;
1440
1441 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1442
1443 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1444
1445 xgbe_phy_free_phy_device(pdata);
1446 } else
1447 phy_data->sfp_changed = 0;
1448
1449 put:
1450 xgbe_phy_sfp_put_mux(pdata);
1451
1452 return (ret);
1453 }
1454
1455 static void
xgbe_phy_sfp_signals(struct xgbe_prv_data * pdata)1456 xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1457 {
1458 struct xgbe_phy_data *phy_data = pdata->phy_data;
1459 uint8_t gpio_reg, gpio_ports[2];
1460 int ret, prev_sfp_inputs = phy_data->port_sfp_inputs;
1461 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1462
1463 /* Read the input port registers */
1464 axgbe_printf(3, "%s: befor sfp_mod:%d sfp_gpio_address:0x%x\n",
1465 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address);
1466
1467 ret = xgbe_phy_sfp_get_mux(pdata);
1468 if (ret) {
1469 axgbe_error("I2C error setting SFP MUX\n");
1470 return;
1471 }
1472
1473 gpio_reg = 0;
1474 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg,
1475 sizeof(gpio_reg), gpio_ports, sizeof(gpio_ports));
1476 if (ret) {
1477 axgbe_error("%s: I2C error reading SFP GPIO addr:0x%x\n",
1478 __func__, phy_data->sfp_gpio_address);
1479 goto put_mux;
1480 }
1481
1482 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1483 phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F;
1484
1485 if (prev_sfp_inputs != phy_data->port_sfp_inputs)
1486 axgbe_printf(0, "%s: port_sfp_inputs: 0x%0x\n", __func__,
1487 phy_data->port_sfp_inputs);
1488
1489 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1490
1491 axgbe_printf(3, "%s: after sfp_mod:%d sfp_gpio_inputs:0x%x\n",
1492 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs);
1493
1494 put_mux:
1495 xgbe_phy_sfp_put_mux(pdata);
1496 }
1497
1498 static int
xgbe_read_gpio_expander(struct xgbe_prv_data * pdata)1499 xgbe_read_gpio_expander(struct xgbe_prv_data *pdata)
1500 {
1501 struct xgbe_phy_data *phy_data = pdata->phy_data;
1502 uint8_t gpio_reg, gpio_ports[2];
1503 int ret = 0;
1504
1505 ret = xgbe_phy_sfp_get_mux(pdata);
1506 if (ret) {
1507 axgbe_error("I2C error setting SFP MUX\n");
1508 return (ret);
1509 }
1510
1511 gpio_reg = 2;
1512 for (int i = 0; i < 3; i++) {
1513 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1514 &gpio_reg, sizeof(gpio_reg), gpio_ports, sizeof(gpio_ports));
1515
1516 if (ret) {
1517 axgbe_error("%s: I2C error reading GPIO expander register: %d\n",
1518 __func__, gpio_reg);
1519 goto put_mux;
1520 }
1521
1522 if (gpio_reg == 2)
1523 phy_data->sfp_gpio_outputs = (gpio_ports[1] << 8) | gpio_ports[0];
1524 else if (gpio_reg == 4)
1525 phy_data->sfp_gpio_polarity = (gpio_ports[1] << 8) | gpio_ports[0];
1526 else if (gpio_reg == 6)
1527 phy_data->sfp_gpio_configuration = (gpio_ports[1] << 8) | gpio_ports[0];
1528
1529 memset(gpio_ports, 0, sizeof(gpio_ports));
1530 gpio_reg += 2;
1531 }
1532
1533 put_mux:
1534 xgbe_phy_sfp_put_mux(pdata);
1535
1536 return (ret);
1537 }
1538
1539 static void
xgbe_log_gpio_expander(struct xgbe_prv_data * pdata)1540 xgbe_log_gpio_expander(struct xgbe_prv_data *pdata)
1541 {
1542 struct xgbe_phy_data *phy_data = pdata->phy_data;
1543
1544 axgbe_printf(1, "Input port registers: 0x%x\n", phy_data->sfp_gpio_inputs);
1545 axgbe_printf(1, "Output port registers: 0x%x\n", phy_data->sfp_gpio_outputs);
1546 axgbe_printf(1, "Polarity port registers: 0x%x\n", phy_data->sfp_gpio_polarity);
1547 axgbe_printf(1, "Configuration port registers: 0x%x\n", phy_data->sfp_gpio_configuration);
1548 }
1549
1550 static int
xgbe_phy_validate_gpio_expander(struct xgbe_prv_data * pdata)1551 xgbe_phy_validate_gpio_expander(struct xgbe_prv_data *pdata)
1552 {
1553 struct xgbe_phy_data *phy_data = pdata->phy_data;
1554 uint8_t gpio_data[3] = {0};
1555 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1556 int rx_los_pos = (1 << phy_data->sfp_gpio_rx_los);
1557 int tx_fault_pos = (1 << phy_data->sfp_gpio_tx_fault);
1558 int mod_abs_pos = (1 << phy_data->sfp_gpio_mod_absent);
1559 int port_sfp_pins = (mod_abs_pos | rx_los_pos | tx_fault_pos);
1560 uint16_t config = 0;
1561 int ret = 0;
1562
1563 ret = xgbe_phy_get_comm_ownership(pdata);
1564 if (ret)
1565 return (ret);
1566
1567 ret = xgbe_read_gpio_expander(pdata);
1568 if (ret)
1569 goto put;
1570
1571 ret = xgbe_phy_sfp_get_mux(pdata);
1572 if (ret) {
1573 axgbe_error("I2C error setting SFP MUX\n");
1574 goto put;
1575 }
1576
1577 if (phy_data->sfp_gpio_polarity) {
1578 axgbe_printf(0, "GPIO polarity inverted, resetting\n");
1579
1580 xgbe_log_gpio_expander(pdata);
1581 gpio_data[0] = 4; /* polarity register */
1582
1583 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1584 gpio_data, sizeof(gpio_data));
1585
1586 if (ret) {
1587 axgbe_error("%s: I2C error writing to GPIO polarity register\n",
1588 __func__);
1589 goto put_mux;
1590 }
1591 }
1592
1593 config = phy_data->sfp_gpio_configuration;
1594 if ((config & port_sfp_pins) != port_sfp_pins) {
1595 xgbe_log_gpio_expander(pdata);
1596
1597 /* Write the I/O states to the configuration register */
1598 axgbe_error("Invalid GPIO configuration, resetting\n");
1599 gpio_data[0] = 6; /* configuration register */
1600 config = config & ~(0xF << shift); /* clear port id bits */
1601 config |= port_sfp_pins;
1602 gpio_data[1] = config & 0xff;
1603 gpio_data[2] = (config >> 8);
1604
1605 ret = xgbe_phy_i2c_write(pdata, phy_data->sfp_gpio_address,
1606 gpio_data, sizeof(gpio_data));
1607 if (ret) {
1608 axgbe_error("%s: I2C error writing to GPIO configuration register\n",
1609 __func__);
1610 goto put_mux;
1611 }
1612 } else {
1613 axgbe_printf(0, "GPIO configuration valid\n");
1614 }
1615
1616 put_mux:
1617 xgbe_phy_sfp_put_mux(pdata);
1618
1619 put:
1620 xgbe_phy_put_comm_ownership(pdata);
1621
1622 return (ret);
1623 }
1624
1625 static void
xgbe_phy_sfp_mod_absent(struct xgbe_prv_data * pdata)1626 xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1627 {
1628 struct xgbe_phy_data *phy_data = pdata->phy_data;
1629
1630 xgbe_phy_free_phy_device(pdata);
1631
1632 phy_data->sfp_mod_absent = 1;
1633 phy_data->sfp_phy_avail = 0;
1634 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1635 }
1636
1637 static void
xgbe_phy_sfp_reset(struct xgbe_phy_data * phy_data)1638 xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1639 {
1640 phy_data->sfp_rx_los = 0;
1641 phy_data->sfp_tx_fault = 0;
1642 phy_data->sfp_mod_absent = 1;
1643 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1644 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1645 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1646 }
1647
1648 static void
xgbe_phy_sfp_detect(struct xgbe_prv_data * pdata)1649 xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1650 {
1651 struct xgbe_phy_data *phy_data = pdata->phy_data;
1652 int ret, prev_sfp_state = phy_data->sfp_mod_absent;
1653
1654 ret = xgbe_phy_get_comm_ownership(pdata);
1655 if (ret)
1656 return;
1657
1658 /* Read the SFP signals and check for module presence */
1659 xgbe_phy_sfp_signals(pdata);
1660 if (phy_data->sfp_mod_absent) {
1661 if (prev_sfp_state != phy_data->sfp_mod_absent)
1662 axgbe_error("%s: mod absent\n", __func__);
1663 xgbe_phy_sfp_mod_absent(pdata);
1664 goto put;
1665 }
1666
1667 ret = xgbe_phy_sfp_read_eeprom(pdata);
1668 if (ret) {
1669 /* Treat any error as if there isn't an SFP plugged in */
1670 axgbe_error("%s: eeprom read failed\n", __func__);
1671 ret = xgbe_read_gpio_expander(pdata);
1672
1673 if (!ret)
1674 xgbe_log_gpio_expander(pdata);
1675
1676 xgbe_phy_sfp_reset(phy_data);
1677 xgbe_phy_sfp_mod_absent(pdata);
1678 goto put;
1679 }
1680
1681 xgbe_phy_sfp_parse_eeprom(pdata);
1682
1683 xgbe_phy_sfp_external_phy(pdata);
1684
1685 put:
1686 xgbe_phy_sfp_phy_settings(pdata);
1687
1688 axgbe_printf(3, "%s: phy speed: 0x%x duplex: 0x%x autoneg: 0x%x "
1689 "pause_autoneg: 0x%x\n", __func__, pdata->phy.speed,
1690 pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg);
1691
1692 xgbe_phy_put_comm_ownership(pdata);
1693 }
1694
1695 static int
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata)1696 xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata)
1697 {
1698 struct xgbe_phy_data *phy_data = pdata->phy_data;
1699 uint8_t eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1700 struct xgbe_sfp_eeprom *sfp_eeprom;
1701 int ret;
1702
1703 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1704 ret = -ENXIO;
1705 goto done;
1706 }
1707
1708 if (phy_data->sfp_mod_absent) {
1709 ret = -EIO;
1710 goto done;
1711 }
1712
1713 ret = xgbe_phy_get_comm_ownership(pdata);
1714 if (ret) {
1715 ret = -EIO;
1716 goto done;
1717 }
1718
1719 ret = xgbe_phy_sfp_get_mux(pdata);
1720 if (ret) {
1721 axgbe_error("I2C error setting SFP MUX\n");
1722 ret = -EIO;
1723 goto put_own;
1724 }
1725
1726 /* Read the SFP serial ID eeprom */
1727 eeprom_addr = 0;
1728 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1729 &eeprom_addr, sizeof(eeprom_addr),
1730 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1731 if (ret) {
1732 axgbe_error("I2C error reading SFP EEPROM\n");
1733 ret = -EIO;
1734 goto put_mux;
1735 }
1736
1737 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1738
1739 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1740 /* Read the SFP diagnostic eeprom */
1741 eeprom_addr = 0;
1742 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1743 &eeprom_addr, sizeof(eeprom_addr),
1744 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1745 XGBE_SFP_EEPROM_DIAG_LEN);
1746 if (ret) {
1747 axgbe_error("I2C error reading SFP DIAGS\n");
1748 ret = -EIO;
1749 goto put_mux;
1750 }
1751 }
1752
1753 put_mux:
1754 xgbe_phy_sfp_put_mux(pdata);
1755
1756 put_own:
1757 xgbe_phy_put_comm_ownership(pdata);
1758
1759 done:
1760 return (ret);
1761 }
1762
1763 static int
xgbe_phy_module_info(struct xgbe_prv_data * pdata)1764 xgbe_phy_module_info(struct xgbe_prv_data *pdata)
1765 {
1766 struct xgbe_phy_data *phy_data = pdata->phy_data;
1767
1768 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1769 return (-ENXIO);
1770
1771 if (phy_data->sfp_mod_absent)
1772 return (-EIO);
1773
1774 return (0);
1775 }
1776
1777 static void
xgbe_phy_phydev_flowctrl(struct xgbe_prv_data * pdata)1778 xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1779 {
1780 struct xgbe_phy_data *phy_data = pdata->phy_data;
1781
1782 pdata->phy.tx_pause = 0;
1783 pdata->phy.rx_pause = 0;
1784
1785 if (!phy_data->phydev)
1786 return;
1787
1788 if (pdata->phy.pause)
1789 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1790
1791 if (pdata->phy.asym_pause)
1792 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1793
1794 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__,
1795 pdata->phy.tx_pause, pdata->phy.rx_pause);
1796 }
1797
1798 static enum xgbe_mode
xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data * pdata)1799 xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1800 {
1801 enum xgbe_mode mode;
1802
1803 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1804 XGBE_SET_LP_ADV(&pdata->phy, TP);
1805
1806 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
1807 pdata->phy.pause_autoneg);
1808
1809 /* Use external PHY to determine flow control */
1810 if (pdata->phy.pause_autoneg)
1811 xgbe_phy_phydev_flowctrl(pdata);
1812
1813 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1814 case XGBE_SGMII_AN_LINK_SPEED_100:
1815 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1816 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full);
1817 mode = XGBE_MODE_SGMII_100;
1818 } else {
1819 /* Half-duplex not supported */
1820 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half);
1821 mode = XGBE_MODE_UNKNOWN;
1822 }
1823 break;
1824 case XGBE_SGMII_AN_LINK_SPEED_1000:
1825 default:
1826 /* Default to 1000 */
1827 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1828 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full);
1829 mode = XGBE_MODE_SGMII_1000;
1830 } else {
1831 /* Half-duplex not supported */
1832 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half);
1833 mode = XGBE_MODE_SGMII_1000;
1834 }
1835 break;
1836 }
1837
1838 return (mode);
1839 }
1840
1841 static enum xgbe_mode
xgbe_phy_an37_outcome(struct xgbe_prv_data * pdata)1842 xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1843 {
1844 enum xgbe_mode mode;
1845 unsigned int ad_reg, lp_reg;
1846
1847 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1848 XGBE_SET_LP_ADV(&pdata->phy, FIBRE);
1849
1850 /* Compare Advertisement and Link Partner register */
1851 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1852 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1853 if (lp_reg & 0x100)
1854 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1855 if (lp_reg & 0x80)
1856 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1857
1858 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
1859 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1860
1861 if (pdata->phy.pause_autoneg) {
1862 /* Set flow control based on auto-negotiation result */
1863 pdata->phy.tx_pause = 0;
1864 pdata->phy.rx_pause = 0;
1865
1866 if (ad_reg & lp_reg & 0x100) {
1867 pdata->phy.tx_pause = 1;
1868 pdata->phy.rx_pause = 1;
1869 } else if (ad_reg & lp_reg & 0x80) {
1870 if (ad_reg & 0x100)
1871 pdata->phy.rx_pause = 1;
1872 else if (lp_reg & 0x100)
1873 pdata->phy.tx_pause = 1;
1874 }
1875 }
1876
1877 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
1878 pdata->phy.rx_pause);
1879
1880 if (lp_reg & 0x20)
1881 XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full);
1882
1883 /* Half duplex is not supported */
1884 ad_reg &= lp_reg;
1885 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1886
1887 return (mode);
1888 }
1889
1890 static enum xgbe_mode
xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data * pdata)1891 xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1892 {
1893 struct xgbe_phy_data *phy_data = pdata->phy_data;
1894 enum xgbe_mode mode;
1895 unsigned int ad_reg, lp_reg;
1896
1897 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1898 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1899
1900 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
1901 pdata->phy.pause_autoneg);
1902
1903 /* Use external PHY to determine flow control */
1904 if (pdata->phy.pause_autoneg)
1905 xgbe_phy_phydev_flowctrl(pdata);
1906
1907 /* Compare Advertisement and Link Partner register 2 */
1908 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1909 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1910 if (lp_reg & 0x80)
1911 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
1912 if (lp_reg & 0x20)
1913 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
1914
1915 ad_reg &= lp_reg;
1916 if (ad_reg & 0x80) {
1917 switch (phy_data->port_mode) {
1918 case XGBE_PORT_MODE_BACKPLANE:
1919 mode = XGBE_MODE_KR;
1920 break;
1921 default:
1922 mode = XGBE_MODE_SFI;
1923 break;
1924 }
1925 } else if (ad_reg & 0x20) {
1926 switch (phy_data->port_mode) {
1927 case XGBE_PORT_MODE_BACKPLANE:
1928 mode = XGBE_MODE_KX_1000;
1929 break;
1930 case XGBE_PORT_MODE_1000BASE_X:
1931 mode = XGBE_MODE_X;
1932 break;
1933 case XGBE_PORT_MODE_SFP:
1934 switch (phy_data->sfp_base) {
1935 case XGBE_SFP_BASE_1000_T:
1936 if ((phy_data->phydev) &&
1937 (pdata->phy.speed == SPEED_100))
1938 mode = XGBE_MODE_SGMII_100;
1939 else
1940 mode = XGBE_MODE_SGMII_1000;
1941 break;
1942 case XGBE_SFP_BASE_1000_SX:
1943 case XGBE_SFP_BASE_1000_LX:
1944 case XGBE_SFP_BASE_1000_CX:
1945 default:
1946 mode = XGBE_MODE_X;
1947 break;
1948 }
1949 break;
1950 default:
1951 if ((phy_data->phydev) &&
1952 (pdata->phy.speed == SPEED_100))
1953 mode = XGBE_MODE_SGMII_100;
1954 else
1955 mode = XGBE_MODE_SGMII_1000;
1956 break;
1957 }
1958 } else {
1959 mode = XGBE_MODE_UNKNOWN;
1960 }
1961
1962 /* Compare Advertisement and Link Partner register 3 */
1963 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1964 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1965 if (lp_reg & 0xc000)
1966 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
1967
1968 return (mode);
1969 }
1970
1971 static enum xgbe_mode
xgbe_phy_an73_outcome(struct xgbe_prv_data * pdata)1972 xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1973 {
1974 enum xgbe_mode mode;
1975 unsigned int ad_reg, lp_reg;
1976
1977 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1978 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1979
1980 /* Compare Advertisement and Link Partner register 1 */
1981 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1982 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1983 if (lp_reg & 0x400)
1984 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1985 if (lp_reg & 0x800)
1986 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1987
1988 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
1989 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1990
1991 if (pdata->phy.pause_autoneg) {
1992 /* Set flow control based on auto-negotiation result */
1993 pdata->phy.tx_pause = 0;
1994 pdata->phy.rx_pause = 0;
1995
1996 if (ad_reg & lp_reg & 0x400) {
1997 pdata->phy.tx_pause = 1;
1998 pdata->phy.rx_pause = 1;
1999 } else if (ad_reg & lp_reg & 0x800) {
2000 if (ad_reg & 0x400)
2001 pdata->phy.rx_pause = 1;
2002 else if (lp_reg & 0x400)
2003 pdata->phy.tx_pause = 1;
2004 }
2005 }
2006
2007 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
2008 pdata->phy.rx_pause);
2009
2010 /* Compare Advertisement and Link Partner register 2 */
2011 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
2012 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
2013 if (lp_reg & 0x80)
2014 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
2015 if (lp_reg & 0x20)
2016 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
2017
2018 ad_reg &= lp_reg;
2019 if (ad_reg & 0x80)
2020 mode = XGBE_MODE_KR;
2021 else if (ad_reg & 0x20)
2022 mode = XGBE_MODE_KX_1000;
2023 else
2024 mode = XGBE_MODE_UNKNOWN;
2025
2026 /* Compare Advertisement and Link Partner register 3 */
2027 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
2028 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
2029 if (lp_reg & 0xc000)
2030 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
2031
2032 return (mode);
2033 }
2034
2035 static enum xgbe_mode
xgbe_phy_an_outcome(struct xgbe_prv_data * pdata)2036 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
2037 {
2038 switch (pdata->an_mode) {
2039 case XGBE_AN_MODE_CL73:
2040 return (xgbe_phy_an73_outcome(pdata));
2041 case XGBE_AN_MODE_CL73_REDRV:
2042 return (xgbe_phy_an73_redrv_outcome(pdata));
2043 case XGBE_AN_MODE_CL37:
2044 return (xgbe_phy_an37_outcome(pdata));
2045 case XGBE_AN_MODE_CL37_SGMII:
2046 return (xgbe_phy_an37_sgmii_outcome(pdata));
2047 default:
2048 return (XGBE_MODE_UNKNOWN);
2049 }
2050 }
2051
2052 static void
xgbe_phy_an_advertising(struct xgbe_prv_data * pdata,struct xgbe_phy * dphy)2053 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)
2054 {
2055 struct xgbe_phy_data *phy_data = pdata->phy_data;
2056
2057 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
2058
2059 /* Without a re-driver, just return current advertising */
2060 if (!phy_data->redrv)
2061 return;
2062
2063 /* With the KR re-driver we need to advertise a single speed */
2064 XGBE_CLR_ADV(dphy, 1000baseKX_Full);
2065 XGBE_CLR_ADV(dphy, 10000baseKR_Full);
2066
2067 /* Advertise FEC support is present */
2068 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
2069 XGBE_SET_ADV(dphy, 10000baseR_FEC);
2070
2071 switch (phy_data->port_mode) {
2072 case XGBE_PORT_MODE_BACKPLANE:
2073 XGBE_SET_ADV(dphy, 10000baseKR_Full);
2074 break;
2075 case XGBE_PORT_MODE_BACKPLANE_2500:
2076 XGBE_SET_ADV(dphy, 1000baseKX_Full);
2077 break;
2078 case XGBE_PORT_MODE_1000BASE_T:
2079 case XGBE_PORT_MODE_1000BASE_X:
2080 case XGBE_PORT_MODE_NBASE_T:
2081 XGBE_SET_ADV(dphy, 1000baseKX_Full);
2082 break;
2083 case XGBE_PORT_MODE_10GBASE_T:
2084 if ((phy_data->phydev) &&
2085 (pdata->phy.speed == SPEED_10000))
2086 XGBE_SET_ADV(dphy, 10000baseKR_Full);
2087 else
2088 XGBE_SET_ADV(dphy, 1000baseKX_Full);
2089 break;
2090 case XGBE_PORT_MODE_10GBASE_R:
2091 XGBE_SET_ADV(dphy, 10000baseKR_Full);
2092 break;
2093 case XGBE_PORT_MODE_SFP:
2094 switch (phy_data->sfp_base) {
2095 case XGBE_SFP_BASE_1000_T:
2096 case XGBE_SFP_BASE_1000_SX:
2097 case XGBE_SFP_BASE_1000_LX:
2098 case XGBE_SFP_BASE_1000_CX:
2099 XGBE_SET_ADV(dphy, 1000baseKX_Full);
2100 break;
2101 default:
2102 XGBE_SET_ADV(dphy, 10000baseKR_Full);
2103 break;
2104 }
2105 break;
2106 default:
2107 XGBE_SET_ADV(dphy, 10000baseKR_Full);
2108 break;
2109 }
2110 }
2111
2112 static int
xgbe_phy_an_config(struct xgbe_prv_data * pdata)2113 xgbe_phy_an_config(struct xgbe_prv_data *pdata)
2114 {
2115 struct xgbe_phy_data *phy_data = pdata->phy_data;
2116 int ret;
2117
2118 ret = xgbe_phy_find_phy_device(pdata);
2119 if (ret)
2120 return (ret);
2121
2122 axgbe_printf(2, "%s: find_phy_device return %s.\n", __func__,
2123 ret ? "Failure" : "Success");
2124
2125 if (!phy_data->phydev)
2126 return (0);
2127
2128 return (ret);
2129 }
2130
2131 static enum xgbe_an_mode
xgbe_phy_an_sfp_mode(struct xgbe_phy_data * phy_data)2132 xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
2133 {
2134 switch (phy_data->sfp_base) {
2135 case XGBE_SFP_BASE_1000_T:
2136 return (XGBE_AN_MODE_CL37_SGMII);
2137 case XGBE_SFP_BASE_1000_SX:
2138 case XGBE_SFP_BASE_1000_LX:
2139 case XGBE_SFP_BASE_1000_CX:
2140 return (XGBE_AN_MODE_CL37);
2141 default:
2142 return (XGBE_AN_MODE_NONE);
2143 }
2144 }
2145
2146 static enum xgbe_an_mode
xgbe_phy_an_mode(struct xgbe_prv_data * pdata)2147 xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
2148 {
2149 struct xgbe_phy_data *phy_data = pdata->phy_data;
2150
2151 /* A KR re-driver will always require CL73 AN */
2152 if (phy_data->redrv)
2153 return (XGBE_AN_MODE_CL73_REDRV);
2154
2155 switch (phy_data->port_mode) {
2156 case XGBE_PORT_MODE_BACKPLANE:
2157 return (XGBE_AN_MODE_CL73);
2158 case XGBE_PORT_MODE_BACKPLANE_2500:
2159 return (XGBE_AN_MODE_NONE);
2160 case XGBE_PORT_MODE_1000BASE_T:
2161 return (XGBE_AN_MODE_CL37_SGMII);
2162 case XGBE_PORT_MODE_1000BASE_X:
2163 return (XGBE_AN_MODE_CL37);
2164 case XGBE_PORT_MODE_NBASE_T:
2165 return (XGBE_AN_MODE_CL37_SGMII);
2166 case XGBE_PORT_MODE_10GBASE_T:
2167 return (XGBE_AN_MODE_CL73);
2168 case XGBE_PORT_MODE_10GBASE_R:
2169 return (XGBE_AN_MODE_NONE);
2170 case XGBE_PORT_MODE_SFP:
2171 return (xgbe_phy_an_sfp_mode(phy_data));
2172 default:
2173 return (XGBE_AN_MODE_NONE);
2174 }
2175 }
2176
2177 static int
xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)2178 xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
2179 enum xgbe_phy_redrv_mode mode)
2180 {
2181 struct xgbe_phy_data *phy_data = pdata->phy_data;
2182 uint16_t redrv_reg, redrv_val;
2183
2184 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
2185 redrv_val = (uint16_t)mode;
2186
2187 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
2188 redrv_reg, redrv_val));
2189 }
2190
2191 static int
xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)2192 xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
2193 enum xgbe_phy_redrv_mode mode)
2194 {
2195 struct xgbe_phy_data *phy_data = pdata->phy_data;
2196 unsigned int redrv_reg;
2197 int ret;
2198
2199 /* Calculate the register to write */
2200 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
2201
2202 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
2203
2204 return (ret);
2205 }
2206
2207 static void
xgbe_phy_set_redrv_mode(struct xgbe_prv_data * pdata)2208 xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
2209 {
2210 struct xgbe_phy_data *phy_data = pdata->phy_data;
2211 enum xgbe_phy_redrv_mode mode;
2212 int ret;
2213
2214 if (!phy_data->redrv)
2215 return;
2216
2217 mode = XGBE_PHY_REDRV_MODE_CX;
2218 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
2219 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
2220 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
2221 mode = XGBE_PHY_REDRV_MODE_SR;
2222
2223 ret = xgbe_phy_get_comm_ownership(pdata);
2224 if (ret)
2225 return;
2226
2227 axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if);
2228 if (phy_data->redrv_if)
2229 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
2230 else
2231 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
2232
2233 xgbe_phy_put_comm_ownership(pdata);
2234 }
2235
2236 static void
xgbe_phy_pll_ctrl(struct xgbe_prv_data * pdata,bool enable)2237 xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
2238 {
2239 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
2240 XGBE_PMA_PLL_CTRL_MASK,
2241 enable ? XGBE_PMA_PLL_CTRL_ENABLE
2242 : XGBE_PMA_PLL_CTRL_DISABLE);
2243 DELAY(200);
2244 }
2245
2246 static void
xgbe_phy_rx_reset(struct xgbe_prv_data * pdata)2247 xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
2248 {
2249 int reg;
2250
2251 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
2252 XGBE_PCS_PSEQ_STATE_MASK);
2253
2254 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
2255 /*
2256 * Mailbox command timed out, reset of RX block is required.
2257 * This can be done by asserting the reset bit and waiting
2258 * for its completion.
2259 */
2260 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2261 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
2262 DELAY(20);
2263 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2264 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
2265 DELAY(50);
2266 axgbe_printf(0, "%s: firmware mailbox reset performed\n", __func__);
2267 }
2268 }
2269
2270 static void
xgbe_phy_perform_ratechange(struct xgbe_prv_data * pdata,unsigned int cmd,unsigned int sub_cmd)2271 xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, unsigned int cmd,
2272 unsigned int sub_cmd)
2273 {
2274 unsigned int s0 = 0;
2275 unsigned int wait;
2276
2277 xgbe_phy_pll_ctrl(pdata, false);
2278
2279 /* Log if a previous command did not complete */
2280 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2281 axgbe_error("firmware mailbox not ready for command\n");
2282 xgbe_phy_rx_reset(pdata);
2283 }
2284
2285 /* Construct the command */
2286 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2287 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2288
2289 /* Issue the command */
2290 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2291 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2292 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2293
2294 /* Wait for command to complete */
2295 wait = XGBE_RATECHANGE_COUNT;
2296 while (wait--) {
2297 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2298 axgbe_printf(3, "%s: Rate change done\n", __func__);
2299 goto reenable_pll;
2300 }
2301
2302 DELAY(2000);
2303 }
2304
2305 axgbe_printf(3, "firmware mailbox command did not complete\n");
2306
2307 reenable_pll:
2308 xgbe_phy_pll_ctrl(pdata, true);
2309 }
2310
2311 static void
xgbe_phy_rrc(struct xgbe_prv_data * pdata)2312 xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2313 {
2314 /* Receiver Reset Cycle */
2315 xgbe_phy_perform_ratechange(pdata, 5, 0);
2316
2317 axgbe_printf(3, "receiver reset complete\n");
2318 }
2319
2320 static void
xgbe_phy_power_off(struct xgbe_prv_data * pdata)2321 xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2322 {
2323 struct xgbe_phy_data *phy_data = pdata->phy_data;
2324
2325 /* Power off */
2326 xgbe_phy_perform_ratechange(pdata, 0, 0);
2327
2328 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2329
2330 axgbe_printf(3, "phy powered off\n");
2331 }
2332
2333 static void
xgbe_phy_sfi_mode(struct xgbe_prv_data * pdata)2334 xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2335 {
2336 struct xgbe_phy_data *phy_data = pdata->phy_data;
2337
2338 xgbe_phy_set_redrv_mode(pdata);
2339
2340 /* 10G/SFI */
2341 axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable,
2342 phy_data->sfp_cable_len);
2343
2344 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE)
2345 xgbe_phy_perform_ratechange(pdata, 3, 0);
2346 else {
2347 if (phy_data->sfp_cable_len <= 1)
2348 xgbe_phy_perform_ratechange(pdata, 3, 1);
2349 else if (phy_data->sfp_cable_len <= 3)
2350 xgbe_phy_perform_ratechange(pdata, 3, 2);
2351 else
2352 xgbe_phy_perform_ratechange(pdata, 3, 3);
2353 }
2354
2355 phy_data->cur_mode = XGBE_MODE_SFI;
2356
2357 axgbe_printf(3, "10GbE SFI mode set\n");
2358 }
2359
2360 static void
xgbe_phy_x_mode(struct xgbe_prv_data * pdata)2361 xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2362 {
2363 struct xgbe_phy_data *phy_data = pdata->phy_data;
2364
2365 xgbe_phy_set_redrv_mode(pdata);
2366
2367 /* 1G/X */
2368 xgbe_phy_perform_ratechange(pdata, 1, 3);
2369
2370 phy_data->cur_mode = XGBE_MODE_X;
2371
2372 axgbe_printf(3, "1GbE X mode set\n");
2373 }
2374
2375 static void
xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data * pdata)2376 xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2377 {
2378 struct xgbe_phy_data *phy_data = pdata->phy_data;
2379
2380 xgbe_phy_set_redrv_mode(pdata);
2381
2382 /* 1G/SGMII */
2383 xgbe_phy_perform_ratechange(pdata, 1, 2);
2384
2385 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2386
2387 axgbe_printf(2, "1GbE SGMII mode set\n");
2388 }
2389
2390 static void
xgbe_phy_sgmii_100_mode(struct xgbe_prv_data * pdata)2391 xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2392 {
2393 struct xgbe_phy_data *phy_data = pdata->phy_data;
2394
2395 xgbe_phy_set_redrv_mode(pdata);
2396
2397 /* 100M/SGMII */
2398 xgbe_phy_perform_ratechange(pdata, 1, 1);
2399
2400 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2401
2402 axgbe_printf(3, "100MbE SGMII mode set\n");
2403 }
2404
2405 static void
xgbe_phy_kr_mode(struct xgbe_prv_data * pdata)2406 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2407 {
2408 struct xgbe_phy_data *phy_data = pdata->phy_data;
2409
2410 xgbe_phy_set_redrv_mode(pdata);
2411
2412 /* 10G/KR */
2413 xgbe_phy_perform_ratechange(pdata, 4, 0);
2414
2415 phy_data->cur_mode = XGBE_MODE_KR;
2416
2417 axgbe_printf(3, "10GbE KR mode set\n");
2418 }
2419
2420 static void
xgbe_phy_kx_2500_mode(struct xgbe_prv_data * pdata)2421 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2422 {
2423 struct xgbe_phy_data *phy_data = pdata->phy_data;
2424
2425 xgbe_phy_set_redrv_mode(pdata);
2426
2427 /* 2.5G/KX */
2428 xgbe_phy_perform_ratechange(pdata, 2, 0);
2429
2430 phy_data->cur_mode = XGBE_MODE_KX_2500;
2431
2432 axgbe_printf(3, "2.5GbE KX mode set\n");
2433 }
2434
2435 static void
xgbe_phy_kx_1000_mode(struct xgbe_prv_data * pdata)2436 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2437 {
2438 struct xgbe_phy_data *phy_data = pdata->phy_data;
2439
2440 xgbe_phy_set_redrv_mode(pdata);
2441
2442 /* 1G/KX */
2443 xgbe_phy_perform_ratechange(pdata, 1, 3);
2444
2445 phy_data->cur_mode = XGBE_MODE_KX_1000;
2446
2447 axgbe_printf(3, "1GbE KX mode set\n");
2448 }
2449
2450 static enum xgbe_mode
xgbe_phy_cur_mode(struct xgbe_prv_data * pdata)2451 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2452 {
2453 struct xgbe_phy_data *phy_data = pdata->phy_data;
2454
2455 return (phy_data->cur_mode);
2456 }
2457
2458 static enum xgbe_mode
xgbe_phy_switch_baset_mode(struct xgbe_prv_data * pdata)2459 xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2460 {
2461 struct xgbe_phy_data *phy_data = pdata->phy_data;
2462
2463 /* No switching if not 10GBase-T */
2464 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2465 return (xgbe_phy_cur_mode(pdata));
2466
2467 switch (xgbe_phy_cur_mode(pdata)) {
2468 case XGBE_MODE_SGMII_100:
2469 case XGBE_MODE_SGMII_1000:
2470 return (XGBE_MODE_KR);
2471 case XGBE_MODE_KR:
2472 default:
2473 return (XGBE_MODE_SGMII_1000);
2474 }
2475 }
2476
2477 static enum xgbe_mode
xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data * pdata)2478 xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2479 {
2480 return (XGBE_MODE_KX_2500);
2481 }
2482
2483 static enum xgbe_mode
xgbe_phy_switch_bp_mode(struct xgbe_prv_data * pdata)2484 xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2485 {
2486 /* If we are in KR switch to KX, and vice-versa */
2487 switch (xgbe_phy_cur_mode(pdata)) {
2488 case XGBE_MODE_KX_1000:
2489 return (XGBE_MODE_KR);
2490 case XGBE_MODE_KR:
2491 default:
2492 return (XGBE_MODE_KX_1000);
2493 }
2494 }
2495
2496 static enum xgbe_mode
xgbe_phy_switch_mode(struct xgbe_prv_data * pdata)2497 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2498 {
2499 struct xgbe_phy_data *phy_data = pdata->phy_data;
2500
2501 switch (phy_data->port_mode) {
2502 case XGBE_PORT_MODE_BACKPLANE:
2503 return (xgbe_phy_switch_bp_mode(pdata));
2504 case XGBE_PORT_MODE_BACKPLANE_2500:
2505 return (xgbe_phy_switch_bp_2500_mode(pdata));
2506 case XGBE_PORT_MODE_1000BASE_T:
2507 case XGBE_PORT_MODE_NBASE_T:
2508 case XGBE_PORT_MODE_10GBASE_T:
2509 return (xgbe_phy_switch_baset_mode(pdata));
2510 case XGBE_PORT_MODE_1000BASE_X:
2511 case XGBE_PORT_MODE_10GBASE_R:
2512 case XGBE_PORT_MODE_SFP:
2513 /* No switching, so just return current mode */
2514 return (xgbe_phy_cur_mode(pdata));
2515 default:
2516 return (XGBE_MODE_UNKNOWN);
2517 }
2518 }
2519
2520 static enum xgbe_mode
xgbe_phy_get_basex_mode(struct xgbe_phy_data * phy_data,int speed)2521 xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2522 {
2523 switch (speed) {
2524 case SPEED_1000:
2525 return (XGBE_MODE_X);
2526 case SPEED_10000:
2527 return (XGBE_MODE_KR);
2528 default:
2529 return (XGBE_MODE_UNKNOWN);
2530 }
2531 }
2532
2533 static enum xgbe_mode
xgbe_phy_get_baset_mode(struct xgbe_phy_data * phy_data,int speed)2534 xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2535 {
2536 switch (speed) {
2537 case SPEED_100:
2538 return (XGBE_MODE_SGMII_100);
2539 case SPEED_1000:
2540 return (XGBE_MODE_SGMII_1000);
2541 case SPEED_2500:
2542 return (XGBE_MODE_KX_2500);
2543 case SPEED_10000:
2544 return (XGBE_MODE_KR);
2545 default:
2546 return (XGBE_MODE_UNKNOWN);
2547 }
2548 }
2549
2550 static enum xgbe_mode
xgbe_phy_get_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2551 xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2552 {
2553 switch (speed) {
2554 case SPEED_100:
2555 return (XGBE_MODE_SGMII_100);
2556 case SPEED_1000:
2557 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2558 return (XGBE_MODE_SGMII_1000);
2559 else
2560 return (XGBE_MODE_X);
2561 case SPEED_10000:
2562 case SPEED_UNKNOWN:
2563 return (XGBE_MODE_SFI);
2564 default:
2565 return (XGBE_MODE_UNKNOWN);
2566 }
2567 }
2568
2569 static enum xgbe_mode
xgbe_phy_get_bp_2500_mode(int speed)2570 xgbe_phy_get_bp_2500_mode(int speed)
2571 {
2572 switch (speed) {
2573 case SPEED_2500:
2574 return (XGBE_MODE_KX_2500);
2575 default:
2576 return (XGBE_MODE_UNKNOWN);
2577 }
2578 }
2579
2580 static enum xgbe_mode
xgbe_phy_get_bp_mode(int speed)2581 xgbe_phy_get_bp_mode(int speed)
2582 {
2583 switch (speed) {
2584 case SPEED_1000:
2585 return (XGBE_MODE_KX_1000);
2586 case SPEED_10000:
2587 return (XGBE_MODE_KR);
2588 default:
2589 return (XGBE_MODE_UNKNOWN);
2590 }
2591 }
2592
2593 static enum xgbe_mode
xgbe_phy_get_mode(struct xgbe_prv_data * pdata,int speed)2594 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)
2595 {
2596 struct xgbe_phy_data *phy_data = pdata->phy_data;
2597
2598 switch (phy_data->port_mode) {
2599 case XGBE_PORT_MODE_BACKPLANE:
2600 return (xgbe_phy_get_bp_mode(speed));
2601 case XGBE_PORT_MODE_BACKPLANE_2500:
2602 return (xgbe_phy_get_bp_2500_mode(speed));
2603 case XGBE_PORT_MODE_1000BASE_T:
2604 case XGBE_PORT_MODE_NBASE_T:
2605 case XGBE_PORT_MODE_10GBASE_T:
2606 return (xgbe_phy_get_baset_mode(phy_data, speed));
2607 case XGBE_PORT_MODE_1000BASE_X:
2608 case XGBE_PORT_MODE_10GBASE_R:
2609 return (xgbe_phy_get_basex_mode(phy_data, speed));
2610 case XGBE_PORT_MODE_SFP:
2611 return (xgbe_phy_get_sfp_mode(phy_data, speed));
2612 default:
2613 return (XGBE_MODE_UNKNOWN);
2614 }
2615 }
2616
2617 static void
xgbe_phy_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2618 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2619 {
2620 switch (mode) {
2621 case XGBE_MODE_KX_1000:
2622 xgbe_phy_kx_1000_mode(pdata);
2623 break;
2624 case XGBE_MODE_KX_2500:
2625 xgbe_phy_kx_2500_mode(pdata);
2626 break;
2627 case XGBE_MODE_KR:
2628 xgbe_phy_kr_mode(pdata);
2629 break;
2630 case XGBE_MODE_SGMII_100:
2631 xgbe_phy_sgmii_100_mode(pdata);
2632 break;
2633 case XGBE_MODE_SGMII_1000:
2634 xgbe_phy_sgmii_1000_mode(pdata);
2635 break;
2636 case XGBE_MODE_X:
2637 xgbe_phy_x_mode(pdata);
2638 break;
2639 case XGBE_MODE_SFI:
2640 xgbe_phy_sfi_mode(pdata);
2641 break;
2642 default:
2643 break;
2644 }
2645 }
2646
2647 static void
xgbe_phy_get_type(struct xgbe_prv_data * pdata,struct ifmediareq * ifmr)2648 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)
2649 {
2650 struct xgbe_phy_data *phy_data = pdata->phy_data;
2651
2652 switch (pdata->phy.speed) {
2653 case SPEED_10000:
2654 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2655 ifmr->ifm_active |= IFM_10G_KR;
2656 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T)
2657 ifmr->ifm_active |= IFM_10G_T;
2658 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R)
2659 ifmr->ifm_active |= IFM_10G_KR;
2660 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2661 ifmr->ifm_active |= IFM_10G_SFI;
2662 else
2663 ifmr->ifm_active |= IFM_OTHER;
2664 break;
2665 case SPEED_2500:
2666 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500)
2667 ifmr->ifm_active |= IFM_2500_KX;
2668 else
2669 ifmr->ifm_active |= IFM_OTHER;
2670 break;
2671 case SPEED_1000:
2672 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2673 ifmr->ifm_active |= IFM_1000_KX;
2674 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T)
2675 ifmr->ifm_active |= IFM_1000_T;
2676 #if 0
2677 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X)
2678 ifmr->ifm_active |= IFM_1000_SX;
2679 ifmr->ifm_active |= IFM_1000_LX;
2680 ifmr->ifm_active |= IFM_1000_CX;
2681 #endif
2682 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2683 ifmr->ifm_active |= IFM_1000_SGMII;
2684 else
2685 ifmr->ifm_active |= IFM_OTHER;
2686 break;
2687 case SPEED_100:
2688 if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)
2689 ifmr->ifm_active |= IFM_100_T;
2690 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2691 ifmr->ifm_active |= IFM_100_SGMII;
2692 else
2693 ifmr->ifm_active |= IFM_OTHER;
2694 break;
2695 default:
2696 ifmr->ifm_active |= IFM_OTHER;
2697 axgbe_printf(1, "Unknown mode detected\n");
2698 break;
2699 }
2700 }
2701
2702 static bool
xgbe_phy_check_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode,bool advert)2703 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode,
2704 bool advert)
2705 {
2706
2707 if (pdata->phy.autoneg == AUTONEG_ENABLE)
2708 return (advert);
2709 else {
2710 enum xgbe_mode cur_mode;
2711
2712 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2713 if (cur_mode == mode)
2714 return (true);
2715 }
2716
2717 return (false);
2718 }
2719
2720 static bool
xgbe_phy_use_basex_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2721 xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2722 {
2723
2724 switch (mode) {
2725 case XGBE_MODE_X:
2726 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2727 1000baseX_Full)));
2728 case XGBE_MODE_KR:
2729 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2730 10000baseKR_Full)));
2731 default:
2732 return (false);
2733 }
2734 }
2735
2736 static bool
xgbe_phy_use_baset_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2737 xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2738 {
2739
2740 axgbe_printf(3, "%s: check mode %d\n", __func__, mode);
2741 switch (mode) {
2742 case XGBE_MODE_SGMII_100:
2743 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2744 100baseT_Full)));
2745 case XGBE_MODE_SGMII_1000:
2746 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2747 1000baseT_Full)));
2748 case XGBE_MODE_KX_2500:
2749 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2750 2500baseT_Full)));
2751 case XGBE_MODE_KR:
2752 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2753 10000baseT_Full)));
2754 default:
2755 return (false);
2756 }
2757 }
2758
2759 static bool
xgbe_phy_use_sfp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2760 xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2761 {
2762 struct xgbe_phy_data *phy_data = pdata->phy_data;
2763
2764 switch (mode) {
2765 case XGBE_MODE_X:
2766 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2767 return (false);
2768 return (xgbe_phy_check_mode(pdata, mode,
2769 XGBE_ADV(&pdata->phy, 1000baseX_Full)));
2770 case XGBE_MODE_SGMII_100:
2771 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2772 return (false);
2773 return (xgbe_phy_check_mode(pdata, mode,
2774 XGBE_ADV(&pdata->phy, 100baseT_Full)));
2775 case XGBE_MODE_SGMII_1000:
2776 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2777 return (false);
2778 return (xgbe_phy_check_mode(pdata, mode,
2779 XGBE_ADV(&pdata->phy, 1000baseT_Full)));
2780 case XGBE_MODE_SFI:
2781 if (phy_data->sfp_mod_absent)
2782 return (true);
2783 return (xgbe_phy_check_mode(pdata, mode,
2784 XGBE_ADV(&pdata->phy, 10000baseSR_Full) ||
2785 XGBE_ADV(&pdata->phy, 10000baseLR_Full) ||
2786 XGBE_ADV(&pdata->phy, 10000baseLRM_Full) ||
2787 XGBE_ADV(&pdata->phy, 10000baseER_Full) ||
2788 XGBE_ADV(&pdata->phy, 10000baseCR_Full)));
2789 default:
2790 return (false);
2791 }
2792 }
2793
2794 static bool
xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2795 xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2796 {
2797
2798 switch (mode) {
2799 case XGBE_MODE_KX_2500:
2800 return (xgbe_phy_check_mode(pdata, mode,
2801 XGBE_ADV(&pdata->phy, 2500baseX_Full)));
2802 default:
2803 return (false);
2804 }
2805 }
2806
2807 static bool
xgbe_phy_use_bp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2808 xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2809 {
2810
2811 switch (mode) {
2812 case XGBE_MODE_KX_1000:
2813 return (xgbe_phy_check_mode(pdata, mode,
2814 XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
2815 case XGBE_MODE_KR:
2816 return (xgbe_phy_check_mode(pdata, mode,
2817 XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
2818 default:
2819 return (false);
2820 }
2821 }
2822
2823 static bool
xgbe_phy_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2824 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2825 {
2826 struct xgbe_phy_data *phy_data = pdata->phy_data;
2827
2828 switch (phy_data->port_mode) {
2829 case XGBE_PORT_MODE_BACKPLANE:
2830 return (xgbe_phy_use_bp_mode(pdata, mode));
2831 case XGBE_PORT_MODE_BACKPLANE_2500:
2832 return (xgbe_phy_use_bp_2500_mode(pdata, mode));
2833 case XGBE_PORT_MODE_1000BASE_T:
2834 axgbe_printf(3, "use_mode %s\n",
2835 xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found");
2836 case XGBE_PORT_MODE_NBASE_T:
2837 case XGBE_PORT_MODE_10GBASE_T:
2838 return (xgbe_phy_use_baset_mode(pdata, mode));
2839 case XGBE_PORT_MODE_1000BASE_X:
2840 case XGBE_PORT_MODE_10GBASE_R:
2841 return (xgbe_phy_use_basex_mode(pdata, mode));
2842 case XGBE_PORT_MODE_SFP:
2843 return (xgbe_phy_use_sfp_mode(pdata, mode));
2844 default:
2845 return (false);
2846 }
2847 }
2848
2849 static bool
xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data * phy_data,int speed)2850 xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2851 {
2852
2853 switch (speed) {
2854 case SPEED_1000:
2855 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2856 case SPEED_10000:
2857 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2858 default:
2859 return (false);
2860 }
2861 }
2862
2863 static bool
xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data * phy_data,int speed)2864 xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2865 {
2866
2867 switch (speed) {
2868 case SPEED_100:
2869 case SPEED_1000:
2870 return (true);
2871 case SPEED_2500:
2872 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2873 case SPEED_10000:
2874 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2875 default:
2876 return (false);
2877 }
2878 }
2879
2880 static bool
xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2881 xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2882 {
2883
2884 switch (speed) {
2885 case SPEED_100:
2886 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100) ||
2887 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000));
2888 case SPEED_1000:
2889 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2890 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2891 case SPEED_10000:
2892 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2893 default:
2894 return (false);
2895 }
2896 }
2897
2898 static bool
xgbe_phy_valid_speed_bp_2500_mode(int speed)2899 xgbe_phy_valid_speed_bp_2500_mode(int speed)
2900 {
2901
2902 switch (speed) {
2903 case SPEED_2500:
2904 return (true);
2905 default:
2906 return (false);
2907 }
2908 }
2909
2910 static bool
xgbe_phy_valid_speed_bp_mode(int speed)2911 xgbe_phy_valid_speed_bp_mode(int speed)
2912 {
2913
2914 switch (speed) {
2915 case SPEED_1000:
2916 case SPEED_10000:
2917 return (true);
2918 default:
2919 return (false);
2920 }
2921 }
2922
2923 static bool
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)2924 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2925 {
2926 struct xgbe_phy_data *phy_data = pdata->phy_data;
2927
2928 switch (phy_data->port_mode) {
2929 case XGBE_PORT_MODE_BACKPLANE:
2930 return (xgbe_phy_valid_speed_bp_mode(speed));
2931 case XGBE_PORT_MODE_BACKPLANE_2500:
2932 return (xgbe_phy_valid_speed_bp_2500_mode(speed));
2933 case XGBE_PORT_MODE_1000BASE_T:
2934 case XGBE_PORT_MODE_NBASE_T:
2935 case XGBE_PORT_MODE_10GBASE_T:
2936 return (xgbe_phy_valid_speed_baset_mode(phy_data, speed));
2937 case XGBE_PORT_MODE_1000BASE_X:
2938 case XGBE_PORT_MODE_10GBASE_R:
2939 return (xgbe_phy_valid_speed_basex_mode(phy_data, speed));
2940 case XGBE_PORT_MODE_SFP:
2941 return (xgbe_phy_valid_speed_sfp_mode(phy_data, speed));
2942 default:
2943 return (false);
2944 }
2945 }
2946
2947 static int
xgbe_upd_link(struct xgbe_prv_data * pdata)2948 xgbe_upd_link(struct xgbe_prv_data *pdata)
2949 {
2950 int reg;
2951
2952 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);
2953 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2954 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2955 if (reg < 0)
2956 return (reg);
2957
2958 if ((reg & BMSR_LINK) == 0)
2959 pdata->phy.link = 0;
2960 else
2961 pdata->phy.link = 1;
2962
2963 axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);
2964 return (0);
2965 }
2966
2967 static int
xgbe_phy_read_status(struct xgbe_prv_data * pdata)2968 xgbe_phy_read_status(struct xgbe_prv_data *pdata)
2969 {
2970 int common_adv_gb = 0;
2971 int common_adv;
2972 int lpagb = 0;
2973 int adv, lpa;
2974 int ret;
2975
2976 ret = xgbe_upd_link(pdata);
2977 if (ret) {
2978 axgbe_printf(2, "Link Update return %d\n", ret);
2979 return (ret);
2980 }
2981
2982 if (AUTONEG_ENABLE == pdata->phy.autoneg) {
2983 if (pdata->phy.supported == SUPPORTED_1000baseT_Half ||
2984 pdata->phy.supported == SUPPORTED_1000baseT_Full) {
2985 lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2986 MII_100T2SR);
2987 if (lpagb < 0)
2988 return (lpagb);
2989
2990 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2991 MII_100T2CR);
2992 if (adv < 0)
2993 return (adv);
2994
2995 if (lpagb & GTSR_MAN_MS_FLT) {
2996 if (adv & GTCR_MAN_MS)
2997 axgbe_printf(2, "Master/Slave Resolution "
2998 "failed, maybe conflicting manual settings\n");
2999 else
3000 axgbe_printf(2, "Master/Slave Resolution failed\n");
3001 return (-ENOLINK);
3002 }
3003
3004 if (pdata->phy.supported == SUPPORTED_1000baseT_Half)
3005 XGBE_SET_ADV(&pdata->phy, 1000baseT_Half);
3006 else if (pdata->phy.supported == SUPPORTED_1000baseT_Full)
3007 XGBE_SET_ADV(&pdata->phy, 1000baseT_Full);
3008
3009 common_adv_gb = lpagb & adv << 2;
3010 }
3011
3012 lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR);
3013 if (lpa < 0)
3014 return (lpa);
3015
3016 if (pdata->phy.supported == SUPPORTED_Autoneg)
3017 XGBE_SET_ADV(&pdata->phy, Autoneg);
3018
3019 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR);
3020 if (adv < 0)
3021 return (adv);
3022
3023 common_adv = lpa & adv;
3024
3025 pdata->phy.speed = SPEED_10;
3026 pdata->phy.duplex = DUPLEX_HALF;
3027 pdata->phy.pause = 0;
3028 pdata->phy.asym_pause = 0;
3029
3030 axgbe_printf(2, "%s: lpa %#x adv %#x common_adv_gb %#x "
3031 "common_adv %#x\n", __func__, lpa, adv, common_adv_gb,
3032 common_adv);
3033 if (common_adv_gb & (GTSR_LP_1000TFDX | GTSR_LP_1000THDX)) {
3034 axgbe_printf(2, "%s: SPEED 1000\n", __func__);
3035 pdata->phy.speed = SPEED_1000;
3036
3037 if (common_adv_gb & GTSR_LP_1000TFDX)
3038 pdata->phy.duplex = DUPLEX_FULL;
3039 } else if (common_adv & (ANLPAR_TX_FD | ANLPAR_TX)) {
3040 axgbe_printf(2, "%s: SPEED 100\n", __func__);
3041 pdata->phy.speed = SPEED_100;
3042
3043 if (common_adv & ANLPAR_TX_FD)
3044 pdata->phy.duplex = DUPLEX_FULL;
3045 } else
3046 if (common_adv & ANLPAR_10_FD)
3047 pdata->phy.duplex = DUPLEX_FULL;
3048
3049 if (pdata->phy.duplex == DUPLEX_FULL) {
3050 pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0;
3051 pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
3052 }
3053 } else {
3054 int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
3055 if (bmcr < 0)
3056 return (bmcr);
3057
3058 if (bmcr & BMCR_FDX)
3059 pdata->phy.duplex = DUPLEX_FULL;
3060 else
3061 pdata->phy.duplex = DUPLEX_HALF;
3062
3063 if (bmcr & BMCR_SPEED1)
3064 pdata->phy.speed = SPEED_1000;
3065 else if (bmcr & BMCR_SPEED100)
3066 pdata->phy.speed = SPEED_100;
3067 else
3068 pdata->phy.speed = SPEED_10;
3069
3070 pdata->phy.pause = 0;
3071 pdata->phy.asym_pause = 0;
3072 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
3073 "autoneg %#x\n", __func__, pdata->phy.speed,
3074 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
3075 }
3076
3077 return (0);
3078 }
3079
3080 static void
xgbe_rrc(struct xgbe_prv_data * pdata)3081 xgbe_rrc(struct xgbe_prv_data *pdata)
3082 {
3083 struct xgbe_phy_data *phy_data = pdata->phy_data;
3084 int ret;
3085
3086 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
3087 axgbe_printf(1, "ENTERED RRC: rrc_count: %d\n",
3088 phy_data->rrc_count);
3089 phy_data->rrc_count = 0;
3090 if (pdata->link_workaround) {
3091 ret = xgbe_phy_reset(pdata);
3092 if (ret)
3093 axgbe_error("Error resetting phy\n");
3094 } else
3095 xgbe_phy_rrc(pdata);
3096 }
3097 }
3098
3099 static int
xgbe_phy_link_status(struct xgbe_prv_data * pdata,int * an_restart)3100 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
3101 {
3102 struct xgbe_phy_data *phy_data = pdata->phy_data;
3103 struct mii_data *mii = NULL;
3104 unsigned int reg;
3105 int ret;
3106
3107 *an_restart = 0;
3108
3109 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
3110 /* Check SFP signals */
3111 axgbe_printf(3, "%s: calling phy detect\n", __func__);
3112 xgbe_phy_sfp_detect(pdata);
3113
3114 if (phy_data->sfp_changed) {
3115 axgbe_printf(1, "%s: SFP changed observed\n", __func__);
3116 *an_restart = 1;
3117 return (0);
3118 }
3119
3120 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
3121 axgbe_printf(1, "%s: SFP absent 0x%x & sfp_rx_los 0x%x\n",
3122 __func__, phy_data->sfp_mod_absent,
3123 phy_data->sfp_rx_los);
3124
3125 if (!phy_data->sfp_mod_absent) {
3126 xgbe_rrc(pdata);
3127 }
3128
3129 return (0);
3130 }
3131 }
3132
3133 if (phy_data->phydev || phy_data->port_mode != XGBE_PORT_MODE_SFP) {
3134 if (pdata->axgbe_miibus == NULL) {
3135 axgbe_printf(1, "%s: miibus not initialized", __func__);
3136 goto mdio_read;
3137 }
3138
3139 mii = device_get_softc(pdata->axgbe_miibus);
3140 mii_tick(mii);
3141
3142 ret = xgbe_phy_read_status(pdata);
3143 if (ret) {
3144 axgbe_error("Link: Read status returned %d\n", ret);
3145 return (0);
3146 }
3147
3148 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
3149 "autoneg %#x\n", __func__, pdata->phy.speed,
3150 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
3151 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
3152 ret = (ret < 0) ? ret : (ret & BMSR_ACOMP);
3153 axgbe_printf(2, "Link: BMCR returned %d\n", ret);
3154 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret)
3155 return (0);
3156
3157 if (pdata->phy.link)
3158 return (1);
3159
3160 xgbe_rrc(pdata);
3161 }
3162
3163 mdio_read:
3164
3165 /* Link status is latched low, so read once to clear
3166 * and then read again to get current state
3167 */
3168 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
3169 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
3170 axgbe_printf(1, "%s: link_status reg: 0x%x\n", __func__, reg);
3171 if (reg & MDIO_STAT1_LSTATUS)
3172 return (1);
3173
3174 /* No link, attempt a receiver reset cycle */
3175 xgbe_rrc(pdata);
3176
3177 return (0);
3178 }
3179
3180 static void
xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data * pdata)3181 xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
3182 {
3183 struct xgbe_phy_data *phy_data = pdata->phy_data;
3184
3185 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
3186 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR);
3187 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3188 GPIO_MASK);
3189 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3190 GPIO_RX_LOS);
3191 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3192 GPIO_TX_FAULT);
3193 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3194 GPIO_MOD_ABS);
3195 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3196 GPIO_RATE_SELECT);
3197
3198 DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address);
3199 DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask);
3200 DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los);
3201 DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault);
3202 DBGPR("SFP: gpio_mod_absent=%u\n",
3203 phy_data->sfp_gpio_mod_absent);
3204 DBGPR("SFP: gpio_rate_select=%u\n",
3205 phy_data->sfp_gpio_rate_select);
3206 }
3207
3208 static void
xgbe_phy_sfp_comm_setup(struct xgbe_prv_data * pdata)3209 xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
3210 {
3211 struct xgbe_phy_data *phy_data = pdata->phy_data;
3212 unsigned int mux_addr_hi, mux_addr_lo;
3213
3214 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
3215 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
3216 if (mux_addr_lo == XGBE_SFP_DIRECT)
3217 return;
3218
3219 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
3220 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
3221 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
3222 MUX_CHAN);
3223
3224 DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address);
3225 DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel);
3226 }
3227
3228 static void
xgbe_phy_sfp_setup(struct xgbe_prv_data * pdata)3229 xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
3230 {
3231 xgbe_phy_sfp_comm_setup(pdata);
3232 xgbe_phy_sfp_gpio_setup(pdata);
3233 }
3234
3235 static int
xgbe_phy_int_mdio_reset(struct xgbe_prv_data * pdata)3236 xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
3237 {
3238 struct xgbe_phy_data *phy_data = pdata->phy_data;
3239 unsigned int ret;
3240
3241 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
3242 if (ret)
3243 return (ret);
3244
3245 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
3246
3247 return (ret);
3248 }
3249
3250 static int
xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data * pdata)3251 xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
3252 {
3253 struct xgbe_phy_data *phy_data = pdata->phy_data;
3254 uint8_t gpio_reg, gpio_ports[2], gpio_data[3];
3255 int ret;
3256
3257 /* Read the output port registers */
3258 gpio_reg = 2;
3259 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
3260 &gpio_reg, sizeof(gpio_reg),
3261 gpio_ports, sizeof(gpio_ports));
3262 if (ret)
3263 return (ret);
3264
3265 /* Prepare to write the GPIO data */
3266 gpio_data[0] = 2;
3267 gpio_data[1] = gpio_ports[0];
3268 gpio_data[2] = gpio_ports[1];
3269
3270 /* Set the GPIO pin */
3271 if (phy_data->mdio_reset_gpio < 8)
3272 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
3273 else
3274 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
3275
3276 /* Write the output port registers */
3277 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3278 gpio_data, sizeof(gpio_data));
3279 if (ret)
3280 return (ret);
3281
3282 /* Clear the GPIO pin */
3283 if (phy_data->mdio_reset_gpio < 8)
3284 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3285 else
3286 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3287
3288 /* Write the output port registers */
3289 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3290 gpio_data, sizeof(gpio_data));
3291
3292 return (ret);
3293 }
3294
3295 static int
xgbe_phy_mdio_reset(struct xgbe_prv_data * pdata)3296 xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
3297 {
3298 struct xgbe_phy_data *phy_data = pdata->phy_data;
3299 int ret;
3300
3301 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3302 return (0);
3303
3304 ret = xgbe_phy_get_comm_ownership(pdata);
3305 if (ret)
3306 return (ret);
3307
3308 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3309 ret = xgbe_phy_i2c_mdio_reset(pdata);
3310 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3311 ret = xgbe_phy_int_mdio_reset(pdata);
3312
3313 xgbe_phy_put_comm_ownership(pdata);
3314
3315 return (ret);
3316 }
3317
3318 static bool
xgbe_phy_redrv_error(struct xgbe_phy_data * phy_data)3319 xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
3320 {
3321 if (!phy_data->redrv)
3322 return (false);
3323
3324 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3325 return (true);
3326
3327 switch (phy_data->redrv_model) {
3328 case XGBE_PHY_REDRV_MODEL_4223:
3329 if (phy_data->redrv_lane > 3)
3330 return (true);
3331 break;
3332 case XGBE_PHY_REDRV_MODEL_4227:
3333 if (phy_data->redrv_lane > 1)
3334 return (true);
3335 break;
3336 default:
3337 return (true);
3338 }
3339
3340 return (false);
3341 }
3342
3343 static int
xgbe_phy_mdio_reset_setup(struct xgbe_prv_data * pdata)3344 xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3345 {
3346 struct xgbe_phy_data *phy_data = pdata->phy_data;
3347
3348 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3349 return (0);
3350
3351 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3352 switch (phy_data->mdio_reset) {
3353 case XGBE_MDIO_RESET_NONE:
3354 case XGBE_MDIO_RESET_I2C_GPIO:
3355 case XGBE_MDIO_RESET_INT_GPIO:
3356 break;
3357 default:
3358 axgbe_error("unsupported MDIO reset (%#x)\n",
3359 phy_data->mdio_reset);
3360 return (-EINVAL);
3361 }
3362
3363 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3364 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3365 XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR);
3366 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3367 MDIO_RESET_I2C_GPIO);
3368 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3369 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3370 MDIO_RESET_INT_GPIO);
3371
3372 return (0);
3373 }
3374
3375 static bool
xgbe_phy_port_mode_mismatch(struct xgbe_prv_data * pdata)3376 xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3377 {
3378 struct xgbe_phy_data *phy_data = pdata->phy_data;
3379
3380 switch (phy_data->port_mode) {
3381 case XGBE_PORT_MODE_BACKPLANE:
3382 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3383 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3384 return (false);
3385 break;
3386 case XGBE_PORT_MODE_BACKPLANE_2500:
3387 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3388 return (false);
3389 break;
3390 case XGBE_PORT_MODE_1000BASE_T:
3391 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3392 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3393 return (false);
3394 break;
3395 case XGBE_PORT_MODE_1000BASE_X:
3396 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3397 return (false);
3398 break;
3399 case XGBE_PORT_MODE_NBASE_T:
3400 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3401 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3402 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3403 return (false);
3404 break;
3405 case XGBE_PORT_MODE_10GBASE_T:
3406 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3407 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3408 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3409 return (false);
3410 break;
3411 case XGBE_PORT_MODE_10GBASE_R:
3412 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3413 return (false);
3414 break;
3415 case XGBE_PORT_MODE_SFP:
3416 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3417 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3418 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3419 return (false);
3420 break;
3421 default:
3422 break;
3423 }
3424
3425 return (true);
3426 }
3427
3428 static bool
xgbe_phy_conn_type_mismatch(struct xgbe_prv_data * pdata)3429 xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3430 {
3431 struct xgbe_phy_data *phy_data = pdata->phy_data;
3432
3433 switch (phy_data->port_mode) {
3434 case XGBE_PORT_MODE_BACKPLANE:
3435 case XGBE_PORT_MODE_BACKPLANE_2500:
3436 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3437 return (false);
3438 break;
3439 case XGBE_PORT_MODE_1000BASE_T:
3440 case XGBE_PORT_MODE_1000BASE_X:
3441 case XGBE_PORT_MODE_NBASE_T:
3442 case XGBE_PORT_MODE_10GBASE_T:
3443 case XGBE_PORT_MODE_10GBASE_R:
3444 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3445 return (false);
3446 break;
3447 case XGBE_PORT_MODE_SFP:
3448 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3449 return (false);
3450 break;
3451 default:
3452 break;
3453 }
3454
3455 return (true);
3456 }
3457
3458 static bool
xgbe_phy_port_enabled(struct xgbe_prv_data * pdata)3459 xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3460 {
3461
3462 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3463 return (false);
3464 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3465 return (false);
3466
3467 return (true);
3468 }
3469
3470 static void
xgbe_phy_cdr_track(struct xgbe_prv_data * pdata)3471 xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3472 {
3473 struct xgbe_phy_data *phy_data = pdata->phy_data;
3474
3475 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
3476 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3477
3478 if (!pdata->sysctl_an_cdr_workaround)
3479 return;
3480
3481 if (!phy_data->phy_cdr_notrack)
3482 return;
3483
3484 DELAY(phy_data->phy_cdr_delay + 500);
3485
3486 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3487 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_ON);
3488
3489 phy_data->phy_cdr_notrack = 0;
3490
3491 axgbe_printf(2, "CDR TRACK DONE\n");
3492 }
3493
3494 static void
xgbe_phy_cdr_notrack(struct xgbe_prv_data * pdata)3495 xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3496 {
3497 struct xgbe_phy_data *phy_data = pdata->phy_data;
3498
3499 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
3500 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3501
3502 if (!pdata->sysctl_an_cdr_workaround)
3503 return;
3504
3505 if (phy_data->phy_cdr_notrack)
3506 return;
3507
3508 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3509 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_OFF);
3510
3511 xgbe_phy_rrc(pdata);
3512
3513 phy_data->phy_cdr_notrack = 1;
3514 }
3515
3516 static void
xgbe_phy_kr_training_post(struct xgbe_prv_data * pdata)3517 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3518 {
3519 if (!pdata->sysctl_an_cdr_track_early)
3520 xgbe_phy_cdr_track(pdata);
3521 }
3522
3523 static void
xgbe_phy_kr_training_pre(struct xgbe_prv_data * pdata)3524 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3525 {
3526 if (pdata->sysctl_an_cdr_track_early)
3527 xgbe_phy_cdr_track(pdata);
3528 }
3529
3530 static void
xgbe_phy_an_post(struct xgbe_prv_data * pdata)3531 xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3532 {
3533 struct xgbe_phy_data *phy_data = pdata->phy_data;
3534
3535 switch (pdata->an_mode) {
3536 case XGBE_AN_MODE_CL73:
3537 case XGBE_AN_MODE_CL73_REDRV:
3538 if (phy_data->cur_mode != XGBE_MODE_KR)
3539 break;
3540
3541 xgbe_phy_cdr_track(pdata);
3542
3543 switch (pdata->an_result) {
3544 case XGBE_AN_READY:
3545 case XGBE_AN_COMPLETE:
3546 break;
3547 default:
3548 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3549 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3550 else
3551 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3552 break;
3553 }
3554 break;
3555 default:
3556 break;
3557 }
3558 }
3559
3560 static void
xgbe_phy_an_pre(struct xgbe_prv_data * pdata)3561 xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3562 {
3563 struct xgbe_phy_data *phy_data = pdata->phy_data;
3564
3565 switch (pdata->an_mode) {
3566 case XGBE_AN_MODE_CL73:
3567 case XGBE_AN_MODE_CL73_REDRV:
3568 if (phy_data->cur_mode != XGBE_MODE_KR)
3569 break;
3570
3571 xgbe_phy_cdr_notrack(pdata);
3572 break;
3573 default:
3574 break;
3575 }
3576 }
3577
3578 static void
xgbe_phy_stop(struct xgbe_prv_data * pdata)3579 xgbe_phy_stop(struct xgbe_prv_data *pdata)
3580 {
3581 struct xgbe_phy_data *phy_data = pdata->phy_data;
3582
3583 /* If we have an external PHY, free it */
3584 xgbe_phy_free_phy_device(pdata);
3585
3586 /* Reset SFP data */
3587 xgbe_phy_sfp_reset(phy_data);
3588 xgbe_phy_sfp_mod_absent(pdata);
3589
3590 /* Reset CDR support */
3591 xgbe_phy_cdr_track(pdata);
3592
3593 /* Power off the PHY */
3594 xgbe_phy_power_off(pdata);
3595
3596 /* Stop the I2C controller */
3597 pdata->i2c_if.i2c_stop(pdata);
3598 }
3599
3600 static int
xgbe_phy_start(struct xgbe_prv_data * pdata)3601 xgbe_phy_start(struct xgbe_prv_data *pdata)
3602 {
3603 struct xgbe_phy_data *phy_data = pdata->phy_data;
3604 int ret;
3605
3606 axgbe_printf(2, "%s: redrv %d redrv_if %d start_mode %d\n", __func__,
3607 phy_data->redrv, phy_data->redrv_if, phy_data->start_mode);
3608
3609 /* Start the I2C controller */
3610 ret = pdata->i2c_if.i2c_start(pdata);
3611 if (ret) {
3612 axgbe_error("%s: impl i2c start ret %d\n", __func__, ret);
3613 return (ret);
3614 }
3615
3616 /* Set the proper MDIO mode for the re-driver */
3617 if (phy_data->redrv && !phy_data->redrv_if) {
3618 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3619 XGBE_MDIO_MODE_CL22);
3620 if (ret) {
3621 axgbe_error("redriver mdio port not compatible (%u)\n",
3622 phy_data->redrv_addr);
3623 return (ret);
3624 }
3625 }
3626
3627 /* Start in highest supported mode */
3628 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3629
3630 /* Reset CDR support */
3631 xgbe_phy_cdr_track(pdata);
3632
3633 /* After starting the I2C controller, we can check for an SFP */
3634 switch (phy_data->port_mode) {
3635 case XGBE_PORT_MODE_SFP:
3636 axgbe_printf(3, "%s: calling phy detect\n", __func__);
3637
3638 /*
3639 * Validate the configuration of the GPIO expander before
3640 * we interpret the SFP signals.
3641 */
3642 axgbe_printf(1, "Checking GPIO expander validity\n");
3643 xgbe_phy_validate_gpio_expander(pdata);
3644
3645 phy_data->sfp_phy_retries = 0;
3646 xgbe_phy_sfp_detect(pdata);
3647 break;
3648 default:
3649 break;
3650 }
3651
3652 /* If we have an external PHY, start it */
3653 ret = xgbe_phy_find_phy_device(pdata);
3654 if (ret) {
3655 axgbe_error("%s: impl find phy dev ret %d\n", __func__, ret);
3656 goto err_i2c;
3657 }
3658
3659 axgbe_printf(3, "%s: impl return success\n", __func__);
3660 return (0);
3661
3662 err_i2c:
3663 pdata->i2c_if.i2c_stop(pdata);
3664
3665 return (ret);
3666 }
3667
3668 static int
xgbe_phy_reset(struct xgbe_prv_data * pdata)3669 xgbe_phy_reset(struct xgbe_prv_data *pdata)
3670 {
3671 struct xgbe_phy_data *phy_data = pdata->phy_data;
3672 enum xgbe_mode cur_mode;
3673 int ret;
3674
3675 /* Reset by power cycling the PHY */
3676 cur_mode = phy_data->cur_mode;
3677 xgbe_phy_power_off(pdata);
3678 xgbe_phy_set_mode(pdata, cur_mode);
3679
3680 axgbe_printf(3, "%s: mode %d\n", __func__, cur_mode);
3681 if (!phy_data->phydev) {
3682 axgbe_printf(1, "%s: no phydev\n", __func__);
3683 return (0);
3684 }
3685
3686 /* Reset the external PHY */
3687 ret = xgbe_phy_mdio_reset(pdata);
3688 if (ret) {
3689 axgbe_error("%s: mdio reset %d\n", __func__, ret);
3690 return (ret);
3691 }
3692
3693 axgbe_printf(3, "%s: return success\n", __func__);
3694
3695 return (0);
3696 }
3697
3698 static void
axgbe_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)3699 axgbe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
3700 {
3701 struct axgbe_if_softc *sc;
3702 struct xgbe_prv_data *pdata;
3703 struct mii_data *mii;
3704
3705 sc = if_getsoftc(ifp);
3706 pdata = &sc->pdata;
3707
3708 axgbe_printf(2, "%s: Invoked\n", __func__);
3709 mtx_lock_spin(&pdata->mdio_mutex);
3710 mii = device_get_softc(pdata->axgbe_miibus);
3711 axgbe_printf(2, "%s: media_active %#x media_status %#x\n", __func__,
3712 mii->mii_media_active, mii->mii_media_status);
3713 mii_pollstat(mii);
3714 ifmr->ifm_active = mii->mii_media_active;
3715 ifmr->ifm_status = mii->mii_media_status;
3716 mtx_unlock_spin(&pdata->mdio_mutex);
3717 }
3718
3719 static int
axgbe_ifmedia_upd(if_t ifp)3720 axgbe_ifmedia_upd(if_t ifp)
3721 {
3722 struct xgbe_prv_data *pdata;
3723 struct axgbe_if_softc *sc;
3724 struct mii_data *mii;
3725 struct mii_softc *miisc;
3726 int ret;
3727
3728 sc = if_getsoftc(ifp);
3729 pdata = &sc->pdata;
3730
3731 axgbe_printf(2, "%s: Invoked\n", __func__);
3732 mtx_lock_spin(&pdata->mdio_mutex);
3733 mii = device_get_softc(pdata->axgbe_miibus);
3734 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3735 PHY_RESET(miisc);
3736 ret = mii_mediachg(mii);
3737 mtx_unlock_spin(&pdata->mdio_mutex);
3738
3739 return (ret);
3740 }
3741
3742 static void
xgbe_phy_exit(struct xgbe_prv_data * pdata)3743 xgbe_phy_exit(struct xgbe_prv_data *pdata)
3744 {
3745 if (pdata->axgbe_miibus != NULL)
3746 device_delete_child(pdata->dev, pdata->axgbe_miibus);
3747
3748 /* free phy_data structure */
3749 free(pdata->phy_data, M_AXGBE);
3750 }
3751
3752 static int
xgbe_phy_init(struct xgbe_prv_data * pdata)3753 xgbe_phy_init(struct xgbe_prv_data *pdata)
3754 {
3755 struct xgbe_phy_data *phy_data;
3756 int ret;
3757
3758 /* Initialize the global lock */
3759 if (!mtx_initialized(&xgbe_phy_comm_lock))
3760 mtx_init(&xgbe_phy_comm_lock, "xgbe phy common lock", NULL, MTX_DEF);
3761
3762 /* Check if enabled */
3763 if (!xgbe_phy_port_enabled(pdata)) {
3764 axgbe_error("device is not enabled\n");
3765 return (-ENODEV);
3766 }
3767
3768 /* Initialize the I2C controller */
3769 ret = pdata->i2c_if.i2c_init(pdata);
3770 if (ret)
3771 return (ret);
3772
3773 phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO);
3774 if (!phy_data)
3775 return (-ENOMEM);
3776 pdata->phy_data = phy_data;
3777
3778 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3779 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3780 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3781 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3782 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3783
3784 pdata->mdio_addr = phy_data->mdio_addr;
3785 DBGPR("port mode=%u\n", phy_data->port_mode);
3786 DBGPR("port id=%u\n", phy_data->port_id);
3787 DBGPR("port speeds=%#x\n", phy_data->port_speeds);
3788 DBGPR("conn type=%u\n", phy_data->conn_type);
3789 DBGPR("mdio addr=%u\n", phy_data->mdio_addr);
3790
3791 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3792 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3793 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3794 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3795 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3796
3797 if (phy_data->redrv) {
3798 DBGPR("redrv present\n");
3799 DBGPR("redrv i/f=%u\n", phy_data->redrv_if);
3800 DBGPR("redrv addr=%#x\n", phy_data->redrv_addr);
3801 DBGPR("redrv lane=%u\n", phy_data->redrv_lane);
3802 DBGPR("redrv model=%u\n", phy_data->redrv_model);
3803 }
3804
3805 DBGPR("%s: redrv addr=%#x redrv i/f=%u\n", __func__,
3806 phy_data->redrv_addr, phy_data->redrv_if);
3807 /* Validate the connection requested */
3808 if (xgbe_phy_conn_type_mismatch(pdata)) {
3809 axgbe_error("phy mode/connection mismatch "
3810 "(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type);
3811 return (-EINVAL);
3812 }
3813
3814 /* Validate the mode requested */
3815 if (xgbe_phy_port_mode_mismatch(pdata)) {
3816 axgbe_error("phy mode/speed mismatch "
3817 "(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds);
3818 return (-EINVAL);
3819 }
3820
3821 /* Check for and validate MDIO reset support */
3822 ret = xgbe_phy_mdio_reset_setup(pdata);
3823 if (ret) {
3824 axgbe_error("%s, mdio_reset_setup ret %d\n", __func__, ret);
3825 return (ret);
3826 }
3827
3828 /* Validate the re-driver information */
3829 if (xgbe_phy_redrv_error(phy_data)) {
3830 axgbe_error("phy re-driver settings error\n");
3831 return (-EINVAL);
3832 }
3833 pdata->kr_redrv = phy_data->redrv;
3834
3835 /* Indicate current mode is unknown */
3836 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3837
3838 /* Initialize supported features. Current code does not support ethtool */
3839 XGBE_ZERO_SUP(&pdata->phy);
3840
3841 DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode);
3842 switch (phy_data->port_mode) {
3843 /* Backplane support */
3844 case XGBE_PORT_MODE_BACKPLANE:
3845 XGBE_SET_SUP(&pdata->phy, Autoneg);
3846 XGBE_SET_SUP(&pdata->phy, Pause);
3847 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3848 XGBE_SET_SUP(&pdata->phy, Backplane);
3849 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3850 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
3851 phy_data->start_mode = XGBE_MODE_KX_1000;
3852 }
3853 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3854 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
3855 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3856 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3857 phy_data->start_mode = XGBE_MODE_KR;
3858 }
3859
3860 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3861 break;
3862 case XGBE_PORT_MODE_BACKPLANE_2500:
3863 XGBE_SET_SUP(&pdata->phy, Pause);
3864 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3865 XGBE_SET_SUP(&pdata->phy, Backplane);
3866 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
3867 phy_data->start_mode = XGBE_MODE_KX_2500;
3868
3869 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3870 break;
3871
3872 /* MDIO 1GBase-T support */
3873 case XGBE_PORT_MODE_1000BASE_T:
3874 XGBE_SET_SUP(&pdata->phy, Autoneg);
3875 XGBE_SET_SUP(&pdata->phy, Pause);
3876 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3877 XGBE_SET_SUP(&pdata->phy, TP);
3878 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3879 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3880 phy_data->start_mode = XGBE_MODE_SGMII_100;
3881 }
3882 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3883 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3884 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3885 }
3886
3887 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3888 break;
3889
3890 /* MDIO Base-X support */
3891 case XGBE_PORT_MODE_1000BASE_X:
3892 XGBE_SET_SUP(&pdata->phy, Autoneg);
3893 XGBE_SET_SUP(&pdata->phy, Pause);
3894 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3895 XGBE_SET_SUP(&pdata->phy, FIBRE);
3896 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
3897 phy_data->start_mode = XGBE_MODE_X;
3898
3899 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3900 break;
3901
3902 /* MDIO NBase-T support */
3903 case XGBE_PORT_MODE_NBASE_T:
3904 XGBE_SET_SUP(&pdata->phy, Autoneg);
3905 XGBE_SET_SUP(&pdata->phy, Pause);
3906 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3907 XGBE_SET_SUP(&pdata->phy, TP);
3908 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3909 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3910 phy_data->start_mode = XGBE_MODE_SGMII_100;
3911 }
3912 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3913 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3914 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3915 }
3916 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3917 XGBE_SET_SUP(&pdata->phy, 2500baseT_Full);
3918 phy_data->start_mode = XGBE_MODE_KX_2500;
3919 }
3920
3921 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3922 break;
3923
3924 /* 10GBase-T support */
3925 case XGBE_PORT_MODE_10GBASE_T:
3926 XGBE_SET_SUP(&pdata->phy, Autoneg);
3927 XGBE_SET_SUP(&pdata->phy, Pause);
3928 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3929 XGBE_SET_SUP(&pdata->phy, TP);
3930 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3931 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3932 phy_data->start_mode = XGBE_MODE_SGMII_100;
3933 }
3934 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3935 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3936 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3937 }
3938 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3939 XGBE_SET_SUP(&pdata->phy, 10000baseT_Full);
3940 phy_data->start_mode = XGBE_MODE_KR;
3941 }
3942
3943 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3944 break;
3945
3946 /* 10GBase-R support */
3947 case XGBE_PORT_MODE_10GBASE_R:
3948 XGBE_SET_SUP(&pdata->phy, Autoneg);
3949 XGBE_SET_SUP(&pdata->phy, Pause);
3950 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3951 XGBE_SET_SUP(&pdata->phy, FIBRE);
3952 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
3953 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
3954 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
3955 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
3956 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3957 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3958 phy_data->start_mode = XGBE_MODE_SFI;
3959
3960 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3961 break;
3962
3963 /* SFP support */
3964 case XGBE_PORT_MODE_SFP:
3965 XGBE_SET_SUP(&pdata->phy, Autoneg);
3966 XGBE_SET_SUP(&pdata->phy, Pause);
3967 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3968 XGBE_SET_SUP(&pdata->phy, TP);
3969 XGBE_SET_SUP(&pdata->phy, FIBRE);
3970 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3971 phy_data->start_mode = XGBE_MODE_SGMII_100;
3972 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3973 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3974 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3975 phy_data->start_mode = XGBE_MODE_SFI;
3976
3977 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3978
3979 xgbe_phy_sfp_setup(pdata);
3980 DBGPR("%s: start %d mode %d adv 0x%x\n", __func__,
3981 phy_data->start_mode, phy_data->phydev_mode,
3982 pdata->phy.advertising);
3983 break;
3984 default:
3985 return (-EINVAL);
3986 }
3987
3988 axgbe_printf(2, "%s: start %d mode %d adv 0x%x\n", __func__,
3989 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);
3990
3991 DBGPR("%s: conn type %d mode %d\n", __func__,
3992 phy_data->conn_type, phy_data->phydev_mode);
3993 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3994 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3995 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3996 phy_data->phydev_mode);
3997 if (ret) {
3998 axgbe_error("mdio port/clause not compatible (%d/%u)\n",
3999 phy_data->mdio_addr, phy_data->phydev_mode);
4000 return (-EINVAL);
4001 }
4002 }
4003
4004 if (phy_data->redrv && !phy_data->redrv_if) {
4005 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
4006 XGBE_MDIO_MODE_CL22);
4007 if (ret) {
4008 axgbe_error("redriver mdio port not compatible (%u)\n",
4009 phy_data->redrv_addr);
4010 return (-EINVAL);
4011 }
4012 }
4013
4014 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
4015
4016 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
4017 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
4018 (ifm_change_cb_t)axgbe_ifmedia_upd,
4019 (ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK,
4020 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
4021
4022 if (ret){
4023 axgbe_printf(2, "mii attach failed with err=(%d)\n", ret);
4024 return (-EINVAL);
4025 }
4026 }
4027
4028 DBGPR("%s: return success\n", __func__);
4029
4030 return (0);
4031 }
4032
4033 void
xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if * phy_if)4034 xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
4035 {
4036 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
4037
4038 phy_impl->init = xgbe_phy_init;
4039 phy_impl->exit = xgbe_phy_exit;
4040
4041 phy_impl->reset = xgbe_phy_reset;
4042 phy_impl->start = xgbe_phy_start;
4043 phy_impl->stop = xgbe_phy_stop;
4044
4045 phy_impl->link_status = xgbe_phy_link_status;
4046
4047 phy_impl->valid_speed = xgbe_phy_valid_speed;
4048
4049 phy_impl->use_mode = xgbe_phy_use_mode;
4050 phy_impl->set_mode = xgbe_phy_set_mode;
4051 phy_impl->get_mode = xgbe_phy_get_mode;
4052 phy_impl->switch_mode = xgbe_phy_switch_mode;
4053 phy_impl->cur_mode = xgbe_phy_cur_mode;
4054 phy_impl->get_type = xgbe_phy_get_type;
4055
4056 phy_impl->an_mode = xgbe_phy_an_mode;
4057
4058 phy_impl->an_config = xgbe_phy_an_config;
4059
4060 phy_impl->an_advertising = xgbe_phy_an_advertising;
4061
4062 phy_impl->an_outcome = xgbe_phy_an_outcome;
4063
4064 phy_impl->an_pre = xgbe_phy_an_pre;
4065 phy_impl->an_post = xgbe_phy_an_post;
4066
4067 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
4068 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
4069
4070 phy_impl->module_info = xgbe_phy_module_info;
4071 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
4072 }
4073