Searched refs:ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK (Results 1 – 2 of 2) sorted by relevance
363 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK); in zy7_pl_fclk_set_freq()413 div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >> in zy7_pl_fclk_get_freq()
154 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK (0x3f << 8) macro