Searched refs:ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT (Results 1 – 2 of 2) sorted by relevance
365 (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT); in zy7_pl_fclk_set_freq()414 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT; in zy7_pl_fclk_get_freq()
153 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT 8 macro