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Searched refs:_reg (Results 1 – 25 of 66) sorted by relevance

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/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_private.h34 #define BHND_PMU_READ_4(_sc, _reg) (_sc)->io->rd4((_reg), (_sc)->io_ctx) argument
35 #define BHND_PMU_WRITE_4(_sc, _reg, _val) \ argument
38 #define BHND_PMU_AND_4(_sc, _reg, _val) \ argument
39 BHND_PMU_WRITE_4((_sc), (_reg), \
40 BHND_PMU_READ_4((_sc), (_reg)) & (_val))
41 #define BHND_PMU_OR_4(_sc, _reg, _val) \ argument
42 BHND_PMU_WRITE_4((_sc), (_reg), \
43 BHND_PMU_READ_4((_sc), (_reg)) | (_val))
55 #define BHND_PMU_CCTRL_READ(_sc, _reg) \ argument
61 #define BHND_PMU_REGCTRL_READ(_sc, _reg) \ argument
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/freebsd/sys/dev/axgbe/
H A Dxgbe-common.h1509 _reg##_##_field##_INDEX, \
1510 _reg##_##_field##_WIDTH)
1519 _reg##_##_field##_INDEX, \
1535 _reg##_##_field##_WIDTH)
1560 _reg##_##_field##_WIDTH)
1564 _reg, (_val))
1619 _reg##_##_field##_WIDTH)
1639 _reg##_##_field##_WIDTH)
1662 _reg##_##_field##_WIDTH)
1695 _reg##_##_field##_WIDTH)
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/freebsd/sys/arm/altera/socfpga/
H A Dsocfpga_common.h31 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
32 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
33 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
34 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
35 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
36 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
/freebsd/sys/dev/sfxge/common/
H A Defx_impl.h993 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1010 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1023 (_reg ## _OFST + \
1034 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1053 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1062 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1085 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1101 ((_reg ## _OFST) + \
1119 ((_reg ## _OFST) + \
1133 ((_reg ## _OFST) + \
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/freebsd/sys/arm/freescale/vybrid/
H A Dvf_common.h29 #define READ4(_sc, _reg) \ argument
30 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
31 #define WRITE4(_sc, _reg, _val) \ argument
32 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
33 #define READ2(_sc, _reg) \ argument
34 bus_space_read_2(_sc->bst, _sc->bsh, _reg)
35 #define WRITE2(_sc, _reg, _val) \ argument
36 bus_space_write_2(_sc->bst, _sc->bsh, _reg, _val)
37 #define READ1(_sc, _reg) \ argument
38 bus_space_read_1(_sc->bst, _sc->bsh, _reg)
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H A Dvf_edma.h111 #define TCD_READ4(_sc, _reg) \ argument
112 bus_space_read_4(_sc->bst_tcd, _sc->bsh_tcd, _reg)
113 #define TCD_WRITE4(_sc, _reg, _val) \ argument
114 bus_space_write_4(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
115 #define TCD_READ2(_sc, _reg) \ argument
116 bus_space_read_2(_sc->bst_tcd, _sc->bsh_tcd, _reg)
117 #define TCD_WRITE2(_sc, _reg, _val) \ argument
118 bus_space_write_2(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
119 #define TCD_READ1(_sc, _reg) \ argument
120 bus_space_read_1(_sc->bst_tcd, _sc->bsh_tcd, _reg)
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H A Dvf_dmamux.h44 #define MUX_READ1(_sc, _mux, _reg) \ argument
45 bus_space_read_1(_sc->bst[_mux], _sc->bsh[_mux], _reg)
47 #define MUX_WRITE1(_sc, _mux, _reg, _val) \ argument
48 bus_space_write_1(_sc->bst[_mux], _sc->bsh[_mux], _reg, _val)
H A Dvf_ehci.c110 #define PHY_READ4(_sc, _reg) \ argument
111 bus_space_read_4(_sc->bst_phy, _sc->bsh_phy, _reg)
112 #define PHY_WRITE4(_sc, _reg, _val) \ argument
113 bus_space_write_4(_sc->bst_phy, _sc->bsh_phy, _reg, _val)
115 #define USBC_READ4(_sc, _reg) \ argument
116 bus_space_read_4(_sc->bst_usbc, _sc->bsh_usbc, _reg)
117 #define USBC_WRITE4(_sc, _reg, _val) \ argument
118 bus_space_write_4(_sc->bst_usbc, _sc->bsh_usbc, _reg, _val)
/freebsd/sys/dev/ath/
H A Dah_osdep.h91 #define OS_REG_UNSWAPPED(_reg) \ argument
92 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
93 ((_reg) >= 0x7000 && (_reg) < 0x8000))
95 #define OS_REG_UNSWAPPED(_reg) (0) argument
130 #define OS_BUS_BARRIER_REG(_ah, _reg, _t) \ argument
131 OS_BUS_BARRIER((_ah), (_reg), 4, (_t))
137 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) argument
138 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) argument
/freebsd/sys/dev/altera/pio/
H A Dpio.c57 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
58 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
59 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
60 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
61 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
62 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
/freebsd/sys/dev/beri/virtio/
H A Dvirtio.h31 #define READ2(_sc, _reg) \ argument
32 bus_read_2((_sc)->res[0], _reg)
33 #define READ4(_sc, _reg) \ argument
34 bus_read_4((_sc)->res[0], _reg)
35 #define WRITE2(_sc, _reg, _val) \ argument
36 bus_write_2((_sc)->res[0], _reg, _val)
37 #define WRITE4(_sc, _reg, _val) \ argument
38 bus_write_4((_sc)->res[0], _reg, _val)
/freebsd/sys/dev/altera/msgdma/
H A Dmsgdma.h68 #define READ4(_sc, _reg) \ argument
69 le32toh(bus_space_read_4(_sc->bst, _sc->bsh, _reg))
70 #define WRITE4(_sc, _reg, _val) \ argument
71 bus_space_write_4(_sc->bst, _sc->bsh, _reg, htole32(_val))
73 #define READ4_DESC(_sc, _reg) \ argument
74 le32toh(bus_space_read_4(_sc->bst_d, _sc->bsh_d, _reg))
75 #define WRITE4_DESC(_sc, _reg, _val) \ argument
76 bus_space_write_4(_sc->bst_d, _sc->bsh_d, _reg, htole32(_val))
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pci_hostb.c176 #define BHND_PCI_READ_2(_sc, _reg) \ argument
177 bhnd_bus_read_2(BHND_PCI_SOFTC(_sc)->mem_res, (_reg))
179 #define BHND_PCI_READ_4(_sc, _reg) \ argument
180 bhnd_bus_read_4(BHND_PCI_SOFTC(_sc)->mem_res, (_reg))
182 #define BHND_PCI_WRITE_2(_sc, _reg, _val) \ argument
185 #define BHND_PCI_WRITE_4(_sc, _reg, _val) \ argument
188 #define BHND_PCI_PROTO_READ_4(_sc, _reg) \ argument
191 #define BHND_PCI_PROTO_WRITE_4(_sc, _reg, _val) \ argument
194 #define BHND_PCI_MDIO_READ(_sc, _phy, _reg) \ argument
197 #define BHND_PCI_MDIO_WRITE(_sc, _phy, _reg, _val) \ argument
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/freebsd/sys/dev/etherswitch/mtkswitch/
H A Dmtkswitchvar.h128 #define MTKSWITCH_READ(_sc, _reg) \ argument
129 bus_read_4((_sc)->sc_res, (_reg))
130 #define MTKSWITCH_WRITE(_sc, _reg, _val) \ argument
131 bus_write_4((_sc)->sc_res, (_reg), (_val))
132 #define MTKSWITCH_MOD(_sc, _reg, _clr, _set) \ argument
133 MTKSWITCH_WRITE((_sc), (_reg), \
134 ((MTKSWITCH_READ((_sc), (_reg)) & ~(_clr)) | (_set))
/freebsd/sys/dev/flash/
H A Dcqspi.c80 #define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg) argument
81 #define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg) argument
82 #define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg) argument
83 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) argument
84 #define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val) argument
85 #define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val) argument
86 #define READ_DATA_4(_sc, _reg) bus_read_4((_sc)->res[1], _reg) argument
87 #define READ_DATA_1(_sc, _reg) bus_read_1((_sc)->res[1], _reg) argument
88 #define WRITE_DATA_4(_sc, _reg, _val) bus_write_4((_sc)->res[1], _reg, _val) argument
89 #define WRITE_DATA_1(_sc, _reg, _val) bus_write_1((_sc)->res[1], _reg, _val) argument
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312reg.h30 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); argument
31 #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) argument
/freebsd/sys/arm/freescale/imx/
H A Dimx6_audmux.c52 #define READ4(_sc, _reg) \ argument
53 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
54 #define WRITE4(_sc, _reg, _val) \ argument
55 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
/freebsd/sys/dev/dwc/
H A Dif_dwcvar.h118 #define READ4(_sc, _reg) \ argument
119 bus_read_4((_sc)->res[0], _reg)
120 #define WRITE4(_sc, _reg, _val) \ argument
121 bus_write_4((_sc)->res[0], _reg, _val)
/freebsd/sys/dev/iicbus/controller/vybrid/
H A Dvf_i2c.c87 #define READ1(_sc, _reg) bus_space_read_1(_sc->bst, _sc->bsh, _reg) argument
88 #define WRITE1(_sc, _reg, _val) bus_space_write_1(_sc->bst,\ argument
89 _sc->bsh, _reg, _val)
96 #define WRITE1(_sc, _reg, _val) ({\ argument
97 vf_i2c_dbg(_sc, "WRITE1 REG 0x%02X VAL 0x%02X\n",_reg,_val);\
98 bus_space_write_1(_sc->bst, _sc->bsh, _reg, _val);\
101 #define READ1(_sc, _reg) ({\ argument
102 uint32_t ret=bus_space_read_1(_sc->bst, _sc->bsh, _reg);\
103 vf_i2c_dbg(_sc, "READ1 REG 0x%02X RETURNS 0x%02X\n",_reg,ret);\
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipc_gpiovar.h107 #define CC_GPIO_UPDATE(_upd, _pin, _reg, _val) do { \ argument
108 (_upd)->_reg.mask |= (1 << (_pin)); \
110 (_upd)->_reg.value |= (1 << (_pin)); \
112 (_upd)->_reg.value &= ~(1 << (_pin)); \
/freebsd/sys/dev/xilinx/
H A Daxi_quad_spi.c64 #define READ4(_sc, _reg) \ argument
65 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
66 #define WRITE4(_sc, _reg, _val) \ argument
67 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
H A Daxidma.c62 #define READ4(_sc, _reg) \ argument
63 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
64 #define WRITE4(_sc, _reg, _val) \ argument
65 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
66 #define READ8(_sc, _reg) \ argument
67 bus_space_read_8(_sc->bst, _sc->bsh, _reg)
68 #define WRITE8(_sc, _reg, _val) \ argument
69 bus_space_write_8(_sc->bst, _sc->bsh, _reg, _val)
/freebsd/tools/tools/ath/common/
H A Dah_osdep.h59 #define OS_REG_WRITE(_ah, _reg, _val) argument
60 #define OS_REG_READ(_ah, _reg) 0 argument
/freebsd/sys/dev/mmc/host/
H A Ddwmmc_samsung.c45 #define WRITE4(_sc, _reg, _val) \ argument
46 bus_write_4((_sc)->res[0], _reg, _val)
/freebsd/sys/arm64/arm64/
H A Didentcpu.c312 #define MRS_FIELD_VALUE_NONE_IMPL(_reg, _field, _none, _impl) \ argument
313 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _none, ""), \
314 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _impl, #_field)
316 #define MRS_FIELD_VALUE_COUNT(_reg, _field, _desc) \ argument
317 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, "1 " _desc), \
318 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "2 " _desc "s"), \
319 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "3 " _desc "s"), \
320 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "4 " _desc "s"), \
332 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s")
2626 #define SHOULD_PRINT_REG(_reg) \ in print_cpu_features() argument
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