Searched refs:al_reg_read32 (Results 1 – 14 of 14) sorted by relevance
99 reg = al_reg_read32(cfg_1); in al_udma_m2s_axi_sm_set()111 reg = al_reg_read32(cfg_2); in al_udma_m2s_axi_sm_set()126 reg = al_reg_read32(cfg_max_beats); in al_udma_m2s_axi_sm_set()196 reg = al_reg_read32(cfg_1); in al_udma_s2m_axi_sm_set()208 reg = al_reg_read32(cfg_2); in al_udma_s2m_axi_sm_set()222 reg = al_reg_read32(cfg_max_beats); in al_udma_s2m_axi_sm_set()694 uint32_t reg = al_reg_read32( in al_udma_m2s_rlimit_set()717 uint32_t reg = al_reg_read32( in al_udma_m2s_rlimit_reset()756 reg = al_reg_read32(®s->mask); in al_udma_common_rlimit_set()955 conf->coal_timeout = al_reg_read32( in al_udma_m2s_comp_timeouts_get()[all …]
76 reg = al_reg_read32(®s->ctrl[group].int_control_grp); in al_iofic_moder_res_config()98 reg = al_reg_read32(®s->ctrl[group].int_control_grp); in al_iofic_legacy_moder_interval_config()121 reg = al_reg_read32(®s->grp_int_mod[group][vector].grp_int_mod_reg); in al_iofic_msix_moder_interval_config()198 reg = al_reg_read32(®s->ctrl[group].int_mask_grp); in al_iofic_mask()213 return al_reg_read32(®s->ctrl[group].int_mask_grp); in al_iofic_read_mask()226 return al_reg_read32(®s->ctrl[group].int_cause_grp); in al_iofic_read_cause()285 reg = al_reg_read32(®s->ctrl[group].int_control_grp); in al_iofic_interrupt_moderation_reset()
115 val = al_reg_read32(reg_addr); in al_udma_q_config()140 val = al_reg_read32(reg_addr); in al_udma_q_config_compl()156 val = al_reg_read32( in al_udma_q_config_compl()213 uint32_t reg = al_reg_read32(&udma_q->q_regs->rings.cfg); in al_udma_q_enable()387 uint32_t status = al_reg_read32(status_reg); in al_udma_q_reset()410 uint32_t dcp = al_reg_read32(dcp_reg); in al_udma_q_reset()411 uint32_t crhp = al_reg_read32(crhp_reg); in al_udma_q_reset()508 state_reg = al_reg_read32(&udma->udma_regs->m2s.m2s.state); in al_udma_state_get()510 state_reg = al_reg_read32(&udma->udma_regs->s2m.s2m.state); in al_udma_state_get()
61 al_dbg(PREFIX #REG " = 0x%08x" POSTFIX, al_reg_read32( \66 al_dbg(PREFIX #LBL " = " FMT POSTFIX, al_reg_read32( \72 al_dbg(PREFIX #LBL " = %d" POSTFIX, ((al_reg_read32( \
354 chip_id = al_reg_read32(&pbs_regs->unit.chip_id); in al_pcie_rev_id_get()471 info_0 = al_reg_read32(®s->app.debug->info_0); in al_pcie_check_link()573 reg = al_reg_read32(®s->port_regs->gen3_ctrl); in al_pcie_port_gen3_params_config()950 reg = al_reg_read32(®s->port_regs->iatu.cr2); in al_pcie_ecrc_gen_ob_atu_enable()952 reg = al_reg_read32(®s->port_regs->iatu.cr1); in al_pcie_ecrc_gen_ob_atu_enable()1331 reg = al_reg_read32(regs->axi.pcie_global.conf); in al_pcie_port_operating_mode_config()1529 reg = al_reg_read32(regs->axi.pcie_global.conf); in al_pcie_operating_mode_get()2055 lane_status = al_reg_read32(reg_ptr); in al_pcie_lane_status_get()2595 reg = al_reg_read32(®s->port_regs->iatu.cr1); in al_pcie_atu_region_get_fields()2753 reg_val = al_reg_read32(&aer_regs->header); in al_pcie_aer_config_aux()[all …]
177 static uint32_t al_reg_read32(uint32_t * offset);292 al_reg_read32(uint32_t *l) in al_reg_read32() function
178 temp = al_reg_read32(reg); in al_reg_write32_masked()
98 *data = al_reg_read32(®s_base->gen.reg_data); in al_serdes_25g_reg_read()967 reg = al_reg_read32(®s_base->lane[lane].stat); in al_serdes_25g_signal_is_detected()1031 reg_val = al_reg_read32(®s_base->gen.status); in al_serdes_25g_rx_equalization()1050 reg_val = al_reg_read32(®s_base->lane[lane].stat); in al_serdes_25g_rx_equalization()
440 return (al_reg_read32(&unit_regs->gen.dma_misc.revision) in al_udma_get_revision()
954 return al_reg_read32(®s_base->gen.reg_data); in al_serdes_grp_reg_read()1163 reg = al_reg_read32(&lane_regs->octl_multi); in al_serdes_eye_measure_run()1176 *value = al_reg_read32(&lane_regs->odat_multi_rxeq); in al_serdes_eye_measure_run()1910 if (al_reg_read32(®s_base->gen.irst) & SERDES_GEN_IRST_POR_B_A) { in al_serdes_mode_rx_tx_inv_state_save()1914 state->pipe_rst = al_reg_read32(®s_base->gen.irst); in al_serdes_mode_rx_tx_inv_state_save()1923 al_reg_read32(®s_base->lane[i].ipd_multi); in al_serdes_mode_rx_tx_inv_state_save()
633 (al_reg_read32(&udma_q->q_regs->rings.crhp) & in al_udma_cdesc_get_all()
1933 val = al_reg_read32(&adapter->mac_regs_base->gen.cfg); in al_eth_mdio_config()2007 *val = al_reg_read32( in al_eth_mdio_1g_mac_read()3926 al_reg_read32(&adapter->mac_regs_base->kr.pcs_data); in al_eth_link_status_clear()4033 octets = al_reg_read32(®_stats->ifInOctetsL); in al_eth_mac_stats_get()4040 octets = al_reg_read32(®_stats->ifOutOctetsL); in al_eth_mac_stats_get()4087 octets = al_reg_read32(®_rx_stats->ifOctetsL); in al_eth_mac_stats_get()4090 octets -= 4 * al_reg_read32(®_rx_stats->VLANOK); in al_eth_mac_stats_get()4094 octets = al_reg_read32(®_tx_stats->ifOctetsL); in al_eth_mac_stats_get()4097 octets -= 4 * al_reg_read32(®_tx_stats->VLANOK); in al_eth_mac_stats_get()4299 mux_sel = al_reg_read32(&mac_regs_base->gen.mux_sel); in al_eth_flr_rmn()[all …]
223 val = al_reg_read32(&adapter->mac_regs_base->kr.an_data); in al_eth_an_lt_reg_read()226 val = al_reg_read32(&adapter->mac_regs_base->kr.pma_data); in al_eth_an_lt_reg_read()242 val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_0_data); in al_eth_an_lt_reg_read()252 val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_1_data); in al_eth_an_lt_reg_read()262 val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_2_data); in al_eth_an_lt_reg_read()272 val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_3_data); in al_eth_an_lt_reg_read()
477 *val = al_reg_read32((void*)((u_long)handle + where)); in al_eth_fpga_read_pci_config()